KR20030056525A - Method for forming cell in a flat rom cell - Google Patents

Abstract

PURPOSE: A method for manufacturing a flat ROM(Read Only Memory) cell is provided to be capable of selectively forming a salicide layer by protecting an active region of a memory cell area except a contact portion using an anti-salicide layer and exposing a peripheral region of a logic area. CONSTITUTION: A plurality of gate electrodes made of a gate oxide layer(11) and a gate poly layer(12), are formed on a substrate. After sequentially depositing a nitride layer and an anti-salicide layer on the resultant structure, the anti-salicide layer is polished by carrying out a CMP(Chemical Mechanical Polishing) process until the nitride layer is exposed. After forming a photoresist pattern on the resultant structure, the anti-salicide layer exposed through the photoresist pattern, is removed by using a wet or dry etching process. After removing the photoresist pattern, the nitride layer is entirely etched. Then, a salicide layer(17) is selectively formed on the resultant structure.

Description

METHOD FOR FORMING CELL IN A FLAT ROM CELL

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating flat ROM cells, and in particular, to make it compatible with logic processes based on Dual Poly Gate and Salicide (Salicide; Self-Aligned silicide) processes. The present invention relates to a method for manufacturing a mask ROM cell in the form of a flat cell.

In general, a mask ROM is a type of nonvolatile device, and the necessary information is recorded by using a mask process in a manufacturing process of the device. In this case, the mask process for information recording is performed by an isolation process or a metal ( In some cases, the metal process may be performed, but most of the process may be performed by ion implantation into a channel region of a memory cell. In this case, a difference in threshold voltage occurs between a cell implanted with an ion and a cell not implanted with an ion implantation, and data is determined using this.

Conventional flat cell manufacturing processes do not require isolation, such as conventional LOCOS or STI, for isolation between memory cells. Therefore, such isolation exists only in the form of enclosing the entire memory cell array block, and there is no isolation pattern therein.

Source / drain junctions of memory cells are BN + (Buried N +) layers formed prior to the gate process, and isolation between junctions is not necessary. At this time, the contact for the BN + junction does not exist in the memory cell array, but exists in the segment select region.

As described above, due to the absence of isolation patterns and contacts in the memory cell, it is possible to make a highly integrated memory having a memory cell size of about 4F ² (F: minimum line width of photolithography). At this time, the isolation between the cells is not necessary in the flat cell process, and the gate is formed in a direction orthogonal to the BN + junction.

The width of the gate becomes the channel width of the memory cell. At this time, the adjacent channels need to be separated from each other, but the process is performed after the gate pattern fine, and thus does not affect the size of the memory cell at all. The flat cell process has a small number of additional processes compared to a conventional logic process, and is used when a very inexpensive memory is to be manufactured using a logic process.

On the other hand, flat cell processes that are compatible with logic processes prior to 0.35 μm have been commercialized, but flat cell processes that can be manufactured by 0.25 μm or 0.18 μm logic processes have not been developed.

A technical challenge in developing a flat cell process that is compatible with logic technology of 0.25 mu m or less arises from the problem of applying a dual gate process and a salicide process used in a logic process to a flat cell structure.

In addition, a portion of the active region, that is, the active contact region should be a salicide, which has a technical problem that is opposed to the fact that most regions of the active should not be salicide.

1 is a manufacturing process chart of a flat ROM cell according to the prior art.

First, an element isolation process is performed on the silicon substrate 1. Device isolation patterns are created only outside the memory cell array. Thereafter, the well 2 process is performed. In some cases, the order of the device isolation process and the well process may be reversed.

Next, a buffer oxide film for bit diffusion ion implantation is grown, and after forming the photosensitive film 4 for the pattern of the bit diffusion layer, bit diffusion ion implantation is performed. Bit diffusion ion implantation consists mainly of As + (FIG. 1A).

The annealing process is then performed to activate the implanted bit diffusion ions. In this process, the diffusion of the junction 5 of the bit diffusion layer and the bit diffusion oxide film 6 are formed thereon.

The bit diffusion oxide film 6 is grown to a thickness necessary to prevent loss of the bit diffusion layer junction by the subsequent process and to reduce the parasitic capacitance between the gate 8 and the junction 5 (FIG. 1B).

A gate oxide film 7 is formed and the gate 8 material is deposited. Such gate materials increase the thickness of the polysilicon or use tungsten silicide to reduce the resistance (FIG. 1C).

The gate 8 is patterned using photolithography and an etching process to generate a space 9 (FIG. 1D).

Next, LDD ion implantation is performed to form a source / drain junction of the peripheral circuit element, and the LDD spacer 10 is formed (FIG. 1E).

Then, source / drain ion implantation is performed. This process is necessary only for the peripheral circuit elements, and in the case of the memory cell, it is not necessary because the junction is already formed by the bit diffusion layer. Furthermore, since the silicon in the gap portion between the gate and the gate of the memory cell is exposed, the memory cell region should be blocked by the photoresist film during source / drain ion implantation.

Thereafter, a code mask and an ion implantation process for data recording are performed, and a process for planarization is performed. Normally this process is accomplished by BPSG deposition and etch back or CMP processes. By the ILD planarization process, the gap between the gates of the memory cells is filled by the gap fill film 11 (FIG. 1F).

Next, an active contact of the memory cell is formed by a contact process, and then a flat cell process is completed by forming a global bit line of the memory cell by a wiring process.

The technical problem that the conventional technique, as described above, may occur in a logic process of 0.25 μm or less, requires the salicide process to be combined to lower the gate resistance, and if the salicide process is performed immediately after the source / drain, Salicide is formed in the silicon exposed in the gap between the cell gates, causing short between adjacent BN + layers.

In order to solve the problems of the prior art as described above, the purpose is to protect the active area except the contact area of the memory cell area with a salicide barrier and the peripheral circuits of the gate part and the logic area of the memory cell It is an object of the present invention to provide a method for manufacturing a mask rom cell in the form of a flat cell in which salicide is formed by exposure.

According to an aspect of the present invention, there is provided a method of manufacturing a flat ROM cell, the method comprising: depositing a gate oxide film and a gate poly on a substrate and then patterning the gate; and depositing a nitride film and a salicide prevention film on the entire surface thereof. A second step of polishing the salicide barrier layer by a CMP process until the nitride layer is exposed; and a fourth step of performing a masking process of protecting the cell region with a photoresist layer and exposing an area to form salicide. And a fifth step of wet or dry removing the salicide preventing film exposed after the masking process, and a sixth step of etching the entire nitride film after removing the photosensitive film, and forming salicide on the exposed part of the resultant. A seventh step.

1 is a manufacturing process chart of a flat ROM cell according to the prior art,

2 is a manufacturing process chart of a flat ROM cell according to a first embodiment of the present invention;

3 is a manufacturing process diagram of a flat ROM cell according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11: gate oxide film 12: gate poly

13: nitride film 14: salicide prevention film

15 photosensitive film 17: salicide

There may be a plurality of embodiments of the present invention. Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. This embodiment allows for a better understanding of the objects, features and advantages of the present invention.

Referring to the technical gist of the present invention, the active region except for the contact region of the memory cell region is protected by the salicide barrier layer, and the peripheral circuits of the gate portion and the logic region of the memory cell are exposed to allow the salicide to be formed. To this end, the salicide barrier used to prevent salicide in the cell array region is removed using a CMP process. In this case, the process control is a spacer nitride layer.

That is, a stopper layer is required for the stability of the process when the CMP process is introduced. The present invention uses a spacer used to control the width of the N + / P + source / drain after gate formation as a stopper layer.

In order to prevent the diffusion of the salicide forming material, a TEO-based oxide film is used, and a nitride film having a physical strength different from that of the TEO-based oxide film is used as a spacer material used to control the width of the N + / P + source / drain.

In this way, the salicide formation in the peripheral circuit area removes the TEO-based oxide film by wet etching along with the masking process, thereby exposing the exposed nitride film by full dry etching.

On the other hand, the salicide formation at the upper end of the gate in the cell array region removes the TEO-based oxide film by the CMP process, thereby removing the exposed nitride film during full dry etching.

Next, the salicide prevention at the active of the cell array region is such that the TEO-based oxide film is protected by the mask process and remains intact, whereby the nitride film is also protected so that the cell at the time of forming salicide on the peripheral circuit and the gate of the cell array Array active is salicide resistant.

According to the present invention having the technical gist as described above, the cell array active prevents salicide in a minimal process, and the peripheral circuit and the upper part of the cell array gate can be salicided.

2 is a manufacturing process chart of a flat ROM cell according to a first embodiment of the present invention.

First, the isolation process and well formation are completed, the gate oxide film 11 and the gate poly 12 are deposited, and then a gate pattern is formed (FIG. 2A).

After the gate patterning, the gate etch recovery is performed to prevent damage to the active and gate sidewalls, and then an IMP process for forming an LDD is performed.

Then, the silicon surface and the gate poly 12 exposed portion are oxidized to a thickness of 40 to 100 GPa to relieve stress on the nitride film 13 in a subsequent process for preventing salicide.

Next, a nitride oxide film 13, which is a buffer oxide film and a CMP stopper layer, is deposited, and then a TEOS series oxide film, that is, a salicide prevention film 14, is deposited on the entire surface. It is preferable to deposit the thickness of the nitride film 13 at 300-1500 kPa here (FIG. 2B).

The CMP process is stopped in the nitride film 13, which is a CMP stopper layer, while removing the buffer oxide film and the salicide prevention film 14 by the CMP process (FIG. 2C).

Then, the photoresist film 15 is masked to pattern the salicide to the active region, and the salicide prevention film 14 exposed after the masking process is removed by wet or dry (FIG. 2D).

Next, the photosensitive film 15 is removed (FIG. 2E), and the exposed nitride film 13 is entirely dry etched (FIG. 2F).

As a result, the active and gate poly 12 are exposed in the peripheral circuit region to form the salicide 17, and only the top of the gate poly 12 is exposed in the cell array region to form the salicide 17.

On the other hand, the active of the cell array is protected by the salicide preventing film 14 and the nitride film 13, so that no salicide is formed.

3 is a manufacturing process chart of a flat ROM cell according to a second embodiment of the present invention.

In the manufacture of a mask rom, it is necessary to form a metal contact, i.e., a BN contact, in a particular cell, in which case the underlying layer, the active region, must be a salicide. Therefore, the active of the BN contact region should be exposed before forming the salicide. Conventionally, a mask process, an etching process, and a photoresist removal process are performed to expose the active of the BN contact region.

Therefore, in the second embodiment of the present invention, a photosensitive film 15 for exposing the active of the BN contact region is formed together when forming the salicide prevention pattern of FIG. 3C, and the BN contact is formed in a subsequent process as shown in FIG. 3G. Salicide 17 is formed in the active region to be formed.

The process description of the second embodiment of the present invention shown in FIGS. 3A to 3G can be sufficiently inferred from the description of the first embodiment of the present invention described with reference to FIGS. 2A to 2G, and thus the detailed description thereof will be omitted.

In the above description, but limited to the embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

The present invention described above enables a flat cell process that is fully compatible with standard logic processes of 0.25 μm or less design rules. In other words, a flat-cell device can be made using the dual gate / salicide process, which is the core of standard logic technology. Thus, existing logic device designers can easily design devices with flat cell memory, and can also easily build on logic processing lines.

In addition, there is an effect that can selectively form a salicide in the bit line contact region.

Claims (5)

A first step of patterning a gate after depositing a gate oxide film and a gate poly on the substrate, A second step of depositing a nitride film and a salicide prevention film on the entire surface; A third step of polishing the salicide barrier layer by a CMP process until the nitride layer is exposed; A fourth step of performing a masking process to protect the cell area with a photoresist and expose the area where the salicide is to be formed; A fifth step of removing the salicide film exposed by wet or dry after the masking process; A sixth step of etching the entire nitride film after removing the photosensitive film; And a seventh step of forming salicide at the exposed part of the resultant. The method of claim 1, wherein the fourth step And forming the salicide side together with the active region of the BN contact. The method of claim 1 or 2, wherein the second step The thickness of the nitride film is deposited at 300 to 1500 kPa, The manufacturing method of the platform cell characterized by the above-mentioned. The method according to claim 1 or 2, And after the gate patterning according to the first step, oxidizing the substrate and the gate poly exposed portion to a predetermined thickness. The method of claim 4, wherein The oxidation thickness is a method for producing a platform cell, characterized in that 40 to 100 kPa.