JP2003017583A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2003017583A
JP2003017583A JP2001196499A JP2001196499A JP2003017583A JP 2003017583 A JP2003017583 A JP 2003017583A JP 2001196499 A JP2001196499 A JP 2001196499A JP 2001196499 A JP2001196499 A JP 2001196499A JP 2003017583 A JP2003017583 A JP 2003017583A
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JP
Japan
Prior art keywords
gate electrode
formed
film
memory cell
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001196499A
Other languages
Japanese (ja)
Inventor
Takeshi Yoshida
毅 吉田
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2001196499A priority Critical patent/JP2003017583A/en
Publication of JP2003017583A publication Critical patent/JP2003017583A/en
Application status is Pending legal-status Critical

Links

Abstract

PROBLEM TO BE SOLVED: To form a silicide film on only a gate electrode in a DRAM cell area by forming a salicide structure in a logic circuit area. SOLUTION: The gate electrode 15 containing silicon is formed through a gate insulating film 14 on a substrate 11, an N type dispersion layer 17 being a source and drain area of a transistor is formed, a silicon oxidation film 18 is deposited on the whole face, furthermore after a photoresist film is formed, it is left in only a memory cell area, the silicon oxidation film 18 is etched by an RIE method, the silicon oxidation film 18 on a gate electrode upper part and in the neighborhood thereof is removed in the memory cell area, left on the side wall of the gate electrode in a peripheral circuit area, after the photoresist film is removed, a metal silicide film 21 is formed on the upper face of the gate electrode 15 and the surface of an N type dispersion layer 20 in the peripheral circuit area, and the metal silicide film 21 is formed on the upper part of the gate electrode 15 in the memory cell area.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell region where a memory cell transistor is formed and a peripheral circuit region where a peripheral transistor is formed, and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device in which a silicide film is formed on a gate electrode and a source / drain diffusion layer of a transistor in a peripheral circuit region to reduce resistance, and a method of manufacturing the same. 2. Description of the Related Art Recent semiconductor integrated circuits include an SOC (System On Chip) in which various kinds of circuits are mounted on one chip.
Has been actively developed. Among them, DRAM
The need for a DRAM embedded LOGIC chip integrating a cell and a LOGIC (peripheral) circuit is rapidly increasing. A problem when a DRAM cell is mixed with a LOGIC circuit is formation of a salicide structure. The salicide structure means that a metal silicide film is formed on a polysilicon gate electrode of a transistor and on a source / drain diffusion layer. In the LOGIC circuit, it is necessary to form a metal silicide film on the source and drain diffusion layers in order to reduce the parasitic resistance. But DR
In the AM cell, when a metal silicide film is formed on the source and drain diffusion layers of the transistor, the junction leak current increases, and the data retention characteristics of the cell deteriorate. In order to avoid this, conventionally, a method has been considered in which a DRAM material region is entirely covered with a mask material, and a salicide structure is formed only in the LOGIC circuit region without forming a salicide structure in the DRAM cell region. I have. However, in this method, since the gate electrode of the DRAM cell is formed only of polysilicon, there is a problem that the gate resistance increases and the access time of the DRAM deteriorates. [0006] As described above, DRA
In a conventional method in which a salicide structure is not formed in an M cell region but a salicide structure is formed only in a peripheral circuit region, DR
There has been a problem that the gate resistance of the AM cell increases and the access time of the DRAM deteriorates. The present invention has been made in view of the above circumstances, and has as its object to form a salicide structure in a peripheral circuit region to reduce parasitic resistance, and to form a gate electrode in a DRAM cell region on a gate electrode. An object of the present invention is to provide a semiconductor device capable of reducing gate resistance by forming a silicide film and a method for manufacturing the same. A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a memory cell region where a memory cell transistor is formed and a peripheral circuit region where a peripheral transistor is formed. There is provided a step of preparing a silicon semiconductor substrate, forming a groove in the substrate, and filling the groove with a first insulating film to form an element isolation region. A step of forming a gate electrode containing silicon; and a step of introducing a dopant into a surface region of the substrate using the element isolation region and the gate electrode as a mask to form a first diffusion layer serving as a source / drain region of a transistor. Depositing a second insulating film over the entire surface, forming a photoresist film over the entire surface, and patterning the photoresist film to form a photoresist film. Leaving a dist film only in the memory cell region, etching the second insulating film by an anisotropic etching method, and removing the second insulating film above the gate electrode and in the vicinity thereof in the memory cell region; Removing the second insulating film so as to leave the second insulating film on the side wall of the gate electrode in the peripheral circuit region; and removing the photoresist film, and then removing the upper part of the gate electrode in the peripheral circuit region. Reacting a surface of the first diffusion layer with a metal to form a metal silicide film, and in the memory cell region, reacting an upper portion of the gate electrode with the metal to form a metal silicide film. It is characterized by. A semiconductor device according to the present invention is a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed. The semiconductor device is formed in the memory cell region, and is formed on a gate electrode. A memory cell transistor having a metal silicide film formed thereon, and a transistor formed in the peripheral circuit region and having a metal silicide film formed on the gate electrode and on the source and drain diffusion layers, respectively. Embodiments of the present invention will be described below in detail with reference to the drawings. 1 (a), 1 (b) through 9 (a),
FIG. 2B shows the present invention using a DR in which a DRAM cell is formed.
LOG where AM cell area and peripheral transistor are formed
DRAM embedded L with IC circuit area (peripheral circuit area)
FIG. 4 is a cross-sectional view showing a manufacturing method in the case where the present invention is applied to an OGIC semiconductor integrated circuit in the order of steps. Each figure (a) shows a DRAM.
It is sectional drawing on the cell area side, and each figure (b) is sectional drawing on the LOGIC circuit area side. First, as shown in FIGS. 1A and 1B,
Semiconductor substrate, for example, P having a specific resistance of 4 to 6 Ω · cm
A silicon substrate (plane orientation (100)) 11 is prepared, and an STI (Shallow Trench Isolation)
After forming a plurality of trenches 12 for n), the inside of these trenches 12 is filled with a silicon oxide film (SiO 2 ) as an insulating film to form element isolation regions 13. Subsequently, the gate oxide film 14 having a thickness of about 10 nm is entirely formed by, for example, an oxidation method.
To form Next, as shown in FIGS. 2A and 2B,
Impurity-introduced polysilicon whose resistance has been reduced to 30
After being deposited to a thickness of about 0 nm, the polysilicon is patterned by using the well-known photolithography and RIE (Reactive Ion Etching) techniques to form a plurality of gate electrodes 1.
5 is formed. Next, as shown in FIGS. 3A and 3B,
The entire surface is oxidized to a thickness of, for example, 1
After a silicon oxide film 16 having a thickness of about 0 nm is formed, N-type impurity ions, for example, P ions, for example, 1 × 10 4 are formed using the element isolation region 13 and the gate electrode 15 as a mask.
A dose of about 14 (atoms / cm 2 ) is introduced into the substrate 11, and then the ion-implanted region is activated to
An N-type diffusion layer 17 having a shallow junction (Lightly Doped Drain) structure is formed. Next, as shown in FIGS. 4A and 4B,
In order to form a sidewall insulating film of a gate electrode of a transistor formed in the LOGIC circuit region, a silicon oxide film 18 is deposited on the entire surface to a thickness of, for example, about 100 nm by a method such as a CVD method. Next, as shown in FIGS. 5A and 5B,
A photoresist film 19 having a uniform thickness is applied and formed on the entire surface. At this time, the thickness of the photoresist film 19 is, for example, 400 nm so as to be smaller than the total thickness of the gate electrode 15 made of polysilicon and the silicon oxide film 18 for forming the sidewall insulating film. The following is assumed. By forming the photoresist film 19 with the above thickness, the surface of the silicon oxide film 18 existing on the uppermost part of the gate electrode 15 is exposed as shown in the figure. Next, the photoresist film 19 is patterned. At this time, the photoresist film 19 in the LOGIC circuit area is exposed to light, and then development processing is performed to leave the photoresist film 19 only in the DRAM cell area, as shown in FIGS. 6 (a) and 6 (b). Next, the silicon oxide film 18 is etched back by the RIE method having a high selectivity to silicon. As a result of this etch-back, as shown in FIGS.
In the GIC circuit region, the silicon oxide films 16 and 18 remain only on the side walls (sidewalls) of the gate electrode 15. In the DRAM cell region, the upper portion of the gate electrode 15 not covered with the photoresist film 19 and the silicon oxide film 16 and the silicon oxide film 18 near the gate electrode 15 are removed, and the upper portion of the gate electrode 15 is exposed. Become. Further, in the DRAM cell region, the N-type diffusion layer 17 is covered with the photoresist film 19 in advance, so that the silicon oxide film 18 remains on the upper portion even after the above-mentioned etch back is performed. Next, after removing the photoresist film 19, N-type impurity ions, for example, As ions,
A dose of about × 10 15 (atoms / cm 2 ) is introduced into the substrate 11 to activate the ion-implanted region. On this occasion,
As shown in FIGS. 8A and 8B, the area where the surface of the substrate 11 is exposed is the N-type diffusion layer 17 in the LOGIC circuit area.
Is only a part of the region, so that A
After s ions are introduced and activated, the N-type diffusion layer 17 is activated.
An N-type diffusion layer 20 having a junction deeper than the N-type diffusion layer is formed therein. Subsequently, after a metal, for example, Co is deposited on the entire surface by a sputtering method, annealing at about 600 ° C. is performed. When depositing Co, the upper surface of the gate electrode 15 made of polysilicon is exposed in the DRAM cell region, and the gate electrode 15 is formed in the LOGIC circuit region.
And the surface of the N-type diffusion layer 20 are exposed, so that silicon and Co react in these regions to form a metal silicide (CoSi) film 21. Thereafter, the whole is immersed in a mixture of sulfuric acid and hydrogen peroxide solution, and unreacted C
o is removed. Through the above steps, the DR
In the AM cell region, a gate electrode 15 having a metal silicide film 21 formed thereon and a pair of N-type diffusion layers 17 formed on the surface of the substrate located on both sides of the gate electrode 15 are formed.
Is formed as a source / drain diffusion layer. In the LOGIC circuit region, a gate electrode 15 having a metal silicide film 21 formed thereon and a substrate surface located on both side surfaces of the gate electrode 15 are formed. ,
A peripheral transistor is formed in which a pair of N-type diffusion layers 17 and 20 each having a metal silicide film 21 formed on the surface are used as source and drain diffusion layers having an LDD structure. Thereafter, as shown in FIGS. 9A and 9B, for example, an interlayer insulating film 22 made of, for example, PSG or BPSG is deposited on the entire surface, and each N-type diffusion layer 17 in the DRAM cell region is formed. Of wiring 23 leading to the surface of
The wiring 23 is formed on the source and drain diffusion layers of the C circuit region on the surface of each metal silicide film 21 and the like, and a stacked capacitor for data storage (not shown) is formed in the DRAM cell region. I do. As described above, according to the above embodiment, the LO
In the GIC circuit region, a metal silicide film 21 is formed on the gate electrode 15 and on the N-type diffusion layers 17 and 20 constituting source and drain diffusion layers, respectively, and a transistor having a salicide structure is formed. In the DRAM cell region, A cell transistor in which the metal silicide film 21 is formed on the gate electrode 15 is formed. As a result, in the LOGIC semiconductor integrated circuit incorporating the DRAM of the above embodiment, the parasitic resistance is reduced by forming the salicide structure in the LOGIC circuit region, and the silicide film is formed on the gate electrode in the DRAM cell region. As a result, gate resistance can be reduced, and high-speed cell access can be realized. Moreover, since no metal silicide film is formed on the diffusion layer of the cell transistor formed in the DRAM cell region, the junction leak current of the cell transistor can be suppressed, and the pause characteristics can be improved. It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified. For example, in the above-described embodiment, a case where a stack type capacitor is formed in the DRAM cell region has been described. However, in this case, a trench is formed in a substrate and a so-called trench capacitor for forming a capacitor for data storage is formed in the trench. You may do so. Since the method of forming the trench capacitor is well known and will not be described in particular, the trench for the STI is formed after the trench for the trench capacitor is formed on the substrate. In the above embodiment, the metal silicide film 2
Although the case where Co is used as a metal when forming No. 1 has been described, this is not limited to Co, and other high melting point metals, such as Ti and Ni, may be used. As described above, according to the present invention,
Provided is a semiconductor device and a method of manufacturing the same, in which a parasitic resistance can be reduced by forming a salicide structure in a peripheral circuit region, and a gate resistance can be reduced by forming a silicide film on a gate electrode in a DRAM cell region. Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a first step of a manufacturing method according to an embodiment of the present invention. FIG. 2 is a sectional view showing a step following FIG. 1; FIG. 3 is a sectional view showing a step following FIG. 2; FIG. 4 is a sectional view showing a step following FIG. 3; FIG. 5 is a sectional view showing a step following FIG. 4; FIG. 6 is a sectional view showing a step following FIG. 5; FIG. 7 is a sectional view showing a step following FIG. 6; FIG. 8 is a sectional view showing a step following FIG. 7; FIG. 9 is a sectional view showing a step following FIG. 8; [Description of Signs] 11: P-type silicon substrate, 12: trench, 13: element isolation region, 14: gate oxide film, 15: gate electrode, 16: silicon oxide film, 17: N-type diffusion layer, 18: silicon oxide Film 19: photoresist film 20: N-type diffusion layer 21: metal silicide (CoSi) film 22: interlayer insulating film 23: wiring

Claims (1)

  1. Claims 1. A method of manufacturing a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed, comprising: preparing a silicon semiconductor substrate; Forming a groove in the substrate, filling the groove with a first insulating film to form an element isolation region, and forming a gate electrode containing silicon on the substrate via a gate insulating film; Using the device isolation region and the gate electrode as a mask, introducing impurities into the surface region of the substrate to form a first diffusion layer serving as source and drain regions of the transistor; and depositing a second insulating film over the entire surface Forming a photoresist film on the entire surface; patterning the photoresist film so that the photoresist film is formed only in the memory cell region Etching the second insulating film by an anisotropic etching method, removing the upper part of the gate electrode and the second insulating film near the gate electrode in the memory cell region, and removing the gate electrode in the peripheral circuit region. The second insulating film is left on the side wall so as to leave the second insulating film.
    Removing the insulating film, and after removing the photoresist film, in the peripheral circuit region, a metal silicide film is formed by reacting a surface of the upper part of the gate electrode and the surface of the first diffusion layer with a metal, respectively.
    And forming a metal silicide film by reacting an upper portion of the gate electrode with a metal in the memory cell region. 2. When forming the photoresist film,
    2. The method according to claim 1, wherein said photoresist film is deposited to a thickness such that a surface of said second insulating film existing on an uppermost portion of said gate electrode is exposed. 3. When forming the photoresist film,
    2. The method of manufacturing a semiconductor device according to claim 1, wherein the deposition is performed so that the thickness is smaller than the total thickness of the gate electrode and the second insulating film. 4. An impurity is introduced into a part of the first diffusion layer in the peripheral circuit region to form a junction deeper than the first diffusion layer before the step of forming the metal silicide film. 2. The method according to claim 1, further comprising the step of forming a second diffusion layer. 5. When forming the metal silicide film,
    2. The method according to claim 1, wherein Co is used as the metal.
    The manufacturing method of the semiconductor device described in the above. 6. A semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed, wherein a metal silicide film is formed in the memory cell region and on a gate electrode. And a transistor formed in the peripheral circuit region and having a metal silicide film formed on each of a gate electrode and a source / drain diffusion layer.
JP2001196499A 2001-06-28 2001-06-28 Semiconductor device and its manufacturing method Pending JP2003017583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001196499A JP2003017583A (en) 2001-06-28 2001-06-28 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001196499A JP2003017583A (en) 2001-06-28 2001-06-28 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003017583A true JP2003017583A (en) 2003-01-17

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Family Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696048B2 (en) 2005-08-12 2010-04-13 Samsung Electronics Co., Ltd. Method of improving gate resistance in a memory array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696048B2 (en) 2005-08-12 2010-04-13 Samsung Electronics Co., Ltd. Method of improving gate resistance in a memory array

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