JP2003017583A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a silicide film on only a gate electrode in a DRAM cell area by forming a salicide structure in a logic circuit area. SOLUTION: The gate electrode 15 containing silicon is formed through a gate insulating film 14 on a substrate 11, an N type dispersion layer 17 being a source and drain area of a transistor is formed, a silicon oxidation film 18 is deposited on the whole face, furthermore after a photoresist film is formed, it is left in only a memory cell area, the silicon oxidation film 18 is etched by an RIE method, the silicon oxidation film 18 on a gate electrode upper part and in the neighborhood thereof is removed in the memory cell area, left on the side wall of the gate electrode in a peripheral circuit area, after the photoresist film is removed, a metal silicide film 21 is formed on the upper face of the gate electrode 15 and the surface of an N type dispersion layer 20 in the peripheral circuit area, and the metal silicide film 21 is formed on the upper part of the gate electrode 15 in the memory cell area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed and a manufacturing method thereof, and more particularly to a gate of a transistor in the peripheral circuit region. The present invention relates to a semiconductor device in which a silicide film is formed on an electrode and a source / drain diffusion layer to reduce the resistance, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Recent semiconductor integrated circuits include SOCs (System On Chip) in which various circuits are mounted on one chip.
The development of is becoming popular. Among them, DRAM
Demand for DRAM embedded LOGIC chips in which cells and LOGIC (peripheral) circuits are integrated is rapidly increasing.

A problem in mounting a DRAM cell together with a LOGIC circuit is formation of a salicide structure. The salicide structure is a structure in which a metal silicide film is formed on the polysilicon gate electrode of the transistor and on the source and drain diffusion layers, respectively. In the LOGIC circuit, it is necessary to form a metal silicide film on the source / drain diffusion layers in order to reduce the parasitic resistance. But DR
In the AM cell, when a metal silicide film is formed on the source / drain diffusion layers of the transistor, the junction leak current increases and the data retention characteristic of the cell deteriorates.

In order to avoid this, conventionally, a method of covering the entire DRAM cell region with a mask material and forming the salicide structure only in the LOGIC circuit region without forming the salicide structure in the DRAM cell region has been considered. There is.

However, in this method, since the gate electrode of the DRAM cell is formed only of polysilicon, there is a problem that the gate resistance increases and the access time of the DRAM deteriorates.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the conventional method of forming the salicide structure only in the peripheral circuit region without forming the salicide structure in the M cell region,
There is a problem that the gate resistance of the AM cell increases and the access time of the DRAM deteriorates.

The present invention has been made in consideration of the above circumstances, and its object is to reduce the parasitic resistance by forming a salicide structure in the peripheral circuit region and to reduce the parasitic resistance on the gate electrode in the DRAM cell region. It is an object of the present invention to provide a semiconductor device capable of reducing gate resistance by forming a silicide film and a method for manufacturing the same.

[0008]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed. A step of preparing a silicon semiconductor substrate, forming a groove in the substrate, and then filling the inside of the groove with a first insulating film to form an element isolation region, and including silicon through the gate insulating film on the substrate A step of forming a gate electrode, a step of introducing impurities into the surface area of the substrate using the element isolation region and the gate electrode as a mask to form a first diffusion layer to be a source and drain area of a transistor, The step of depositing the second insulating film, the step of forming a photoresist film on the entire surface, the patterning of the photoresist film, and the photoresist film above. The step of leaving only in the memory cell region, and etching the second insulating film by an anisotropic etching method to remove the second insulating film above the gate electrode and in the vicinity thereof in the memory cell region, and in the peripheral circuit region. Then, a step of removing the second insulating film so as to leave the second insulating film on the sidewall of the gate electrode, and, after removing the photoresist film, in the peripheral circuit region, the upper portion of the gate electrode and the first diffusion layer are formed. Forming a metal silicide film by reacting a surface of the layer with a metal and forming a metal silicide film by reacting an upper portion of the gate electrode with the metal in the memory cell region, respectively. .

A semiconductor device of the present invention is a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed, the semiconductor device being formed in the memory cell region and on a gate electrode. A memory cell transistor having a metal silicide film formed thereon and a transistor having a metal silicide film formed on the gate electrode and on the source and drain diffusion layers respectively are formed in the peripheral circuit region.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in detail with reference to the drawings.

1A, 1B to 9A,
(B) is a DR in which a DRAM cell is formed according to the present invention.
LOG in which AM cell region and peripheral transistor are formed
DRAM embedded L having an IC circuit area (peripheral circuit area)
FIG. 7 is a cross-sectional view showing the manufacturing method in the order of steps when implemented in an OGIC semiconductor integrated circuit. Each figure (a) is a DRAM
It is a sectional view of the cell region side, and each figure (b) is a sectional view of the LOGIC circuit region side.

First, as shown in FIGS. 1 (a) and 1 (b),
Semiconductor substrate, for example P having a resistivity of 4 to 6 Ω · cm
Type silicon substrate (plane orientation (100)) 11 is prepared, and STI (Shallow Trench Isolation) is performed on this substrate 11.
After forming a plurality of trenches 12 for n), the inside of these trenches 12 is filled with a silicon oxide film (SiO ₂ ) which is an insulating film to form an element isolation region 13. Then, the gate oxide film 14 having a thickness of about 10 nm is formed on the entire surface by, for example, an oxidation method.
To form.

Next, as shown in FIGS. 2 (a) and 2 (b),
The polysilicon which is made low resistance by introducing impurities is used.
After depositing a film having a film thickness of about 0 nm, this polysilicon is patterned by using well-known photolithography and RIE (Reactive Ion Etching) technology to form a plurality of gate electrodes 1.
5 is formed.

Next, as shown in FIGS. 3 (a) and 3 (b),
The entire surface is oxidized to form a film having a thickness of, for example, 1 on the surface of the gate electrode 15.
After the silicon oxide film 16 having a thickness of about 0 nm is formed, N-type impurity ions, for example P ions, for example, 1 × 10 4 are used by using the element isolation region 13 and the gate electrode 15 as a mask.
^The LDD is introduced into the substrate 11 with a dose amount of about ¹⁴ (atoms / cm ² ), and then the ion-implanted region is activated to perform LDD.
The N-type diffusion layer 17 having a shallow junction of (Lightly Doped Drain) structure is formed.

Next, as shown in FIGS. 4 (a) and 4 (b),
In order to form the sidewall insulating film of the gate electrode of the transistor formed in the LOGIC circuit region, the silicon oxide film 18 is deposited on the entire surface by a method such as the CVD method to a thickness of about 100 nm, for example.

Next, as shown in FIGS. 5 (a) and 5 (b),
A photoresist film 19 having a uniform film thickness is formed on the entire surface by coating. At this time, the thickness of the photoresist film 19 is, for example, 400 nm so as to be thinner than the total thickness of the gate electrode 15 made of polysilicon and the silicon oxide film 18 for forming the sidewall insulating film. Below. By forming the photoresist film 19 with the above film thickness, the surface of the silicon oxide film 18 existing on the uppermost portion of the gate electrode 15 is exposed as shown in the drawing.

Next, the photoresist film 19 is patterned. At this time, the photoresist film 19 in the LOGIC circuit region is exposed to light, and then a development process is performed to leave the photoresist film 19 only in the DRAM cell region as shown in FIGS. 6A and 6B.

Next, the silicon oxide film 18 is etched back by the RIE method having a high selection ratio with respect to silicon. By this etch back, as shown in FIGS. 7A and 7B, the LO film from which the photoresist film 19 has been removed.
In the GIC circuit region, the silicon oxide film 16 and the silicon oxide film 18 remain only on the side wall of the gate electrode 15.

In the DRAM cell region, the upper portion of the gate electrode 15 not covered with the photoresist film 19 and the silicon oxide film 18 and the silicon oxide film 18 in the vicinity thereof are removed so that the upper portion of the gate electrode 15 is exposed. Become. Further, in the DRAM cell region, since the N type diffusion layer 17 is covered with the photoresist film 19 in advance, the silicon oxide film 18 remains on the upper portion thereof even after the above etch back.

Next, after peeling off the photoresist film 19, N-type impurity ions such as As ions are added to, for example, 5 times.
It is introduced into the substrate 11 at a dose amount of about × 10 ¹⁵ (atoms / cm ² ) to activate the ion-implanted region. On this occasion,
As shown in FIGS. 8A and 8B, the region where the surface of the substrate 11 is exposed is the N-type diffusion layer 17 of each LOGIC circuit region.
Since there is only a partial area of
After the s ions are introduced and activated, the N-type diffusion layer 17 is formed.
An N-type diffusion layer 20 having a junction deeper than this N-type diffusion layer is formed therein. Then, after depositing a metal such as Co on the entire surface by a sputtering method, annealing is performed at about 600 ° C. When depositing this Co, the upper surface of the gate electrode 15 made of polysilicon is exposed in the DRAM cell region, and the gate electrode 15 is exposed in the LOGIC circuit region.
Since the upper surface of the N-type diffusion layer 20 and the surface of the N-type diffusion layer 20 are exposed, silicon and Co react with each other in these regions to form a metal silicide (CoSi) film 21. Then, the whole is soaked in a mixed solution of sulfuric acid and hydrogen peroxide water to remove unreacted C.
remove o.

Through the above steps, the DR
In the AM cell region, the gate electrode 15 on which the metal silicide film 21 is formed, and the pair of N-type diffusion layers 17 formed on the surface of the substrate located on both sides of the gate electrode 15.
Is formed as a source / drain diffusion layer. In the LOGIC circuit region, a gate electrode 15 on which a metal silicide film 21 is formed and a substrate surface located on both sides of the gate electrode 15 are formed. ,
A peripheral transistor is formed using the pair of N-type diffusion layers 17 and 20 each having the metal silicide film 21 formed on the surface as the source and drain diffusion layers of the LDD structure.

Thereafter, as shown in FIGS. 9A and 9B, for example, an interlayer insulating film 22 made of, for example, PSG or BPSG is deposited on the entire surface and each N type diffusion layer 17 in the DRAM cell region. Of the wiring 23 leading to the surface of the
Completed by forming a wiring 23 and the like that communicate with the surface of each metal silicide film 21 on the source and drain diffusion layers in the C circuit area, and further forming a stack type capacitor (not shown) for data storage in the DRAM cell area. To do.

As described above, according to the above embodiment, the LO
In the GIC circuit region, a metal silicide film 21 is formed on the gate electrode 15 and N-type diffusion layers 17 and 20 forming source and drain diffusion layers, a transistor having a salicide structure is formed, and a DRAM cell region is formed. A cell transistor in which the metal silicide film 21 is formed on the gate electrode 15 is formed.

As a result, in the DRAM-embedded LOGIC semiconductor integrated circuit of the above-described embodiment, the salicide structure is formed in the LOGIC circuit area, so that the parasitic resistance is reduced, and the silicide film is formed on the gate electrode in the DRAM cell area. By doing so, the gate resistance can be lowered, and high-speed cell access can be realized.

Moreover, since the metal silicide film is not formed on the diffusion layer of the cell transistor formed in the DRAM cell region, the junction leak current of the cell transistor can be suppressed and the pause characteristic becomes good.

It is needless to say that the present invention is not limited to the above embodiment and various modifications can be made. For example, in the above-described embodiment, the case of forming the stack type capacitor in the DRAM cell region has been described, but this forms a groove in the substrate and forms a so-called trench capacitor in which a capacitor for data storage is formed. You may do it. Although a method of forming the trench capacitor is well known and will not be particularly described, the groove for the STI is formed after the groove for the trench capacitor is formed on the substrate.

In the above embodiment, the metal silicide film 2 is used.
Although the case where Co is used as a metal when forming 1 has been described, this is not limited to Co, and other refractory metals such as Ti and Ni may be used.

[0028]

As described above, according to the present invention,
Provided is a semiconductor device in which parasitic resistance can be reduced by forming a salicide structure in a peripheral circuit region, and a gate resistance can be lowered by forming a silicide film on a gate electrode in a DRAM cell region, and a manufacturing method thereof. You can

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows FIG.

FIG. 3 is a cross-sectional view showing a step that follows FIG.

FIG. 4 is a cross-sectional view showing a step that follows FIG.

FIG. 5 is a cross-sectional view showing a step that follows FIG.

6 is a cross-sectional view showing a step that follows FIG.

FIG. 7 is a cross-sectional view showing a step that follows FIG.

FIG. 8 is a cross-sectional view showing a step that follows FIG.

FIG. 9 is a cross-sectional view showing a step that follows FIG.

[Explanation of symbols]

11 ... P-type silicon substrate, 12 ... groove, 13 ... Element isolation region, 14 ... Gate oxide film, 15 ... Gate electrode, 16 ... Silicon oxide film, 17 ... N-type diffusion layer, 18 ... Silicon oxide film, 19 ... Photoresist film, 20 ... N-type diffusion layer, 21 ... Metal silicide (CoSi) film, 22 ... Interlayer insulating film, 23 ... Wiring.

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed, wherein a silicon semiconductor substrate is prepared, and a groove is formed in the substrate. Then, a step of filling the groove with a first insulating film to form an element isolation region, a step of forming a gate electrode containing silicon on the substrate via a gate insulating film, the element isolation region and the gate Impurities are introduced into the surface region of the substrate using the electrodes as a mask to form a first diffusion layer to be the source and drain regions of the transistor; a step of depositing a second insulating film on the entire surface; A step of forming a resist film, a step of patterning the photoresist film to leave the photoresist film only in the memory cell region, and anisotropy The second insulating film is etched by a etching method to remove the second insulating film above and above the gate electrode in the memory cell region, and on the side wall of the gate electrode in the peripheral circuit region. Second to leave
A step of removing the insulating film, and after removing the photoresist film, in the peripheral circuit region, a metal silicide film is formed by reacting the upper portion of the gate electrode and the surface of the first diffusion layer with a metal,
And a step of reacting an upper portion of the gate electrode with a metal in the memory cell region to form a metal silicide film, the method of manufacturing a semiconductor device. 2. When forming the photoresist film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the photoresist film is deposited in such a thickness that the surface of the second insulating film existing on the uppermost part of the gate electrode is exposed. 3. When forming the photoresist film,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is deposited such that its film thickness is smaller than the total film thickness of the gate electrode and the second insulating film. 4. Before the step of forming the metal silicide film, impurities are introduced into a part of the first diffusion layer in the peripheral circuit region to form a junction deeper than the first diffusion layer. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a second diffusion layer. 5. When forming the metal silicide film,
2. Co is used as the metal.
A method for manufacturing a semiconductor device as described above. 6. A semiconductor device having a memory cell region in which a memory cell transistor is formed and a peripheral circuit region in which a peripheral transistor is formed, wherein a metal silicide film is formed on the gate electrode in the memory cell region. And a transistor formed in the peripheral circuit region and having metal silicide films formed on the gate electrode and the source and drain diffusion layers, respectively.