KR20040013293A - Semiconductor device and method for forming the same - Google Patents
Semiconductor device and method for forming the same Download PDFInfo
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- KR20040013293A KR20040013293A KR1020020046151A KR20020046151A KR20040013293A KR 20040013293 A KR20040013293 A KR 20040013293A KR 1020020046151 A KR1020020046151 A KR 1020020046151A KR 20020046151 A KR20020046151 A KR 20020046151A KR 20040013293 A KR20040013293 A KR 20040013293A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
Abstract
Description
본 발명은 반도체 장치 및 그의 제조방법에 관한 것으로서, 보다 구체적으로는 셀영역과 주변회로 및 코아영역에서의 콘택을 동시에 형성할 수 있는 디램소자 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a DRAM device and a method of manufacturing the same, which can simultaneously form contacts in a cell region, a peripheral circuit, and a core region.
디바이스의 셀피치가 감소함에 따라 게이트사이에 산화막으로 된 절연막을 갭필하는 것이 점점 더 어려워지고 있다. 특히 DRAM 소자는 로직소자(logic device)보다 패킹밀도(packing densitiy)가 훨씬 높기 때문에, 층간 절연막이 제대로 갭필되지 않게 되고, 이에 따라 SAC(self-aligned contact) 패드간에 브리지페일이 발생하는 문제점이 있었다.As the cell pitch of a device decreases, it becomes increasingly difficult to gapfill an insulating film made of an oxide film between gates. In particular, DRAM devices have much higher packing densities than logic devices, which prevents interlayer insulating films from gapping properly, resulting in bridge fail between self-aligned contact pads. .
도 1a 내지 도 1d는 종래의 반도체 장치의 DC(direct contact) 콘택을 형성하는 방법을 설명하기 위한 공정단면도를 도시한 것이다.1A to 1D are cross-sectional views illustrating a method of forming a direct contact (DC) contact of a conventional semiconductor device.
도 1a를 참조하면, 셀영역(101)과 주변회로 및 코아영역(102)으로 구분된 반도체 기판(100)에 통상적인 STI(shallow trench isolation) 공정으로 STI 소자분리막(110)을 형성한다.Referring to FIG. 1A, an STI device isolation layer 110 is formed in a conventional shallow trench isolation (STI) process in a semiconductor substrate 100 divided into a cell region 101, a peripheral circuit, and a core region 102.
이어서, 반도체 기판(100)상에 게이트 절연막(121), 게이트 전극물질(123) 및 질화막으로 된 캡핑층(125)으로 이루어진 게이트(120)가 형성되고, 상기 게이트(120)의 측벽에 게이트 스페이서(130)가 형성된다. 상기 게이트 캡핑층(125) 및 게이트 스페이서(130)는 질화막으로 이루어진다. 도면상에는 도시되지 않았으나, 상기 게이트(102) 양측의 기판에는 소오스/드레인을 위한 불순물영역이 형성되어 있다.Subsequently, a gate 120 including a gate insulating layer 121, a gate electrode material 123, and a capping layer 125 formed of a nitride layer is formed on the semiconductor substrate 100, and a gate spacer is formed on sidewalls of the gate 120. 130 is formed. The gate capping layer 125 and the gate spacer 130 are formed of a nitride film. Although not shown in the drawing, impurity regions for sources / drains are formed in the substrates on both sides of the gate 102.
도 1b를 참조하면, 기판전면에 HDP(high density plasma) 산화막, BPSG막, TOSZ막(hydropolysilizane의 상품명) 등과 같은 제1층간 절연막(140)을 기판전면에증착한 다음 평탄화시킨다. 이어서, 셀영역(101)의 제1층간 절연막(140)을 식각하여 SAC 콘택(145)을 형성한다.Referring to FIG. 1B, a first interlayer insulating layer 140 such as a high density plasma (HDP) oxide film, a BPSG film, a TOSZ film (trade name of hydropolysilizane), and the like is deposited on the front surface of the substrate and then planarized. Subsequently, the first interlayer insulating layer 140 of the cell region 101 is etched to form a SAC contact 145.
도 1c를 참조하면, 기판전면에 폴리실리콘막을 증착한 다음 CMP 공정을 수행하여 셀영역(101)의 상기 SAC 콘택(145)에 SAC 콘택패드(150)를 형성한다.Referring to FIG. 1C, a polysilicon film is deposited on the entire surface of a substrate, and then a SMP contact pad 150 is formed in the SAC contact 145 of the cell region 101 by performing a CMP process.
도 1d를 참조하면, 기판전면에 제2층간 절연막(160)을 증착한 다음 상기 셀영역(101)과 주변회로 및 코아영역(102)에 별도의 사진식각공정을 수행하여 DC 콘택(171), (173, 175)을 형성한다. 즉, 셀영역(101)에서는 콘택패드(150)를 노출시키는 DC 콘택(171)을 형성하고, 주변회로 및 코아영역(102)에서는 게이트(120)의 게이트 전극물질(123)과 기판(100)을 노출시키는 DC 콘택(173), (175)을 형성한다.Referring to FIG. 1D, a second interlayer insulating layer 160 is deposited on the front surface of the substrate, and then a separate photolithography process is performed on the cell region 101, the peripheral circuits, and the core region 102, thereby contacting the DC contact 171. (173, 175). That is, in the cell region 101, a DC contact 171 is formed to expose the contact pad 150. In the peripheral circuit and core region 102, the gate electrode material 123 and the substrate 100 of the gate 120 are formed. DC contacts 173 and 175 are formed to expose them.
상기한 바와같은 종래의 콘택형성방법은 셀영역(101)의 게이트간의 간격(space)이 좁은 경우, 제1층간 절연막(140)에 보이드가 발생하고, 후속의 콘택패드(150)를 위한 폴리실리콘막의 증착시 제1층간 절연막(140)에 발생된 보이드를 통해 브리지가 발생하는 문제점이 있었다.In the conventional contact forming method as described above, when the space between gates of the cell region 101 is narrow, voids are generated in the first interlayer insulating layer 140 and polysilicon for the subsequent contact pad 150 is formed. There was a problem in that the bridge was generated through the voids generated in the first interlayer insulating layer 140 during the deposition of the film.
또한, SAC 콘택(145)을 형성하기 위한 제1층간 절연막(140)의 식각시, 소오스/드레인용 불순물 영역이 식각손상되어 접합누설전류(junction leakage current)가 발생하는 문제점이 있었다.In addition, when the first interlayer insulating layer 140 for forming the SAC contact 145 is etched, source / drain impurity regions are etched to damage the junction leakage current.
또한, 셀영역(101)에서의 DC 콘택(171)과 주변회로 및 코아영역(102)에서의 DC 콘택(173), (175)을 별도의 사진식각공정을 통하여 형성하여 줌으로써, 공정이 복잡한 문제점이 있었다.In addition, by forming a DC contact 171 in the cell region 101 and DC contacts 173 and 175 in the peripheral circuit and core region 102 through a separate photolithography process, the process is complicated. There was this.
상기한 바와같은 종래 기술의 문제점을 해결하기 위하여, 증착컨포멀리티(deposition conformality)가 우수한 폴리실리콘막을 갭필하고, 소정부분의 폴리실리콘막이 식각된 부분에 층간 절연막을 채워준 다음 DC 콘택을 형성하는 방법이 제안되었다.In order to solve the problems of the prior art as described above, a method of gap filling a polysilicon film excellent in deposition conformality, filling the interlayer insulating film in a portion where the polysilicon film of the predetermined portion is etched, and then forming a DC contact This has been proposed.
상기한 방법은 폴리실리콘막을 갭필한 다음에 산화막으로 된 층간 절연막을 갭필하기 때문에, 층간 절연막에 보이드가 발생하여도 보이드에 의한 브리지는 발생되지 않으며, SAC 콘택을 형성하기 위한 층간 절연막의 식각공정이 배제되므로, 소오스/드레인 영역의 식각손상이 방지되어 접합누설전류를 방지할 수 있는 이점이 있다.Since the above method gap-fills the polysilicon film and then gapfills the interlayer insulating film made of oxide film, even if voids are generated in the interlayer insulating film, no bridge is caused by voids, and the etching process of the interlayer insulating film for forming the SAC contact is performed. Since it is excluded, etching damage of the source / drain regions is prevented, and thus there is an advantage that the junction leakage current can be prevented.
그러나, 상기한 종래의 콘택형성방법도 셀영역에서만 소오스/드레인 영역상에 폴리실리콘막을 채워주고, 주변회로 및 코아영역에서는 여전히 층간 절연막으로 갭필하여 주기 때문에, 별도의 사진식각공정을 수행하여 셀영역과 주변회로 및 코아영역에서 DC 콘택을 형성하여야 하는 문제점이 있었다.However, the conventional contact forming method described above also fills the polysilicon layer on the source / drain regions only in the cell region, and still gap-fills the interlayer insulating layer in the peripheral circuit and the core region, so that a separate photolithography process is performed. There was a problem in that the DC contact should be formed in the peripheral circuit and the core region.
본 발명의 목적은 상기한 바와같은 종래 기술의 문제점을 해결하기 위한 것으로서, 한번의 사진식각공정으로 셀영역과 주변회로 및 코아영역에서 콘택을 동시에 형성하여 공정을 단순화할 수 있는 반도체 장치 및 그의 제조방법을 제공하는 데 그 목적이 있다.Disclosure of Invention An object of the present invention is to solve the problems of the prior art as described above, and a semiconductor device capable of simplifying the process by simultaneously forming a contact in a cell region, a peripheral circuit, and a core region in one photolithography process and its manufacture The purpose is to provide a method.
본 발명의 다른 목적은 콘택저항 및 누설전류를 감소시킬 수 있는 반도체 장치 및 그의 제조방법을 제공하는 데 그 목적이 있다.Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can reduce contact resistance and leakage current.
도 1a 내지 도 1d는 종래의 반도체 장치의 DC 콘택을 형성하는 방법을 설명하기 위한 공정단면도,1A to 1D are cross-sectional views illustrating a method of forming a DC contact of a conventional semiconductor device;
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 장치의 DC 콘택을 형성하는 방법을 설명하기 위한 공정단면도,2A to 2G are cross-sectional views illustrating a method of forming a DC contact of a semiconductor device according to an embodiment of the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
200 : 반도체 기판 201 : 셀영역200: semiconductor substrate 201: cell region
202 : 주변회로 및 코아영역 210 : 소자분리막202: peripheral circuit and core region 210: device isolation film
220 : 게이트 230 : 게이트 스페이서220: gate 230: gate spacer
240 : 배리어 금속막 245, 255 : 실리사이드층240 barrier metal film 245, 255 silicide layer
260 : 개구부 270, 290 : 층간 절연막260: opening 270, 290: interlayer insulating film
280 : 금속막 291, 293, 295 : DC 콘택280: metal film 291, 293, 295: DC contact
이와 같은 목적을 달성하기 위한 본 발명은 소자분리막이 형성되고 셀영역과 주변회로 및 코아영역으로 구분된 반도체 기판상에 캡핑층과 스페이서를 구비한 게이트를 형성하는 단계와; 상기 소자분리막을 제외한, 상기 게이트사이의 노출된 기판에 제1실리사이드층을 형성하는 단계와; 상기 게이트사이의 기판상에 게이트에 의해 서로 분리되는 폴리실리콘막을 형성하는 단계와; 상기 소자분리막상의 폴리실리콘막을 식각하여 개구부를 형성하는 단계와; 상기 개구부에 제1층간 절연막을 갭필하는 단계와; 상기 폴리실리콘막을 실리사이드화하여 제2실리사이드층을 형성하는 단계와; 기판전면에 제2층간 절연막을 형성하는 단계와; 상기 셀영역상의 제2실리사이드층, 주변회로 및 코아영역의 게이트 및 반도체 기판을 노출시키는 콘택을 동시에 형성하는 단계를 구비하는 반도체 장치의 제조방법을 제공하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a device isolation layer including: forming a gate having a capping layer and a spacer on a semiconductor substrate divided into a cell region, a peripheral circuit, and a core region; Forming a first silicide layer on the exposed substrate between the gates, except for the device isolation layer; Forming a polysilicon film separated from each other by a gate on a substrate between the gates; Etching the polysilicon layer on the device isolation layer to form an opening; Gap-filling a first interlayer insulating film in the opening; Silicifying the polysilicon film to form a second silicide layer; Forming a second interlayer insulating film on the front surface of the substrate; And forming a contact for exposing a second silicide layer on the cell region, a peripheral circuit and a gate of the core region, and a semiconductor substrate at the same time.
또한, 본 발명은 소자분리막이 형성되고, 셀영역과 주변회로 및 코아영역으로 구분된 반도체 기판과; 상기 반도체 기판상에 형성되고, 상부와 측벽에 갭핑층 및 스페이서를 각각 구비한 게이트와; 상기 소자분리막을 제외한 상기 게이트사이의 기판에 형성된 제1실리사이드층과; 상기 소자분리막을 제외한 기판상에, 상기 게이트에 의해 서로 분리되도록 형성된 제2실리사이드층과; 상기 소자분리막상에 형성된 제1층간 절연막과; 기판전면에 형성되고, 상기 셀영역의 제2실리사이드층을 노출시키는 제1콘택, 상기 주변회로 및 코아영역의 게이트 및 기판을 각각 노출시키는 제2콘택 및 제3콘택을 구비하는 제2층간 절연막으로 이루어지는 반도체 장치를 제공하는 것을 특징으로 한다.In addition, the present invention provides a semiconductor device comprising: a semiconductor substrate on which an isolation layer is formed and divided into a cell region, a peripheral circuit and a core region; A gate formed on the semiconductor substrate and having a gapping layer and a spacer on top and sidewalls, respectively; A first silicide layer formed on a substrate between the gates other than the device isolation layer; A second silicide layer formed on the substrate other than the device isolation layer so as to be separated from each other by the gate; A first interlayer insulating film formed on the device isolation film; A second interlayer insulating layer formed on the entire surface of the substrate and having a first contact exposing the second silicide layer of the cell region, and a second contact and a third contact exposing the gate and the substrate of the peripheral circuit and the core region, respectively. It is characterized by providing a semiconductor device.
이하, 본 발명을 보다 구체적으로 설명하기 위하여 본 발명에 따른 실시예를 첨부 도면을 참조하면서 보다 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체 장치의 DC 콘택을 형성하는 방법을 설명하기 위한 공정단면도를 도시한 것이다.2A to 2G are cross-sectional views illustrating a method of forming a DC contact of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 셀영역(201)과 주변회로 및 코아영역(202)을 구비한 반도체 기판(200)에 통상적인 STI공정을 통하여 STI 소자분리막(210)을 형성하고, 상기 반도체 기판(200)상에 게이트 절연막(221), 게이트 전극물질(223) 및 캡핍층(225)으로 이루어진 게이트(220)를 형성한다.Referring to FIG. 2A, an STI device isolation layer 210 is formed on a semiconductor substrate 200 having a cell region 201, a peripheral circuit, and a core region 202 through a conventional STI process, and the semiconductor substrate 200 is formed. The gate 220 formed of the gate insulating layer 221, the gate electrode material 223, and the capping layer 225 is formed on the gate insulating layer 221.
이어서, 상기 게이트(220)의 측벽에 통상적인 스페이서 형성방법으로 스페이서(230)를 형성한다. 도면상에는 도시되지 않았으나, 상기 게이트 양측의 기판에는 소오스/드레인을 위한 불순물영역이 형성되어 있다. 상기 게이트 캡핑층(225)은 질화막으로 이루어지고, 상기 게이트 스페이서(230)는 산화막으로 이루어진다.Subsequently, the spacer 230 is formed on the sidewall of the gate 220 by a conventional spacer forming method. Although not shown in the drawing, impurity regions for sources / drains are formed on substrates on both sides of the gate. The gate capping layer 225 is formed of a nitride film, and the gate spacer 230 is formed of an oxide film.
도 2b 및 도 2c를 참조하면, 기판전면에 배리어 금속막(240)을 증착하고, 열처리하면 상기 배리어 금속막(240)과 콘택된 반도체 기판(201)의 표면이 실리사이드화(silicidation)되어 반도체 기판(201)의 표면에 실리사이드층(245)이 형성된다. 상기 실리사이드층(245)은 후속의 폴리실리콘막의 실리사이드화공정시 확산배리어(diffusion barrier)로서 작용하고, 소오스/드레인영역에서의 콘택직렬저항을 감소시켜 준다.Referring to FIGS. 2B and 2C, when the barrier metal film 240 is deposited on the entire surface of the substrate, when the heat treatment is performed, the surface of the semiconductor substrate 201 that is in contact with the barrier metal film 240 is silicided to form a semiconductor substrate. The silicide layer 245 is formed on the surface of the 201. The silicide layer 245 acts as a diffusion barrier in the subsequent silicidation process of the polysilicon layer, and reduces contact series resistance in the source / drain regions.
이어서, 나머지 반응하지 않고 남아있는 금속막(240)을 제거하고, 기판전면에 폴리실리콘막(250)을 증착한다. 이때, 폴리실리콘막(250)은 층간 절연막으로 사용되는 산화막보다 컨포멀리티(conformality)가 좋으므로 보이드없이 게이트(220)사이에 갭필되어진다. 상기 폴리실리콘막(250)을 풀(full) CMP하여 게이트사이에 서로 분리되도록 한다.Subsequently, the remaining metal film 240 remaining without reaction is removed, and the polysilicon film 250 is deposited on the entire surface of the substrate. In this case, since the polysilicon film 250 has better conformality than the oxide film used as the interlayer insulating film, the polysilicon film 250 is gap-filled between the gates 220 without voids. The polysilicon film 250 is full CMP to be separated from each other between gates.
도 2d를 참조하면, 셀영역(201)과 주변회로 및 코아영역(202)에서 트랜지스터를 분리하기 위하여 상기 소자분리막(210)이 노출되도록 상기 폴리실리콘막(250)을 식각하여 개구부(260)를 형성한다.Referring to FIG. 2D, the polysilicon layer 250 is etched to expose the device isolation layer 210 so as to separate the transistors in the cell region 201, the peripheral circuits, and the core region 202. Form.
도 2e를 참조하면, 상기 개구부(260)가 채워지도록 제1층간 절연막(270)을 기판전면에 증착한다. 이때, 상기 제1층간 절연막(270)을 갭필할 때, 보이드가 발생할 수도 있으나, 이미 폴리실리콘막이 형성되어 있으므로, 제1층간 절연막(270)의 보이드발생에 의한 브리지 페일은 발생되지 않는다.Referring to FIG. 2E, a first interlayer insulating layer 270 is deposited on the entire surface of the substrate to fill the opening 260. In this case, when gap filling the first interlayer insulating layer 270, voids may occur. However, since the polysilicon layer is already formed, a bridge fail due to void generation of the first interlayer insulating layer 270 is not generated.
상기 제1층간 절연막(270)을 CMP 또는 에치백하여 평탄화시키면 상기 개구부(260)내에 제1층간 절연막(270)이 형성된다. 종래에는 제1층간 절연막(140)을 평탄화한 다음 식각하여 SAC 콘택(145)을 형성하였기 때문에 기판 표면의 식각손상이 발생하였으나, 본 발명에서는 소자분리막(210)상부의 폴리실리콘막(250)을 식각하여 개구부(260)을 형성한 다음 제1층간 절연막(270)을 갭필하기 때문에, 기판표면의 식각손상이 방지된다.When the first interlayer insulating layer 270 is planarized by CMP or etch back, the first interlayer insulating layer 270 is formed in the opening 260. Conventionally, since the SAC contact 145 is formed by planarizing the first interlayer insulating layer 140 and then etching, the surface of the substrate is etched. However, in the present invention, the polysilicon layer 250 on the device isolation layer 210 is formed. Since the openings 260 are formed by etching and then the first interlayer insulating film 270 is gap-filled, etching damage to the surface of the substrate is prevented.
이어서, 기판전면에 실리사이드가 가능한 금속막(280)을 기판전면에 증착한다. 이때, 기판표면은 평탄화된 상태이므로, 상기 금속막(280)의 증착 균일도가 보다 향상된다. 이때, 상기 금속막(280)은 Ni 와 Pd 와 같이 실리콘내에서 확산이 잘되며, 가용성(solubility)이 높은 니어노블메탈(near noble metal)을 사용한다.Subsequently, a metal film 280 capable of silicide on the front surface of the substrate is deposited on the front surface of the substrate. At this time, since the substrate surface is flattened, the deposition uniformity of the metal film 280 is further improved. In this case, the metal film 280 is a good diffusion in silicon, such as Ni and Pd, and uses a noble metal (near noble metal) having high solubility.
도 2f를 참조하면, 상기 폴리실리콘막(250)이 완전히 실리사이드화(full silicidation)되도록 열처리하면, 상기 금속막(280)과 콘택된 폴리실리콘막(250)이 실리사이드층(255)으로 된다. 이어서, 반응하지 않고 남아있는 금속막(280)을 H2O2+H2SO4의 혼합용액으로 제거한다. 이때, 상기 실리사이드층(245)을 확산배리어로 이용하여 폴리실리콘막(250)이 실리사이드층(255)으로 되므로, 폴리실리콘막(250)내의 불순물이 기판으로 확산되는 것이 방지된다.Referring to FIG. 2F, when the polysilicon film 250 is heat-treated to be fully silicidated, the polysilicon film 250 contacted with the metal film 280 becomes the silicide layer 255. Subsequently, the metal film 280 remaining unreacted is removed with a mixed solution of H 2 O 2 + H 2 SO 4. At this time, since the polysilicon layer 250 is the silicide layer 255 using the silicide layer 245 as a diffusion barrier, impurities in the polysilicon layer 250 are prevented from being diffused to the substrate.
도 2g를 참조하면, 기판전면에 제2층간 절연막(290)을 증착한 다음 상기 제2층간 절연막(290)을 식각하여 셀영역(201)에 DC 콘택(291)을 형성함과 동시에 주변회로 및 코아영역(202)에 DC 콘택(293), (295)을 형성한다.Referring to FIG. 2G, a second interlayer insulating film 290 is deposited on the entire surface of the substrate, and then the second interlayer insulating film 290 is etched to form a DC contact 291 in the cell region 201, and at the same time, a peripheral circuit and DC contacts 293 and 295 are formed in the core region 202.
상기 셀영역(201)의 DC 콘택(291)은 상기 콘택패드용 실리사이드층(255)이 노출되도록 형성되고, 상기 주변회로 및 코아영역(202)의 DC 콘택(293)은 게이트(220)의 게이트전극물질(223)이 노출되도록 형성되며, 또한 상기 주변회로 및 코아영역(202)의 DC 콘택(295)은 상기 기판(200)이 노출되도록 형성된다.The DC contact 291 of the cell region 201 is formed to expose the silicide layer 255 for the contact pad, and the DC contact 293 of the peripheral circuit and the core region 202 is a gate of the gate 220. The electrode material 223 is formed to be exposed, and the DC contact 295 of the peripheral circuit and the core region 202 is formed to expose the substrate 200.
본 발명의 실시예에서는, 상기 셀영역(201)의 DC 콘택(291)과 상기 주변회로 및 코아영역(202)의 DC 콘택(293), (295)에 의해 노출되는 실리사이드층(255), (245)이 상기 게이트(220)의 갭핑층(225)으로 사용된 질화막과 높은 선택비를 갖기 때문에, 한번의 사진식각공정으로 셀영역(201)과 주변회로 및 코아영역(202)에서의 DC 콘택(291), (293), (295)을 동시에 형성할 수 있다.In an embodiment of the present invention, the silicide layers 255 and 255 exposed by the DC contacts 291 of the cell region 201 and the DC contacts 293 and 295 of the peripheral circuit and core region 202. Since the 245 has a high selectivity with the nitride film used as the gapping layer 225 of the gate 220, the DC contact in the cell region 201, the peripheral circuit and the core region 202 in one photolithography process. 291, 293, and 295 can be formed at the same time.
상기한 바와같은 본 발명에 따르면, 셀영역과 주변회로 및 코아영역에 폴리실리콘막을 형성하고, 소자분리영역이 형성된 부분만 폴리실리콘막을 제거하여 층간 절연막을 갭필하여 줌으로써, 셀영역과 주변회로 및 코아영역에서 DC 콘택을 동시에 형성하여 줄 수 있다. 또한, 기판표면의 식각손상을 방지하여 접합누설전류를 방지할 수 있을 뿐만 아니라 마이크로 브리지의 발생을 방지할 수 있는 이점이 있다.According to the present invention as described above, by forming a polysilicon film in the cell region, the peripheral circuit and the core region, and by removing the polysilicon film only in the portion where the device isolation region is formed, by gap-filling the interlayer insulating film, the cell region and the peripheral circuit and core DC contacts can be formed simultaneously in the region. In addition, by preventing the etching damage of the surface of the substrate to prevent the junction leakage current, there is an advantage that can prevent the occurrence of the micro bridge.
또한, 기판의 소오스/드레인 영역과 실리사이드층이 콘택되므로, 콘택직렬저항을 낮출 수 있는 이점이 있다.In addition, since the source / drain regions of the substrate and the silicide layer are contacted, there is an advantage that the contact series resistance can be lowered.
상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.
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| US7709375B2 (en) | 2007-03-16 | 2010-05-04 | Hynix Semiconductor Inc. | Semiconductor device including contact pattern and method for fabricating the same |
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