JPH11307474A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a diffusion of copper into a semiconductor substrate or an element when a copper or copper alloy wire is used, of realizing high reliability and excellent characteristic, and of contriving to simplify a manufacture process, and its manufacture. SOLUTION: An element such as an n channel MOSFET, a p channel MOSFET or the like is provided on one main face of a semiconductor substrate 1, and a diffusion prevention film 11 such as SiN film is provided on the one main face where the element of the semiconductor substrate 1 is provided. An interlayer insulation film 12 such as, an SiO2 film is provided on the diffusion prevention film 11, and a wiring channel 13 and a connection hole 14 are provided in the interlayer insulation film 12. A diffusion prevention film 15 such as an SiN film is provided on a side face of the wiring channel 13 and the connection hole 14, and also a Cu film constituting a Cu channel wiring 17 is buried via a TiN/Ti film 16 as an underlayer barrier metal inside the wiring channel 13 and the connection hole 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having copper or copper alloy wiring and a method of manufacturing the same.

[0002]

2. Description of the Related Art ULSI (Ultra Large Scale Integrat)
In highly integrated semiconductor devices such as ed-circuits, not only demands for high-speed devices, but also high reliability for wiring electromigration, which is becoming more serious due to increased power consumption, is required. .

Since the operation speed of a device is generally represented by an RC delay time, the wiring capacitance C is improved by lowering the dielectric constant of an interlayer insulating film, and the wiring resistance R is reduced by a low-resistance metal.
Is required. Common aluminum (Al) alloy as an LSI wiring material, for example, Al-0.5
% Cu alloy or Al-1% Si alloy has a specific resistance of 2.5 to 3.2 μΩcm. In contrast, copper (C
u) has a specific resistance of 1.8 μΩcm, is lower in specific resistance than the above-described Al alloy, and is advantageous in increasing the speed of a device when used as a wiring material. Further, the Cu wiring has about 2-3 times higher electromigration resistance than the Al alloy wiring, and is also excellent in reliability.

[0004]

SUMMARY OF THE INVENTION However, Cu
Is easily diffused into a silicon (Si) substrate or a silicon dioxide (SiO ₂ ) film even at a relatively low temperature. For example, when a Cu wiring is used in a semiconductor device such as a MOSFET, Cu in the wiring is , The gate insulating film is broken by diffusion into the SiO ₂ film used as the gate insulating film or the interlayer insulating film in the Si substrate,
There is a problem of causing a threshold variation of T, a junction leak of the device, and the like.

On the other hand, a so-called grooved wiring technique has been actively studied as a method for realizing finer wiring by a simpler process. Here, the term “groove wiring” refers to a method in which a predetermined wiring groove is formed in a wiring forming portion of an interlayer insulating film, and a film is formed while embedding a wiring material such as Cu or a Cu alloy in the inside of the wiring groove. A wiring formed by removing a wiring material formed in a portion other than the wiring groove by a polishing (CMP) method or the like and leaving the wiring material only inside the wiring groove.

[0006] In a trench wiring made of Cu or a Cu alloy, the upper portion is usually capped with a conductive film for preventing the diffusion of Cu in order to prevent the diffusion of Cu. However, it is not always easy to realize a structure in which the upper portion of the trench wiring is capped with another conductive film, and there is a problem that the manufacturing process becomes complicated.

Therefore, an object of the present invention is to prevent the diffusion of copper into a semiconductor substrate or an element when copper or a copper alloy wiring is used, thereby realizing high reliability and good characteristics. It is another object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device, which can simplify the manufacturing process.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor substrate having an element provided on one main surface, and a device covering the element on one main surface of the semiconductor substrate. A semiconductor device having an interlayer insulating film provided as described above, and copper or copper alloy wiring buried in wiring trenches and / or connection holes provided in the interlayer insulating film. A diffusion preventing film for preventing copper diffusion is provided between the interlayer insulating film and the interlayer insulating film.

A method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of forming a diffusion prevention film for preventing diffusion of copper on one main surface of a semiconductor substrate having an element formed on one main surface. Forming an interlayer insulating film on the diffusion preventing film, forming a wiring groove and / or connection hole in the interlayer insulating film, and embedding copper or copper alloy wiring inside the wiring groove and / or connection hole. And characterized in that:

[0010] In the present invention, as the diffusion preventing film,
Typically, for example, a silicon nitride film is used. Also,
As the semiconductor substrate, for example, a silicon substrate is typically used, and as the interlayer insulating film, for example, a silicon dioxide film is typically used.

In the present invention, the element is typically
For example, a field-effect transistor including a gate insulating film on a semiconductor substrate, a gate electrode on the gate insulating film, and a diffusion layer in the semiconductor substrate on both sides of the gate electrode, other than this, for example, a bipolar transistor or It may be a diode or the like. Further, a plurality of elements may be provided on the semiconductor substrate, and in this case, different elements such as a field effect transistor and a bipolar transistor may be mounted together.

According to the present invention constructed as described above, diffusion prevention for preventing diffusion of copper between one main surface of a semiconductor substrate having an element provided on one main surface and an interlayer insulating film. The provision of the film can prevent copper contained in the copper or copper alloy wiring from diffusing into the element and the semiconductor substrate. Thereby, the reliability of the semiconductor device can be improved, and the characteristics can be prevented from being deteriorated due to the diffusion of copper. In addition, since the diffusion preventing film prevents the diffusion of copper into the element and the semiconductor substrate, it is not necessary to provide a cap film for preventing the diffusion of copper above the copper or copper alloy wiring. Simplification can be achieved.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. This semiconductor device has an n-channel MOSFET and a p-channel MOSFET on a semiconductor substrate.
It is a CMOS integrated circuit (IC) provided with ET.

As shown in FIG. 1, in this semiconductor device, a semiconductor substrate 1 such as a low-resistance Si substrate is used.
, A p-well 2 and an n-well 3 are provided. A field insulating film 4 made of, for example, a SiO ₂ film is selectively provided on the surface of the semiconductor substrate 1, thereby separating elements. Below the field insulating film 4 in the p well 2, for example, a p ⁺ type channel stop region (not shown) is provided.

On the surface of the active region surrounded by the field insulating film 4, a gate insulating film 5 such as a SiO ₂ film is provided. On the gate insulating film 5, for example, a polycrystalline Si film 6a and a tungsten silicide (WSi
₂ ) A gate electrode 6 having a so-called polycide structure comprising the film 6b is provided. The gate electrode 6 constitutes the lowermost (first layer) wiring. The thickness of the polycrystalline Si film 6a forming the gate electrode 6 is, for example, 70 nm, and the thickness of the WSi ₂ film 6b is, for example, 100 nm.
The polycrystalline Si film 6a is heavily doped with an n-type impurity such as phosphorus (P) in order to reduce the resistance value. On the gate electrode 6, an offset insulating film 7 such as a SiO ₂ film having the same shape as the gate electrode 6 is provided. The thickness of the offset insulating film 7 is, for example, 150 nm. Sidewall spacers 8 made of, for example, SiO ₂ are provided on side surfaces of the gate electrode 6 and the offset insulating film 7.

In the p-well 2 n-channel MOSFET formation region, a gate electrode 6 and a sidewall spacer 8 are provided in an active region surrounded by the field insulating film 4.
An n ⁺ -type source region 9 and a drain region 10 are provided in a self-aligned manner. These source regions 9
And a drain region 10, respectively, n in the lower portion of the side wall spacers 8 ^- type lightly doped portion 9
a and 10a. A gate insulating film 5, a gate electrode 6,
n ⁺ type source region 9 and n ⁺ type drain region 10
Form an n-channel MOSFET. Although not shown in FIG. 1, a p ⁺ -type diffusion layer is provided in the active region surrounded by the field insulating film 4 in the well contact diffusion layer formation region of the p well 2.

On the other hand, although not shown in FIG.
In the p-channel MOSFET formation region of well 3,
In the active region surrounded by the field insulating film 4, p ⁺ -type source and drain regions are provided in self-alignment with the gate electrode 6 and the sidewall spacer 8. These source and drain regions are
Each of the lower portions of the sidewall spacers 8 has n
^- having a low impurity concentration portion of the mold. The gate insulating film 5, the gate electrode 6, the p ⁺ -type source region and the p ⁺ -type drain region constitute a p-channel MOSFET.
In addition, in the well contact diffusion layer forming region of the n well 3, an n ⁺ type diffusion layer is provided in an active region surrounded by the field insulating film 4.

As described above, one main surface of the semiconductor substrate 1
N-channel MOSFET and p-channel MOSFET
Is provided. Then, in the semiconductor device, the semiconductor substrate 1 is covered so as to cover the surface on the one main surface side.
That is, the insulating diffusion film made of, for example, a 100-nm-thick SiN film covers the offset insulating film 7 on the gate electrode 6, the sidewall spacers 8, the gate insulating film 5 on both sides of the gate electrode 6, and the field insulating film 4. The prevention film 11 is provided. The diffusion preventing film 11 is for preventing Cu as a wiring material from diffusing into the semiconductor substrate 1 provided with the n-channel MOSFET and the p-channel MOSFET. On the diffusion preventing film 11, an interlayer insulating film 12 such as a SiO ₂ film is provided. The surface of the interlayer insulating film 12 is substantially flat, and the thickness of the interlayer insulating film 12 on the semiconductor substrate 1 corresponding to the active region is, for example, 1200 nm.

In a predetermined portion of the interlayer insulating film 12, a wiring groove 13 for forming a groove wiring is provided. Reference numeral 14 denotes a diffusion layer provided in the semiconductor substrate 1 such as a source region and a drain region, and a connection hole to a gate electrode 6 which is a first-layer wiring. These connection holes 14 are n-channel MOS
A predetermined portion above the source region 9 and the drain region 10 of the FET, a predetermined portion above the source region and the drain region (both not shown) of the p-channel MOSFET, and ap ⁺ -type diffusion layer for a well contact of the p well 2 ( (Not shown) and in the interlayer insulating film 12, diffusion preventing film 11, and gate insulating film 5 in a predetermined portion above the n ⁺ -type diffusion layer (not shown) for the well contact of the n-well 3. And is provided on the interlayer insulating film 12, the diffusion preventing film 11 and the offset insulating film 7 in a predetermined portion above the gate electrode 6. These connection holes 14 are provided at the bottom of the wiring groove 13.

On the side surface of the wiring groove 13 and the side surface of the connection hole 14, an insulating diffusion prevention film 15 such as a SiN film having a thickness of, for example, about 10 nm is provided. These diffusion preventing films 15 are formed by the Cu of the wiring material
And to prevent diffusion into the interlayer insulating film 12 through the side surface of the connection hole 14. As described above, for example, a Cu groove wiring 17 is buried in the inside of the wiring groove 13 and the connection hole 14 provided with the diffusion prevention film 15 on the side surface, for example, using the TiN / Ti film 16 as a base barrier metal. The Cu groove wiring 17 forms a second-layer wiring. Here, the TiN / Ti film 16 is formed of C
It has a function of preventing u from diffusing into the interlayer insulating film 12 and the semiconductor substrate 1 through the side surfaces and the bottom of the wiring groove 13 and the connection hole 14. The thickness of the Ti film constituting the TiN / Ti film 16 is, for example, 30 nm.
The thickness of the TiN film is, for example, 70 nm.

Although not shown, when a third layer wiring is provided above the Cu trench wiring 17 in this semiconductor device, an interlayer insulating film such as a SiO ₂ film is provided on the interlayer insulating film 12. Can be A wiring groove and a connection hole are provided in a predetermined portion of the interlayer insulating film, and a Cu groove wiring, for example, which forms a third-layer wiring, is embedded in the wiring groove and the connection hole. To realize a multilayer wiring structure, the above-described structure is repeated.

Next, the method for fabricating the semiconductor device according to this embodiment will be explained.

As shown in FIG. 2, a p-well 2 and an n-well 3 are formed adjacent to each other in a semiconductor substrate 1 such as a Si substrate. Specifically, first, an oxide film (not shown) is formed by thermally oxidizing the surface of the semiconductor substrate 1. Next, a resist pattern (not shown) having a predetermined shape is formed on the oxide film to cover the surface of the p-well formation region.
Using this resist pattern as a mask, an n-type impurity such as phosphorus (P) is ion-implanted, for example, at an implantation energy of 50 keV and a dose of 1 × 10 ¹² to 10 ×.
Doping is performed under the condition of 10 ¹² cm ^-2 .

Next, after removing the resist pattern, a resist pattern of a predetermined shape covering the surface of the n-well forming region is formed on the oxide film, and using this resist pattern as a mask, boron (B) is ion-implanted, for example. )
A p-type impurity such as
V. Doping is performed under the conditions of a dose of 1 × 10 ¹² to 10 × 10 ¹² cm ⁻² . Next, after removing the resist pattern, the implanted impurities are electrically activated by performing a heat treatment at a temperature of, for example, 1150 ° C. for 3 hours. As a result, a p-well 2 is formed in the region doped with the p-type impurity, and an n-well 3 is formed in the region doped with the n-type impurity.

Next, after the oxide film formed on the surface of the semiconductor substrate 1 is removed by etching, for example, a selective oxidation method (LO
(COS method) to selectively deposit Si on the surface of the semiconductor substrate 1.
A field insulating film 4 such as an O ₂ film is formed to perform element isolation. At this time, in the p-well 2 portion, a p-type impurity such as B, which has been ion-implanted in the selective oxidation portion of the p-well 2 in advance, diffuses, and for example, the p-type impurity is formed below the field insulating film 4. ^{A +} type channel stop region (not shown) is formed.

Next, a gate insulating film 5 made of SiO ₂ is formed on the surface of the active region surrounded by the field insulating film 4 by, for example, a thermal oxidation method. Next, a polycrystalline Si film 6a having a thickness of, for example, about 70 nm is formed on the entire surface by, for example, a CVD method. Next, in order to reduce the resistance, polycrystalline Si
An n-type impurity such as P is implanted into the film 6a by ion implantation, for example, at an implantation energy of 20 keV and a dose of 5 ×.
Doping is performed at a high concentration under the condition of 10 ¹⁵ cm ^-2 . Next, a WSi ₂ film 6b having a thickness of, for example, about 100 nm is formed on the polycrystalline Si film 6a by, for example, a CVD method. Next, WS
An offset insulating film 7 such as a SiO ₂ film having a thickness of, for example, about 150 nm is formed on the i ₂ film 6b by, for example, a CVD method. Next, after a resist pattern (not shown) having a predetermined shape is formed on the offset insulating film 7 by a lithography method, the offset insulating film 7, the WSi ₂ film 6b, and the polycrystalline Si film 6a are formed using the resist pattern as a mask. Is etched and patterned by, for example, the RIE method. Thus, a gate electrode 6 having a polycide structure is formed on the gate insulating film 5, and the offset insulating film 7 is patterned into the same shape as the gate electrode 6.
Thereafter, the resist pattern used as the etching mask is removed.

Next, the n-channel MOSFE of the p well 2
A portion other than the active region corresponding to the T formation region is covered with a resist pattern (not shown), and the active region corresponding to the n-channel MOSFET formation region of the p well 2 is formed using the gate electrode 6, the offset insulating film 7 and the resist pattern as a mask. The region is doped with an n-type impurity such as P, for example, by ion implantation under the conditions of an implantation energy of 30 keV and a dose of 0.5 × 10 ^{13 to} 5 × 10 ¹³ cm ⁻² . Thereby, an n ⁻ -type region is formed in the active region corresponding to the n-channel MOS formation region of p well 2 in a self-aligned manner with respect to gate electrode 6. Next, the resist pattern used for the ion implantation of the n-type impurity is removed.

Next, the p-channel MOSFE of the n-well 3
A portion other than the active region corresponding to the T formation region is covered with a resist pattern (not shown), and an active region corresponding to the p-channel MOSFET formation region of the n-well 3 is formed using the gate electrode 6, the offset insulating film 7 and the resist pattern as a mask. A p-type impurity such as B is doped into the region by, for example, an ion implantation method under the conditions of an implantation energy of 20 keV and a dose of 0.5 × 10 ^{13 to} 5 × 10 ¹³ cm ⁻² . As a result, a p ⁻ -type region is formed in the active region corresponding to the p-channel MOS formation region of n-well 3 in a self-aligned manner with respect to gate electrode 6. Next, the resist pattern used for the ion implantation of the p-type impurity is removed.

Next, an SiO ₂ film having a thickness of, for example, about 150 nm is formed on the entire surface by, for example, a CVD method.
The iO ₂ film is etched back in a direction perpendicular to the surface of the semiconductor substrate 1 by, for example, RIE to form sidewall spacers 8 on the side surfaces of the gate electrode 6 and the offset insulating film 7.

Next, the n-channel MOSFE of the p well 2
A portion other than the active region corresponding to the T formation region and the active region corresponding to the well contact diffusion layer formation region of the n-well 3 is covered with a resist pattern (not shown), and the gate electrode 6, the offset insulating film 7, the sidewalls Using the spacer 8 and the resist pattern as a mask, the p well 2
In the active region corresponding to the n-channel MOSFET forming region and the active region corresponding to the well contact diffusion layer forming region of the n-well 3, for example, by ion implantation,
For example, an n-type impurity such as arsenic (As) is dosed at a dose of 1 ×
Doping is performed at a high concentration under the condition of 10 ¹⁵ to 10 × 10 ¹⁵ cm ⁻² . Next, the resist pattern used for the ion implantation of the n-type impurity is removed.

Next, the p-channel MOSFE of the n-well 3
A portion other than the active region corresponding to the T formation region and the active region corresponding to the well contact diffusion layer formation region of the p well 2 is covered with a resist pattern (not shown), and the gate electrode 6, the offset insulating film 7, the sidewalls are formed. The n-well 3 is formed using the spacer 8 and the resist pattern as a mask.
The active region corresponding to the p-channel MOSFET formation region and the active region corresponding to the well contact diffusion layer formation region of the p well 2 are formed by, for example, ion implantation.
For example, a p-type impurity such as B is dosed from 1 × 10 ¹⁵ to 1
Doping is performed at a high concentration under the condition of 0 × 10 ¹⁵ cm ⁻² .

Next, after removing the resist pattern used for the ion implantation of the n-type impurity, a heat treatment is performed as necessary to electrically activate the implanted impurity. As a result, in the p-well 2 n-channel MOSFET formation region,
An n ⁺ -type source region 9 and a drain region 10 are formed in self-alignment with the sidewall spacer 8, and are formed in the p-channel MOSFET formation region of the n-well 3 in self-alignment with the sidewall spacer 8. p
^{A +} type source region and a drain region are formed. Further, p ⁺ -type region is formed in the diffusion layer forming region for the well contact of the p-well 2, n ⁺ -type region is formed on the diffusion layer forming region for the well contact of the n-well 3.

Next, for example, as shown in FIG.
By a method D, for example, a diffusion prevention film 11 such as a SiN film having a thickness of 100 nm is formed on the entire surface. At this time, although not shown, the diffusion prevention film 11 is also formed on the back surface of the semiconductor substrate 1 (the main surface opposite to the main surface on which the elements are formed). Next, an interlayer insulating film 12 such as a 1500-nm-thick SiO ₂ film is formed on the diffusion preventing film 11 formed on the main surface of the semiconductor substrate 1 on the side where the elements are formed, for example, by a CVD method. . Next, chemical mechanical polishing (CMP)
Polishing is performed by the method until the thickness of the interlayer insulating film 12 on the active region becomes, for example, 1200 nm, and the surface of the interlayer insulating film 12 is planarized.

Next, as shown in FIG.
After a resist pattern (not shown) having a predetermined shape is formed thereon by a lithography method, a diffusion layer (a source region and a drain region of a MOSFET and a MOSFET) formed in an active region is formed by using the resist pattern as a mask, for example, by an RIE method. An interlayer insulating film 12, a diffusion preventing film 11, and a gate insulating film 5 in a predetermined portion on a well contact diffusion layer), and an interlayer insulating film 12, a diffusion preventing film 11, and an offset insulating film in a predetermined portion on a gate electrode 6. 7 are sequentially etched to form connection holes 1.
4 is formed.

Next, a SiN film having a thickness of, for example, 10 nm is formed on the entire surface by, for example, a CVD method, and the SiN film is etched back in a direction perpendicular to the main surface of the semiconductor substrate 1 by, for example, an RIE method. An insulating diffusion prevention film 15 made of SiN is formed on each of the side surface of the wiring groove 13 and the side surface of the connection hole 14.

Next, a Ti film having a thickness of, for example, 30 nm and a TiN film having a thickness of 70 nm are sequentially formed on the entire surface by, for example, a sputtering method so as to cover the side surfaces and the bottom of the wiring groove 13 and the connection hole 14. Thereby, a TiN / Ti film 16 as a barrier metal is formed. Here, as an example of sputtering conditions for forming the Ti film of the TiN / Ti film 16, Ar gas is used as a process gas, the flow rate is 120 sccm, the pressure is 0.67 Pa, the DC power is 4 kW, Film forming temperature 20
0 ° C. In addition, as an example of the sputtering conditions when forming the TiN film of the TiN / Ti film 16,
A mixed gas of Ar and nitrogen (N ₂ ) was used as the process gas, and the flow rates thereof were 60 sccm and 1 sc, respectively.
20 sccm, pressure 0.67 Pa, DC power 8
kW, and a film formation temperature of 200 ° C.

Next, as a seed layer used for forming a Cu film by electrolytic plating, for example, a Cu film (not shown) having a thickness of about 50 nm is entirely formed by sputtering.
To form Next, a Cu film is formed by electrolytic plating so as to fill the insides of the wiring grooves 13 and the connection holes 14. At this time, the thickness of the Cu film on the flat surface of the interlayer insulating film 12 is set to, for example, about 800 nm. As an example of the conditions for forming the Cu film by the electrolytic plating method, CuSO ₄ (5H ₂ O) is used as a plating solution, the solution temperature is 30 ° C., the voltage is 10 V, and the current density is 20 mA.
/ Dm ^2, and a Cu plate is used as the anode plate. When the Cu film is formed, the semiconductor substrate 1 is immersed in a plating solution containing Cu. In the step of forming the diffusion prevention film 11, the diffusion prevention film 1
The formation of Cu prevents diffusion of Cu from the back surface of semiconductor substrate 1 to the inside. The diffusion prevention film 11 formed on the back surface of the semiconductor substrate 1 is thereafter removed as necessary.

Next, a Cu film and a TiN / TiN film formed in portions other than the wiring grooves 13 and the connection holes 14 by the CMP method are formed.
The Ti film 16 is polished and removed to leave the Cu film and the TiN / Ti film 16 only inside the wiring groove 13 and the connection hole 14. As a result, as shown in FIG.
A Cu trench wiring 17 is formed inside the connection hole 3 and the connection hole 14 using the TiN / Ti film 16 as a base barrier metal.

As described above, the intended semiconductor device is manufactured.

According to this embodiment having the above-described structure, the diffusion preventing film 11 for preventing the diffusion of copper is provided between the surface of the semiconductor substrate 1 provided with the elements and the interlayer insulating film 12. Is provided, Cu contained in the Cu trench wiring 17 is transferred to the semiconductor substrate 1 through the interlayer insulating film 12.
It can be prevented from diffusing inside. As a result, problems such as gate insulating film destruction due to Cu diffusion, fluctuations in threshold voltage, and junction leakage of elements are effectively improved, thereby realizing a semiconductor device with high reliability and good characteristics. Can be. According to this embodiment,
In addition to the diffusion preventing film 11, a diffusion preventing film 15 for preventing the diffusion of Cu is provided on the side surfaces of the wiring grooves 13 and the connection holes 14, and the side surfaces and bottom portions of the wiring grooves 13 and the connection holes 14 are provided. TiN as barrier metal /
Since the Ti film 16 is provided, the semiconductor substrate 1 on which the elements are provided is isolated from the Cu trench wiring 17 and the diffusion path of Cu into the semiconductor substrate 1 is cut off. The effect of preventing the diffusion of Cu into the semiconductor substrate 1 is extremely high.

As described above, since the diffusion of Cu into the semiconductor substrate 1 provided with the elements is effectively prevented, the cap film for preventing the diffusion of Cu on the Cu trench wiring 17 is formed. Need not be provided, so that the manufacturing process can be simplified. Further, for example, in the case where a Cu wiring is further formed on the upper layer of the Cu groove wiring 17 to realize a multilayer wiring structure, it is necessary to provide an underlying barrier metal such as a TiN / Ti film on the Cu wiring above the Cu groove wiring 17. Since the Cu wiring can be directly connected to each other, there is also an advantage that the contact resistance can be reduced.

Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above embodiment, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values, materials, structures, processes, and the like described in the embodiments are merely examples,
It is not limited to this.

Further, in the above-described embodiment, the diffusion preventing film 1 provided on the side surfaces of the wiring grooves 13 and the connection holes 14 is provided.
5 can be omitted when good coverage of the TiN / Ti film 16 is obtained on the side surfaces of the wiring groove 13 and the connection hole 14.

In the above-described embodiment, Cu
Although the Cu film forming the trench wiring 17 is formed by an electrolytic plating method, the Cu film may be formed by an electroless plating method. In an example of conditions for forming the Cu film by the electroless plating method, copper sulfate (CuSO ₄ · 5H ₂ O)
7 g / l, formalin (37% HCHO) 20 ml
/ L, sodium hydroxide (NaOH) 10 g / l, sodium potassium tartrate 20 g / l, a stabilizer and a wetting agent each using a small amount of bath components, and the liquid temperature is 50 ° C. In addition, the Cu groove wiring 17 may be formed by a reflow method other than the plating method in some cases. Also,
A Cu alloy may be used as a wiring material.

In the above-described embodiment, the case where the present invention is applied to a CMOS IC has been described. For example, the present invention relates to a Bi-CMOS IC in which a bipolar transistor and a CMOS are mounted on the same substrate.
It is also possible to apply to.

[0047]

As described above, according to the present invention, the diffusion for preventing the diffusion of copper between one main surface of a semiconductor substrate having an element provided on one main surface and an interlayer insulating film. By providing the prevention film, it is possible to prevent copper contained in the copper or copper alloy wiring from diffusing into the element and the semiconductor substrate. Need not be provided with a cap film for preventing copper diffusion. Thus, a semiconductor device having high reliability and good characteristics can be realized, and the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 5 ... Gate insulating film, 6 ...
Gate electrode, 8 ... sidewall spacer, 11,
15: diffusion prevention film, 12: interlayer insulating film, 13
..Wiring grooves, 14 connection holes, 16 TiN / T
i film, 17 ... Cu groove wiring

Claims (14)

[Claims] A semiconductor substrate having an element provided on one main surface thereof; an interlayer insulating film provided on the one main surface of the semiconductor substrate so as to cover the element; A copper or copper alloy wiring buried inside a wiring groove and / or a connection hole, wherein diffusion of copper is prevented between the one main surface of the semiconductor substrate and the interlayer insulating film. Semiconductor device provided with a diffusion prevention film for the semiconductor device. 2. The semiconductor device according to claim 1, wherein said diffusion prevention film is a silicon nitride film. 3. The semiconductor device according to claim 1, wherein a diffusion preventing film for preventing diffusion of copper is provided on at least a side surface of the wiring groove and / or the connection hole. 4. The semiconductor device according to claim 1, wherein said copper or copper alloy wiring is embedded in said wiring groove and / or connection hole via a barrier metal. 5. A diffusion preventing film for preventing diffusion of copper is provided on at least a side surface of the wiring groove and / or the connection hole, and the barrier metal is provided on a side surface of the wiring groove and / or the connection hole. The semiconductor device according to claim 4, wherein the semiconductor device is provided on the diffusion preventing film provided. 6. The semiconductor device according to claim 1, wherein said copper or copper alloy wiring is formed by a plating method. 7. The element is a field effect transistor including a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, and a diffusion layer in the semiconductor substrate on both sides of the gate electrode. 2. The method according to claim 1, wherein
13. The semiconductor device according to claim 1. 8. A step of forming an anti-diffusion film for preventing copper diffusion on the one main surface of the semiconductor substrate having an element provided on one main surface; and forming an interlayer insulating film on the anti-diffusion film. Forming a wiring groove and / or a connection hole in the interlayer insulating film; and burying a copper or copper alloy wiring inside the wiring groove and / or the connection hole. Device manufacturing method. 9. The method according to claim 8, wherein the diffusion preventing film is a silicon nitride film. 10. The wiring groove and / or the wiring groove in the interlayer insulating film.
Alternatively, after the connection hole is formed, before the copper or copper alloy wiring is buried in the wiring groove and / or the connection hole, diffusion of copper into at least a side surface of the wiring groove and / or the connection hole is prevented. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming a diffusion prevention film. 11. The wiring groove and / or the wiring groove in the interlayer insulating film.
Alternatively, a step of forming a barrier metal on the side and bottom of the wiring groove and / or the connection hole before forming the copper or copper alloy wiring inside the wiring groove and / or the connection hole after forming the connection hole. 9. The method for manufacturing a semiconductor device according to claim 8, comprising: 12. The wiring groove and / or the wiring groove in the interlayer insulating film.
Alternatively, after forming the connection hole and before forming the barrier metal on the side surface and the bottom portion of the wiring groove and / or the connection hole, it is necessary to prevent diffusion of copper into at least the side surface of the wiring groove and / or the connection hole. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming a diffusion prevention film. 13. The method according to claim 8, wherein said copper or copper alloy wiring is formed by a plating method. 14. The field effect transistor according to claim 1, wherein the element comprises a gate insulating film on the semiconductor substrate, a gate electrode on the gate insulating film, and diffusion layers in the semiconductor substrate on both sides of the gate electrode. 9. The method of manufacturing a semiconductor device according to claim 8, wherein: