JP2001044201A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield and reliability of a semiconductor integrated circuit device by improving the planarity of an insulating film on metal interconnections formed by a CMP(Chemical mechanical polishing) method, and suppressing short circuits of the metal interconnections formed by the CMP method. SOLUTION: In a process step where a sacrificial film 16 is formed on an insulating film 11b and interconnections buried in grooves 15 formed of the films 11b and 16 are formed by deposition of a titanium nitride film 14b (barrier film) and a conductive film 18, such as a copper film and polishing using a CMP method, the film 16 which is polished at a speed higher than for the film 18 is polished at the same time. The film 16 is formed by implanting boron ions into the surface of the film 11b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device by depositing a conductive film containing copper as a main component in a groove formed in an insulating film and then performing a CMP process.
The present invention relates to a technique which is effective when applied to the manufacture of a semiconductor integrated circuit device having a wiring formed by removing a conductive film other than a groove region by a (Chemical Mechanical Polishing) method.

[0002]

2. Description of the Related Art Conventionally, wiring layers in a semiconductor integrated circuit are formed, for example, on November 30, 1984, by Ohm Co., Ltd., "LSI Handbook", p.
292, a high-melting-point metal thin film such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, and a photolithography process is used to form a thin film having the same shape as the wiring pattern on the wiring thin film. A resist pattern is formed, and a wiring pattern is formed by a dry etching process using the resist pattern as a mask.

However, in the method using an Al alloy or the like, there is a problem that the wiring resistance is remarkably increased as the wiring is miniaturized, the wiring delay is increased, and the performance of the semiconductor integrated circuit device is reduced. Was. Especially high performance logic L
In SI, a big problem has arisen as a performance hindrance factor.

[0004] Therefore, 1993 VMIC (VLSI Multi
level Interconnection Conference) Proceedings, p15-
As described in p21, after a wiring metal having copper (Cu) as a main conductor layer is buried in a groove formed in an insulating film, an extra metal outside the groove is removed by a CMP method (chemical mechanical polishing method). A method of forming a wiring pattern in a groove by removing the wiring pattern (so-called damascene method) has been studied.

[0005]

After a metal film for wiring having copper (Cu) or the like as a main conductor layer is buried in a groove formed in an insulating film, excess metal outside the groove is removed by a CMP method. The conventional technique has the following problems. This problem will be described with reference to FIG. FIGS. 32A and 32B are diagrams for explaining the problems examined by the present inventors. FIG. 32A is a plan view of a semiconductor substrate, FIG. 32B is a sectional view taken along line bb in FIG. 32A, and FIG. It is cc sectional drawing in. Note that FIG. 32 shows only a wiring layer that causes a problem,
Other members are omitted.

That is, in order to form the wiring 102 on the insulating film 101, first, an insulating film 103 for forming a wiring is deposited on the insulating film 101, and a wiring groove 104 is formed in the insulating film 103. Normally, a silicon oxide film is used for the insulating film 103. Next, a conductive film (for example, copper (Cu)) forming the wiring 102 is deposited on the insulating film 103 so as to fill the groove 104, and the insulating film 1 other than the groove 104 is formed.
The conductive film on the substrate 03 is removed by polishing by a CMP method.
As a result, the conductive film remains only in the groove 104, and the wiring 102 is formed.

However, since the polishing agent and the oxidizing agent for CMP are selected so that the polishing rate of copper is high, for example,
With respect to the silicon oxide film serving as the insulating film 103 and copper constituting the wiring 102, the polishing rate of CMP is higher in copper. Therefore, a concave portion 105 is generated in the surface portion of the wiring 102. The recess 105 is known as a kind of so-called dishing (dent). In addition, erosion of the wiring portion (loss of the insulating film due to over-processing) occurs by polishing by CMP.

When the insulating film 106 is formed thereon in a state where such a concave portion 105 or erosion exists, a concave portion 105 or a concave portion caused by erosion is also generated on the surface of the insulating film 106. When the plug 107 is formed in the insulating film 106 by the CMP method in a state where the recess exists, the plug 107 is formed in the recess on the surface of the insulating film 106.
Will remain.

That is, the plug 107 is formed by embedding a conductive film forming the plug 107 inside the connection hole opened in the insulating film 106 and depositing a conductive film on the insulating film 106. By removing the conductive film by the CMP method, the conductive film is formed to remain only in the connection hole. However, if a concave portion (including a concave portion caused by erosion) exists on the surface of the insulating film 106, the concave portion is formed in the concave portion. Also, the conductive material 108 which is a residue of the conductive film remains. Note that the conductive film may remain in the concave portion due to the erosion, but is omitted in the drawings.

[0010] Such a residue of the conductive substance 108 is not originally intended and is not preferable. That is, an insulating film 109 is formed on the plug 107, and the insulating film 109 is formed.
When the wirings 110 are formed in the groove portions, the wirings 110 that should be insulated are electrically short-circuited due to the presence of the conductive material 108, and a short-circuit failure between the wirings 110 occurs.

[0011] Such a short-circuit defect also occurs when a wiring is formed by a so-called dual damascene method without using the plug 107.

An object of the present invention is to provide a technique for improving the surface flatness of an insulating film on a metal wiring formed by a chemical mechanical polishing method.

Another object of the present invention is to suppress a short-circuit failure of an upper metal wiring on a metal wiring formed by a chemical mechanical polishing method, and to improve the yield and reliability of a semiconductor integrated circuit device. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) forming a semiconductor element on a main surface of a semiconductor substrate and forming an insulating film on the semiconductor element; (b) sacrificing a polishing rate higher than the insulating film on the insulating film; Forming a film, (c) etching the sacrificial film and the insulating film to form a groove,
(D) forming a barrier film on the surface of the sacrificial film including the inside of the groove, and (e) forming a conductive film filling the groove on the surface of the barrier film including the inside of the groove. (F) chemically and mechanically polishing the conductive film, the barrier film, and the sacrificial film outside the groove to leave the barrier film and the conductive film in the groove, thereby forming a wiring. Forming a.

(2) Another method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) forming a semiconductor element on a main surface of a semiconductor substrate and forming an insulating film on the semiconductor element; (b) forming a groove by etching the insulating film; Forming a sacrificial film having a higher polishing rate than the insulating film on the insulating film including the inside of the groove;
(D) forming a barrier film on the surface of the sacrificial film including the inside of the groove, and (e) forming a conductive film filling the groove on the surface of the barrier film including the inside of the groove. (F) chemically and mechanically polishing the conductive film, the barrier film, and the sacrificial film outside the groove to leave the sacrificial film, the barrier film, and the conductive film in the groove; Thereby forming a wiring.

According to the manufacturing methods (1) and (2),
At the time of polishing the conductive film, the sacrificial film having a higher polishing rate than the insulating film deposited on the insulating film around the groove is simultaneously polished, so that the polishing can be performed without causing dishing (dent) or erosion (loss) on the wiring. Then, the polishing selectivity between the wiring and the insulating film can be controlled.

Even when an insulating film is further formed on the upper portion, the surface of the conductive film is buried in the upper insulating film because the dent of the wiring portion on the lower insulating film is reduced. The formation by the method is reliably performed. That is, the polishing residue of the conductive film embedded in the upper insulating film is not formed in the concave portion on the surface of the upper insulating film that would occur when the sacrificial film is not formed, and the upper insulating film caused by the residue is not removed. Short-circuit failure between wirings can be prevented. As a result, the flatness of the step is improved, and the yield and reliability of the semiconductor integrated circuit device can be improved.

When a concave portion is present on the surface of the upper insulating film, it is necessary to excessively polish the conductive film deposited on the upper insulating film in order to form a wiring. Since no depressed portion is formed on the surface of the upper insulating film, excessive polishing is not required. As a result, dishing of the wiring buried in the upper insulating film can be prevented, and furthermore, the wiring formed on the upper part can be surely formed for the same reason as described above, and the short circuit failure can be prevented.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing an example of a semiconductor integrated circuit device manufactured according to the present invention.

The semiconductor integrated circuit device according to the first embodiment is
For example, an n-channel MISFET (Metal Insulator Semi) is formed in a p-well 4 of a semiconductor substrate 1 having an SOI (Silicon On Insulator) insulating layer 2 and a U-groove element isolation region 3.
conductor Field Effect Transistor) Qn is formed. SOI insulating layer 2, U-groove element isolation region 3
Is composed of, for example, a silicon oxide film.

The n-channel MISFET Qn has a gate electrode 7 formed on the main surface of the semiconductor substrate 1 with a gate insulating film 6 interposed therebetween, and an impurity semiconductor region formed on the main surface of the semiconductor substrate 1 on both sides of the gate electrode 7. 8, a sidewall spacer 9 and a cap insulating film 10 are formed on the side surface and the upper surface of the gate electrode 7, respectively.

Gate insulating film 6 is formed of a silicon oxide film having a thickness of several nm, and can be formed by, for example, a thermal CVD method or a thermal oxidation method.

The gate electrode 7 may be made of, for example, a low-resistance polycrystalline silicon film, and a low-resistance metal layer such as a silicide layer or tungsten may be formed thereon.

The impurity semiconductor region 8 has an n-channel MIS
It functions as a source / drain region of the FET Qn. For example, impurities such as phosphorus (P) or arsenic (As) are implanted at a high concentration.

[0030] On top of the gate electrode 7 and the impurity semiconductor regions _{8, WSi x, MoSi x,} TiSi x, TaS
a refractory metal silicide film such as i _x a silicide film may be formed by laminating.

The sidewall spacer 9 and the cap insulating film 10 can be, for example, a silicon oxide film or a silicon nitride film. When a silicon nitride film is used, the sidewall spacer 9 and the cap insulating film made of the silicon nitride film are used. Using the film 10 as a mask, a connection hole can be opened in a self-aligned manner in an insulating film described later.

An insulating film 11a is formed above the n-channel MISFET Qn. B as the insulating film 11a
A reflow film such as a PSG (Boron-doped Phospho Silicate Glass) film or a PSG (Phospho Silicate Glass) film can be used, and a silicon oxide film formed by a CVD method or a sputtering method below or above the insulating film 11a. Can be formed as a laminated film. Insulating film 11
After a is deposited, it is polished by, for example, a CMP method, and its surface is planarized.

In the insulating film 11a on the impurity semiconductor region 8, a connection hole 12 is provided. In the connection hole 12, a titanium nitride film 13a formed by, for example, a sputtering method and a blanket CVD method or a selective CVD method are formed. A metal plug 13b made of the removed tungsten is formed.

An insulating film 11b is formed on the insulating film 11a, and a wiring 14 is formed in the groove 1 in the insulating film 11b.
5 are formed.

The insulating film 11b is formed of, for example, a silicon oxide film formed by a CVD method or a sputtering method.

The wiring 14 is composed of a main conductive layer 14a and a titanium nitride film 14b. Main conductive layer 14a is made of, for example, copper. By using a material having a low resistivity as the main conductive layer, such as copper, an increase in wiring resistance due to miniaturization of the wiring 14 can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. The titanium nitride film 14b can serve as a barrier film for preventing copper, which is a material forming the main conductive layer 14a, from diffusing into the insulating film 11a and the insulating film 11b. Adhesion is also improved. The titanium nitride film 14b may be a titanium nitride film, for example, a tantalum film, a tantalum nitride film, a tungsten nitride film, a sputtered tungsten film,
Alternatively, it may be a compound of these and silicon.

An insulating film 19 is formed on the wiring 14 and the insulating film 11b. The insulating film 19 includes a blocking layer 1 formed in contact with the wiring 14 and the insulating film 11b.
9a and an insulating film 19b.

The blocking layer 19a can be, for example, a silicon nitride film formed by a plasma CVD method, and has a function of suppressing diffusion of copper constituting the main conductive layer 14a of the wiring 14. Thereby, the titanium nitride film 14
It is possible to prevent copper from diffusing into the insulating films 11a, 11b, and 19 together with b, maintain their insulating properties, and improve the reliability of the semiconductor integrated circuit device.

The insulating film 19b can be, for example, a silicon oxide film formed by a CVD method.
It is for ensuring the depth of the.

The groove 20 is formed in the insulating film 19, and a wiring 22 as a second metal wiring is formed in the groove 20. Note that a part of the groove 20 also includes a connection hole for connecting to the wiring 14 formed thereunder. That is, a groove and a connection hole are formed, and a conductive film is deposited on the insulating film including the groove and the inside of the connection hole.
It is formed by a so-called dual damascene method in which the conductive film in the region other than the groove is removed by the P method to form the connection wiring and the wiring integrally.

The wiring 22 is, like the wiring 14, the main conductive layer 2.
2a and a titanium nitride film 22b. Main conductive layer 22a
Is, for example, copper. By using a material having a low resistivity as a main conductive layer, an increase in wiring resistance due to miniaturization of the wiring 22 can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. Titanium nitride film 2
2b prevents diffusion of the material constituting the main conductive layer 22a, for example, copper, into the insulating film 19, and furthermore, when an insulating film is formed on the wiring 22, Can function as a barrier film for preventing diffusion of copper, and the adhesion to copper deposited in the groove 20 is also improved. In addition to the titanium nitride film, for example, a tantalum film, a tantalum nitride film, a tungsten nitride film, a sputtered tungsten film, or a compound thereof with silicon can be used.

The wiring 22 is connected to a CM as described later.
The conductive film formed on the insulating film 19 is removed by polishing using the P method, and the surface of the insulating film 19 is flattened by polishing using a CMP method using a sacrificial film described later. Since it is secured, there is no concave portion other than the groove portion 20 on the surface thereof, and therefore, no residue of the conductive film other than the wiring 22 is formed. Therefore, short-circuit failure of the wiring 22 due to the conductive residue does not occur, and the yield and reliability of the semiconductor integrated circuit device can be improved. Since the surface of the insulating film 19 is sufficiently flat, the wiring 2
Excessive overpolishing is not required in the polishing by CMP to form No. 2. As a result, it is possible to suppress the dishing of the wiring 22 and prevent a short-circuit failure of the upper wiring when a multilayer wiring (third metal wiring or the like) is formed, thereby improving the yield and reliability of the semiconductor integrated circuit device. it can.

An insulating film and a wiring similar to the insulating film 19 and the wiring 22 may be formed on the wiring 22 to form a multilayer structure. In this case, as in the case of the wiring 22, it is possible to reliably process the upper layer wiring by polishing using a CMP method using a sacrificial film similar to a sacrificial film described later.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

[0045] First, p has a SOI insulating layer 2 formed by hyperoxia implantation or the like ^- providing a semiconductor substrate 1 made of the form of single crystal silicon, an impurity for the conductivity type of p-type, such as boron Is doped by ion implantation or the like to form a p-well 4. The p-well 4 may be doped with an impurity gas during the epitaxial growth by the high-concentration oxygen implantation method.

Next, a U-groove reaching the SOI insulating layer 2 is formed on the main surface of the semiconductor substrate 1, and then, for example, a silicon oxide film is deposited. Then, an extra silicon oxide film is removed by using a CMP method or the like. Then, a silicon oxide film is buried in the U-groove to form a U-groove element isolation region 3 (FIG. 2).

Next, a silicon oxide film serving as a gate insulating film 6, a polycrystalline silicon film serving as a gate electrode 7, and a silicon oxide film serving as a cap insulating film 10 are sequentially deposited on the main surface of the semiconductor substrate 1 to form a laminated film. Is formed, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate electrode 7 and a cap insulating film 10 (FIG. 3). The gate insulating film 6 can be formed by, for example, a thermal CVD method, and the polycrystalline silicon forming the gate electrode 7 can be formed by a CVD method. In order to reduce the resistance value, an n-type impurity (for example, Doping with phosphorus (P). In addition, the upper part WSi _x of polycrystalline silicon 7, MoSi _x, TiS
i _x, it may be stacked refractory metal silicide film such as TaSi _x. The cap insulating film 10 can be deposited by, for example, a CVD method.

Next, after depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, reactive ion etching (RI
The silicon oxide film is anisotropically etched by the method E) to form sidewall spacers 9 on the side walls of the gate electrode 7 and ion-implant n-type impurities (phosphorus) to form p-wells on both sides of the gate electrode 7. 4 n channel MISFE
The impurity semiconductor regions 8 forming the source and drain regions of TQn are formed (FIG. 4). Note that a low-concentration impurity semiconductor region is formed before the formation of the sidewall spacers 9.
After the formation of the sidewall spacers 9, a high-concentration impurity semiconductor region may be formed.

Next, after depositing a silicon oxide film on the semiconductor substrate 1 by a sputtering method or a CVD method, for example, the silicon oxide film is polished by a CMP method to form an insulating film 11a whose surface is flattened. I do. Further, insulating film 11a on impurity semiconductor region 8 on the main surface of semiconductor substrate 1
The connection hole 12 is formed by using a known photolithography technique.
Is opened (FIG. 5).

Next, the titanium nitride film 13 is formed by sputtering.
Then, a tungsten film 13c is deposited by blanket CVD (FIG. 6).

Next, the tungsten film 13c and the titanium nitride film 13a on the insulating film 11a other than the connection holes 12 are removed by, for example, an etch-back method to form a metal plug 13b (FIG. 7).

Next, a silicon oxide film is deposited by a CVD method to form an insulating film 11b (FIG. 8).

Next, boron (B) is ion-implanted into the surface of the deposited insulating film 11b to form a sacrificial film 16 (FIG. 9). In this case, the sacrificial film 16 is an insulating film. In the first embodiment, boron is exemplified, but ion implantation of phosphorus (P) or both boron and phosphorus may be performed.
Further, an oxide film containing B and / or P is newly deposited on the insulating film 11 by the CVD method, and the sacrificial film 16 is formed.
It may be. The formation of the sacrificial film 16 by ion implantation has a feature that the insulating film 11b can be used for forming the sacrificial film 16, and the formation of the sacrificial film 16 by attaching a new film to the surface of the insulating film 11b has Sacrificial film 1 formed
6 has a feature that is easy to cut. The formation of the sacrificial film 16 is performed to prevent dishing during the CMP of the copper film described later. The thickness of the sacrificial film 16 is 500 to 100.
0 °, and this film thickness corresponds to the CMP of a copper film described later.
Is performed without forming the sacrificial film 16. The polishing rate of the insulating film 11 is 10 °.
/ Min or less, and the polishing rate of the sacrificial film 16 is 50 to 100 times the polishing rate of the conductive film 18 described later.

Next, the sacrifice film 16 and the insulating film 11b are processed by using a known photolithography technique and an etching technique to form the groove 15 (FIG. 10). Groove 15
Has a depth of 0.5 μm after CMP of a copper film to be described later.
m.

Next, a titanium nitride film 14b serving as a barrier film for the wiring 14 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 1).
1). The titanium nitride film 14b can be deposited by, for example, a CVD method or a sputtering method. The titanium nitride film 14b is deposited to improve the adhesion of the copper film and prevent the diffusion of copper, which will be described later.
00 °. In the first embodiment, a titanium nitride film is exemplified. However, a metal film such as tantalum or a tantalum nitride film may be used. In the case where the barrier film is tantalum or tantalum nitride, the titanium nitride film is more suitable than when titanium nitride is used. Good adhesion to copper film. It is also possible to sputter-etch the surface of the titanium nitride film 14b immediately before the next step of depositing the main conductive layer 14a. With such a sputter etch,
By removing water, oxygen molecules, and the like adsorbed on the surface of the titanium nitride film 14b, the adhesion of the main conductive layer 14a can be improved. In particular, after deposition of the titanium nitride film 14b, the effect is great when vacuum breaking is performed to expose the surface to the atmosphere and deposit the main conductive layer 14a.

Next, a thin film of copper, which is a metal to be the main conductive layer 14a, is deposited, heat-treated and fluidized to form a groove 15a.
The conductive film 18 satisfactorily embedded without gaps is uniformly formed (FIG. 12). For the deposition of the copper film, a normal sputtering method can be used, but a physical vapor deposition method such as an evaporation method,
A plating method may be used. When using the plating method,
Before depositing a copper thin film, it is necessary to deposit a seed film, which is deposited by a sputtering method. The heat treatment conditions are as follows:
It requires a temperature and a time at which the copper constituting the conductive film 18 is fluidized, for example, 400 ° C. to 450 ° C., 3 minutes to 5 minutes.
Minutes can be illustrated.

Next, the excess titanium nitride film 14b and the conductive film 18 on the insulating film 11b are removed, and the main conductive layer 14a and the titanium nitride film
4b is formed (FIG. 13). The removal of the titanium nitride film 14b and the conductive film 18 is performed by polishing using a CMP method. In the CMP, alumina abrasive grains and silica abrasive grains are used as a polishing agent, and hydrogen peroxide water is used as an oxidizing agent.
For example, a torque detection method is used to detect the end point of the CMP. In addition, a small hole is made in the CMP polishing pad in advance, and the polishing surface is irradiated with a laser beam from the small hole.
At the end point of the MP, the reflectance of the laser light changes,
An optical detection method for detecting a change in the intensity of the reflected laser light may be used for detecting the end point of the CMP. During CMP, the conductive film 1 deposited on the insulating film 11b around the trench 15
Since the sacrificial film 16 having a polishing rate higher than 8 is simultaneously polished, the conductive film 18 is polished without causing dishing (dent) or erosion (loss) on the wiring, and the wiring 14 and the insulating film 11b are polished. Can be controlled.

Next, a silicon nitride film is deposited on the wiring 14 and the insulating film 11b to form a blocking layer 19a (FIG. 14). For example, a plasma CVD method can be used for depositing the silicon nitride film.
It is set to 0 nm.

Next, an insulating film 19b is deposited to form an insulating film 19b.
Is completed (FIG. 15). The insulating film 19b is, for example, a CV
It can be a silicon oxide film by the D method. The surface of the insulating film 19b, that is, the surface of the insulating film 19 is formed on the main conductive layer 1 by CMP of the conductive film 18 using the sacrificial film 16.
Since the dishing amount on the surface 4a is reduced, flatness is ensured.

Next, a sacrificial film 21 is formed on the insulating film 19b in the same manner as the sacrificial film 16 (FIG. 16). The thickness of the sacrificial film 21 is the same as the thickness of the sacrificial film 16.

Next, a groove 20 is formed (FIG. 17). The groove 20 also includes a connection hole for connecting to the wiring 14 as a lower wiring.

Next, as in the case of the wiring 14, the wiring 22
Is deposited, and a thin film of a metal, for example, copper, serving as the main conductive layer 22a is deposited. The thin film is heat-treated and fluidized, and the conductive film is buried in the groove 20 without gaps. A film 23 is formed (FIG. 18). The titanium nitride film 22b and the conductive film 23 are the same as the titanium nitride film 14b and the conductive film 18 described above, and thus description thereof is omitted.

Finally, the conductive film 23, the titanium nitride film 22b, and the sacrificial film 21 on the insulating film 19 are removed and the wiring 22
Is formed, and the semiconductor integrated circuit device shown in FIG. 1 is almost completed. The CMP method using the sacrificial film described above is used for removing the conductive film 23 and the titanium nitride film 22b.
In the present embodiment, since the flatness of the surface of the insulating film 19 is ensured, even if CMP is performed for forming the wiring 22, there is no unintentional concave portion on the surface of the insulating film 19. Conductive film 23 or titanium nitride film 2
No residue of 2b is produced. For this reason, occurrence of a short circuit failure of the wiring 22 due to such a residue can be prevented, and the yield and reliability of the semiconductor integrated circuit device can be improved.

Since the flatness of the surface of the insulating film 19 is ensured, the wiring 18 can be surely formed without excessive CMP overpolishing, and excessive polishing can be prevented. . For this reason, dishing on the surface of the wiring 22 can be suppressed to prevent short-circuit failure of the wiring formed thereon, and the yield and reliability of the semiconductor integrated circuit device can be improved.

(Second Embodiment) A method of manufacturing a semiconductor integrated circuit device according to a second embodiment is the same as that of the first embodiment.
1 is replaced with a sacrifice film 25. In this case, the sacrifice films 24 and 25 are titanium nitride conductor films deposited by a sputtering method. Other members are the same as in the first embodiment. Therefore, description of those similar members will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

After that, a titanium nitride film is deposited on the insulating film 11b by sputtering to form a sacrificial film 24 (FIG. 19). The sacrificial film 24 exemplified in the second embodiment is titanium nitride, but may be tungsten, tungsten nitride, or polycrystalline silicon. When the sacrificial film 24 is made of tungsten or tungsten nitride, it is deposited by a sputtering method, and when it is made of polycrystalline silicon, it is deposited by a CVD method. The thickness of the sacrificial film 24 is about 300 °.

Next, the insulating film 11b is processed in the same step as that of FIG. 10 in the first embodiment to form the groove 15 (FIG. 20).

Next, a tantalum film 14c is deposited as a barrier film in the same step as in FIG. 11 in the first embodiment (FIG. 21). Although the tantalum film 14c is exemplified as the barrier film in the second embodiment, tantalum nitride may be used.
When the barrier film is tantalum or tantalum nitride, the adhesion to the copper film is better than when titanium nitride is used. The thickness of the tantalum film 14c is about 200 °. When CMP is performed by combining the sacrificial film 24 and the tantalum film 14c, the sacrificial film 24 having a higher polishing rate than the copper film is polished after polishing the tantalum film 14c having a lower polishing rate than the copper film.
The dishing amount is reduced as compared with the case where CMP is performed without forming the sacrificial film 24.

Next, a copper thin film is deposited in the same process as that of FIG. 12 in the first embodiment, and is heat-treated to be fluidized.
8 (FIG. 22).

The subsequent steps are the same as in FIGS. 13 to 18 in the first embodiment. Further, the formation of the sacrificial film 25 is the same as the process of FIG. 19 of the second embodiment, and the deposition of the tantalum film 22c is described in FIG.
This is the same as the first step (FIG. 23).

(Third Embodiment) In the semiconductor integrated circuit device according to the third embodiment, the order of the step of forming the sacrificial film 16 and the step of forming the groove 15 of the semiconductor integrated circuit device of the first embodiment is reversed. Thus, the order of the step of forming the sacrificial film 21 and the step of forming the groove 20 are reversed. The members are the same as in the first embodiment, and a description of those similar members will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device of the third embodiment is the same as that of the first embodiment up to the steps shown in FIGS.

Thereafter, the insulating film 11b is processed in the same step as that of FIG. 10 in the first embodiment to form the groove 15 (FIG. 24).

Next, a sacrificial film 16 is formed by the same process as that of FIG. 9 in the first embodiment (FIG. 25). In the third embodiment, boron (B) is exemplified, but ion implantation of phosphorus (P) or both boron and phosphorus may be performed. Since the sacrifice film 16 is formed by ion implantation of boron perpendicular to the main surface of the semiconductor substrate, the insulating film 1
The sacrificial film is not formed on the upper surface of the groove 1b and on the bottom of the groove 15 (excluding the plug), but on the side surface of the groove 15.

Next, a titanium nitride film 14b serving as a barrier film of the wiring 14 is deposited on the entire surface of the semiconductor substrate 1 in the same step as that of FIG. 11 in the first embodiment (FIG. 2).
6). In the third embodiment, a titanium nitride film is exemplified. However, a metal film such as tantalum or a tantalum nitride film may be used. In the case where the barrier film is tantalum or tantalum nitride, a titanium nitride film is used. Good adhesion to copper film.

Next, in a step similar to that of FIG. 11 in the first embodiment, a thin film of copper, which is a metal to be main conductive layer 14a, is deposited, and conductive film satisfactorily buried in groove 15 without gaps. The film 18 is formed (FIG. 27).

The subsequent steps are the same as in FIGS. 13 to 18 in the first embodiment. Further, the formation of the groove 20 is the same as the step of FIG. 24 of the third embodiment, and the deposition of the sacrificial film 21 is the same as the step of FIG. 25 of the third embodiment (FIG. 28).

(Embodiment 4) In the semiconductor integrated circuit device of Embodiment 4, the sacrificial film 16 of the semiconductor integrated circuit device of Embodiment 3 is replaced by the sacrificial film 24, and the sacrificial film 21 is replaced by the sacrificial film 25. In this case, the sacrificial films 24 and 25 are titanium nitride conductor films deposited by a sputtering method. Other members are the same as in the first embodiment. Therefore, description of those similar members will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device of the fourth embodiment is the same as that of the first embodiment up to the step of FIG.

Thereafter, the insulating film 11b is processed in the same step as that of FIG. 10 in the first embodiment to form the groove 15. Since the groove 15 becomes smaller than the designed value due to the deposition of the sacrificial film 24 formed later, it is necessary to form the groove 15 larger than the designed value. Next, a sacrificial film 24 is formed in the same step as that of FIG. 19 in the second embodiment (FIG. 29).

Next, a tantalum film 14c is deposited as a barrier film in the same step as in FIG. 11 in the first embodiment (FIG. 30). Although the tantalum film 14c is exemplified as the barrier film in the fourth embodiment, tantalum nitride may be used.
When the barrier film is tantalum or tantalum nitride, the adhesion to the copper film is better than when titanium nitride is used.

The subsequent steps are the same as in FIGS. 12 to 18 in the first embodiment. The formation of the groove 20 and the deposition of the sacrificial film 25 are the same as those in the step of FIG. 29 of the fourth embodiment (FIG. 31).

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the second embodiment, the case where the barrier film is made of tantalum is illustrated, but titanium nitride may be used.

[0089]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.

(1) The dishing amount of the copper wiring formed by burying it in the groove formed in the insulating film by the chemical mechanical polishing method is reduced, and the surface flatness on the copper wiring can be improved.

(2) A short circuit failure of the second conductive member on the conductive member embedded in the groove or the connection hole formed in the insulating film by the chemical mechanical polishing method can be prevented, and the semiconductor integrated circuit device can be prevented. Yield and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1 in the order of steps.

FIG. 3 is a cross-sectional view showing an example of a method for manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps.

FIG. 4 is a cross-sectional view showing one example of a method for manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 5 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 6 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 7 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 8 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 9 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 10 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 11 is a sectional view illustrating an example of a method of manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps.

FIG. 12 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 13 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 14 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 15 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 17 is a cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device of the first embodiment in the order of steps;

FIG. 18 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 19 is a sectional view illustrating an example of a method of manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention in the order of steps.

FIG. 20 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the second embodiment in the order of steps;

FIG. 21 is a cross-sectional view showing one example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 2 in the order of steps;

FIG. 22 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 2 in the order of steps;

FIG. 23 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 2 in the order of steps;

FIG. 24 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to Embodiment 3 of the present invention in the order of steps.

FIG. 25 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the third embodiment in the order of steps;

FIG. 26 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 3 in the order of steps;

FIG. 27 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 3 in the order of steps;

FIG. 28 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of Embodiment 3 in the order of steps;

FIG. 29 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 4 of the present invention in the order of steps.

FIG. 30 is a cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 4 in the order of steps.

FIG. 31 is a cross-sectional view showing one example of the method of manufacturing the semiconductor integrated circuit device of the fourth embodiment in the order of steps;

FIGS. 32A and 32B are diagrams for explaining a problem studied by the present inventors, wherein FIG. 32A is a plan view, and FIG.
b is a cross-sectional view, and (c) is a cc cross-sectional view in (a).

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 SOI insulating layer 3 U-groove element isolation region 4 p-well 6 gate insulating film 7 gate electrode 8 impurity semiconductor region 9 sidewall spacer 10 cap insulating film 11 insulating film 11a insulating film 11b insulating film 12 connection groove 13 metal plug 13a Titanium nitride film 13b Metal plug 13c Tungsten film 14 Wiring 14a Main conductive layer 14b Titanium nitride film 14c Tantalum film 15 Groove 16 Sacrificial film 18 Conductive film 19 Insulating film 19a Blocking film 19b Insulating film 20 Groove 21 Sacrificial film 22 Wiring 22a Main Conductive layer 22b Titanium nitride film 22c Tantalum film 23 Conductive film 24 Sacrificial film 25 Sacrificial film 101 Insulating film 102 Wiring 103 Insulating film 104 Groove 105 Depression 106 Insulating film 107 Plug 108 Conductive material 109 Insulating film 110 Wiring

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/88 R 21/90 M (72) Inventor Shinichi Fukada 6-16, Shinmachi, Ome-shi, Tokyo 3 F-term (Reference) in Hitachi, Ltd. Device Development Center HH33 HH34 JJ01 JJ11 JJ19 JJ21 JJ31 JJ32 JJ33 JJ34 KK01 KK11 KK19 KK21 KK31 KK32 KK33 KK34 LL04 MM01 MM02 MM05 MM07 MM12 MM13 NN06 NN40 PP06 PP07 PP15 PP26 QQ08 QQ09 QQ10 QQ13 QQ16 QQ31 QQ37 QQ48 QQ49 QQ58 QQ60 QQ65 QQ73 RR04 RR06 RR13 RR14 RR15 SS08 SS11 SS15 TT02 TT08 UU05 VV06 XX00 XX01 XX31 XX34

Claims (7)

[Claims] (A) forming a semiconductor element on a main surface of a semiconductor substrate and forming an insulating film on the semiconductor element; (b) forming a semiconductor element on the insulating film at a polishing rate lower than that of the insulating film; Forming a large sacrificial film, (c) etching the sacrificial film and the insulating film to form a groove,
(D) forming a barrier film on the surface of the sacrificial film including the inside of the groove, and (e) forming a conductive film filling the groove on the surface of the barrier film including the inside of the groove. (F) chemically and mechanically polishing the conductive film, the barrier film, and the sacrificial film outside the groove to leave the barrier film and the conductive film in the groove, thereby forming a wiring. Forming a semiconductor integrated circuit device. (A) forming a semiconductor element on a main surface of a semiconductor substrate and forming an insulating film on the semiconductor element; (b) forming a groove by etching the insulating film; (C) forming a sacrificial film having a higher polishing rate than the insulating film on the insulating film including the inside of the groove;
(D) forming a barrier film on the surface of the sacrificial film including the inside of the groove, and (e) forming a conductive film filling the groove on the surface of the barrier film including the inside of the groove. (F) chemically and mechanically polishing the conductive film, the barrier film, and the sacrificial film outside the groove to leave the sacrificial film, the barrier film, and the conductive film in the groove; Forming a wiring, thereby producing a semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said insulating film is a silicon oxide film, and said sacrificial film is formed by ion-implanting boron or phosphorus or both. A method for manufacturing a semiconductor integrated circuit device, wherein the method is an implanted silicon oxide film-based insulating film. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said insulating film is a silicon oxide film, and said sacrificial film is a gas containing boron or phosphorus, or both. A method for manufacturing a semiconductor integrated circuit device, comprising a silicon oxide-based insulating film formed by a used CVD method. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the sacrificial film is a metal film or a metal nitride film having a higher polishing rate than the barrier film. A method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said metal nitride film is a titanium nitride film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said conductive film contains copper as a main component. Production method.