JP2001284557A - Producing method for non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of a memory array. SOLUTION: A producing method for a non-volatile semiconductor memory device is provided with plural memory cells composed of diffusion bit lines formed at least one part of the bottom surface and the side face of a trench formed on a wafer, provided with a selection gate transistor for selecting one of diffusion bit lines, a peripheral circuit transistor and an element separating area, and formed with the element separating area inside a trench. This method is provided with a process for simultaneously forming the trench to form the diffusion bit lines and the trench for forming the element separating area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device. More specifically, the present invention provides:
The present invention relates to an improvement in a method of manufacturing a nonvolatile semiconductor memory device in which a diffusion bit line is formed on at least a part of a bottom surface and a side surface of a trench formed by etching a semiconductor substrate, and the trench is formed simultaneously with a trench for forming an element isolation region. .

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device having a select gate transistor for selecting a bit line of a memory array in which a plurality of memory cells are arranged,
It is desired to reduce the manufacturing cost by reducing the device size. Therefore, it is important to optimize the layout of the select gate transistor to reduce its area and to simplify the manufacturing process.

[0003] In order to solve these problems, Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open No. 64-7033 and Japanese Patent Application Laid-Open No. H11-26731 describe the following technology. That is, like the memory cell, the select gate transistor and the peripheral circuit transistor have a stacked gate having a structure in which a floating gate made of polysilicon and a control gate are stacked. Further, in the select gate transistor and the peripheral circuit transistor, the floating gate and the control gate are connected.

FIG. 24 is a plan view of a conventional memory array (nonvolatile semiconductor memory device). In addition, FIG.
25 (B), 25 (C), 25 (D) and 25 are sectional views taken along lines B, CC, DD and EE.
(E) shows each. Further, the line FF of FIG.
FIGS. 26F and 26C are cross-sectional views taken along lines G and HH.
(G) and FIG. 26 (H).

In FIGS. 24, 25 and 26, a plurality of memory cells are arranged in a matrix to form a memory array.

The select gates 9 are separated from each other by an element isolation region 7 in which an oxide film is buried in a trench. The select gate 9 has a laminated structure of a polysilicon film 22 as a floating gate and a polycide film 25 as a control gate, like the memory cell.

A bit line is selected by select gates 9 provided on both sides of a block comprising each memory array. The bit line is aligned with the element isolation region 7 of the selection gate 9 (or peripheral circuit). Further, the bit line is connected to the N ⁺ region 20 of the memory cell via the source / drain region 27 of the select gate transistor. Furthermore, it is connected via a contact 8 to a main bit line (not shown) made of metal wiring. In the figure, 5 is a memory cell gate, 10 is a semiconductor substrate, 13 is a tunnel oxide film, 14 is a gate oxide film, 19 is an N ⁻ region, 21 is a silicon oxide film, 23 is an ONO film, and 32 is an interlayer insulating film. means.

A conventional manufacturing process of a nonvolatile semiconductor memory device having a memory cell portion and a peripheral circuit transistor will be described with reference to manufacturing process sectional views of FIGS.

In FIGS. 27 to 45, the cross section in the channel length direction of the memory cell portion is shown in FIG. 27A, and the cross section in the channel width direction of the memory cell portion is shown in FIG. (C) of each figure and (D) of each figure show a cross section of the peripheral circuit transistor in the channel width direction.

First, an oxide film 11 serving as a gate oxide film of a peripheral circuit transistor is formed on a P-type semiconductor substrate 10 on which element isolation regions for peripheral circuit transistors have been formed (see FIG. 27).

Subsequently, the formation region of the peripheral circuit transistor other than the memory array portion where the tunnel oxide film is formed is covered with the resist pattern 12 by a photo process. Thereafter, wet etching is performed on the oxide film 11 by HF until the semiconductor substrate 10 is completely exposed (see FIG. 28). In the figure, 31 indicates an element isolation region.

Further, after the resist pattern 12 is removed, thermal oxidation for forming a tunnel oxide film of 9 to 11 nm is performed with the oxide film 11 left in the region where the peripheral circuit transistor is formed. Due to this oxidation, a gate oxide film 14 having a thickness of 14 to 16 nm is formed in the region where the peripheral circuit transistor is formed, and a tunnel oxide film 13 having a thickness of 9 to 11 nm is formed in the memory cell portion (see FIG. 29).

Subsequently, a 50 nm polysilicon film 15,
An HTO film 16 of 100 nm and a silicon nitride film 17 of 250 nm are sequentially formed by a CVD method (see FIG. 30).

Next, a resist pattern 18 in which a region to be a bit line of the memory cell is opened is aligned with the element isolation region 31 of the peripheral circuit transistor and formed by a photo process. Thereafter, the silicon nitride film 17, the HTO film 16, the polysilicon film 15, and the tunnel oxide film 13 are sequentially etched by dry etching,
Further, the semiconductor substrate 10 is etched by about 20 nm (see FIG. 31).

Next, N, which is an asymmetric structure of the memory cell,
^-A region 19 is formed on one side wall of the trench
In addition, As is 15 KeV, 1E13-3E13ions /
cm ^Two(See FIG. 32).

Subsequently, As is set to 15 KeV and 3E15 to 5E.
By obliquely implanting E15 ions / cm ² , an impurity diffusion layer for element isolation of a memory cell and a bit line are formed in a self-aligned manner (see FIG. 33).

Next, a silicon oxide film 2 serving as an insulating film is formed by HDP-CVD (high-density plasma chemical vapor deposition).
1 is deposited in a thickness of about 400 to 600 nm (see FIG. 34).

Next, a part of the silicon oxide film 21 is removed by, for example, a wet etch back method using diluted HF, and the upper surface of the silicon nitride film 17 is completely exposed (see FIG. 35).

Thereafter, the silicon nitride film 17 is removed with hot phosphoric acid (see FIG. 36).

Further, the silicon oxide film 21 is round-etched while removing the HTO film 16 by, for example, a wet etch-back method using diluted HF. Thus, the silicon oxide film 21 is buried in the space between the floating gates (see FIG. 37).

Thereafter, in order to increase the gate coupling ratio, a polysilicon film 22 doped with phosphorus as an impurity is deposited to a thickness of 100 nm (see FIG. 38).

Next, the CMP method (chemical mechanical polishing method)
Thereby, the polysilicon film 22 is polished until the silicon oxide film 21 in the space between the floating gates is exposed. The polished polysilicon film 22 becomes a part of the floating gate (see FIG. 39). At this time,
The polysilicon film 22 is also formed in the active region of the peripheral circuit transistor. This polysilicon film will be
It becomes a part of the gate electrode.

Thereafter, the ONO film 23 (silicon oxide film SiO ₂ / silicon nitride film / silicon oxide film SiO _{2) serving} as an insulating film between the floating gate and the control gate is formed.
Layer). That is, the ONO film 23 is formed by forming a 6 nm silicon oxide film on the surface of the floating gate by a thermal oxidation method, and by forming a 8 nm silicon oxide film by a CVD (chemical vapor deposition) method.
Is formed by sequentially forming a silicon nitride film having a thickness of 6 nm and a silicon oxide film having a thickness of 6 nm (see FIG. 40).

Next, after the memory array portion is covered with a resist pattern by a photo process, the ONO film 23 in the gate forming portion of the peripheral circuit transistor is removed by dry etching (see FIG. 41).

Next, after depositing a polysilicon film having a thickness of 100 nm as a control gate and a gate electrode of a peripheral circuit transistor, phosphorus is doped by ion implantation. Furthermore,
The polycide film 25 is formed by depositing a 100 nm WSi film. The polycide film 25 is connected to the polysilicon film 22 smoothed by the CMP method in the peripheral circuit transistor formation region (see FIG. 42).

Next, using the resist pattern 18 formed by the photo process as a mask, the control gate of the memory array portion and the gate of the peripheral circuit transistor are processed by reactive ion etching. That is, in order to form a control gate, the polycide film 25, the ONO film 23, and the polysilicon film 22 are sequentially etched and removed. When the etching of the polycide film 25 serving as the control gate and the ONO film 23 in the memory cell portion is completed, the polysilicon film 22 is partially etched in the peripheral circuit transistor formation region. Thereafter, the control gate and the gate of the peripheral circuit transistor are processed by etching the polysilicon film 22 with high selectivity with respect to the SiO ₂ film (FIG. 4).
3).

After the resist pattern 18 is removed, an impurity diffusion layer for element isolation in the memory array is formed using the control gate as a mask. For example, if boron is 0 degree,
10-40 KeV, 5E12-5E13 ions / cm
² is injected (FIG. 44).

Thereafter, a peripheral circuit transistor is formed by a known technique (FIG. 45).

Further, by forming the interlayer insulating film 32 and forming the contact 8 and the metal wiring, a nonvolatile semiconductor memory device can be obtained.

[0030]

However, in the conventional forming method as described above, it is necessary to align the bit line with the element isolation region of the selection gate and the peripheral circuit transistor formation region. Therefore, an alignment margin between the bit line and the element isolation region is required. Therefore, there is a problem that it is difficult to reduce the size of the memory array.

After removing the insulating film between the floating gate and the control gate, a polysilicon film for forming the control gate and the gate of the peripheral circuit transistor is deposited. Usually, an ONO film (three-layer laminated film of silicon oxide film SiO ₂ / silicon nitride film / silicon oxide film SiO ₂ ) is used as the insulating film. At this time, since the stacked gates of the select gate transistor and the peripheral circuit transistor electrically connect the floating gate and the control gate with low resistance, a pretreatment for removing a natural oxide film formed on the upper surface of the floating gate is required. is there.

However, if a pretreatment is performed using, for example, HF to remove the natural oxide film, the upper SiO ₂ film of the ONO film which is an insulating film between the floating gate and the control gate in the memory cell portion is reduced. Occurs. Therefore, there is a problem that the pretreatment with HF cannot be performed, and it is difficult to remove particles generated in the step of removing the ONO film.

In the step of forming the gates of the select gate transistor and the peripheral circuit transistor, the insulating film on the floating gate is removed before depositing the control gate polysilicon film. At this time, contact of the resist with the ONO film, which is an insulating film on the floating gate of the memory cell portion, cannot be avoided. Therefore, contamination from the resist and damage to the insulating film on the floating gate at the time of resist ashing may occur.
For this reason, there is a problem that the reliability of the insulating film between the floating gate and the control gate in the memory cell portion is reduced.

[0034]

According to the present invention, there is provided a memory cell comprising a plurality of memory cells each including a diffusion bit line formed on at least a part of a bottom surface and a side surface of a trench formed in a semiconductor substrate. A method of manufacturing a nonvolatile semiconductor memory device including a select gate transistor for selecting a line, a peripheral circuit transistor, and an element isolation region, wherein the element isolation region is formed in the trench, the trench including a diffusion bit line formed therein When,
A method for manufacturing a nonvolatile semiconductor memory device is provided, which includes a step of simultaneously forming a trench for forming an element isolation region.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One of the features of the present invention is that it includes a step of simultaneously forming a trench in which a diffusion bit line is formed and a trench for forming an element isolation region. Therefore, the steps can be shortened.

Further, the gates of the select gate transistor and the peripheral circuit transistor have a structure in which a floating gate and a control gate are connected, and the gate deposits a protective film of an insulating film on the floating gate. The step of removing the insulating film is included. Therefore, the treatment with HF can be sufficiently performed before depositing the polysilicon for the control gate, and the particles can be more completely removed. Further, since the insulating film on the floating gate is covered with the protective film, contact of the resist with the insulating film in the memory cell portion can be prevented. Therefore, the present invention, which can eliminate contamination from a resist and damage to an insulating film on a floating gate at the time of resist ashing, will be described in detail based on an embodiment. FIG. 1 shows a schematic plan view of a memory array according to an embodiment of the present invention. 2 (B), FIG. 2 (C), FIG. 2 (D) and FIG. 2 (E) are respectively a line BB of FIG.
It is a schematic sectional drawing of the CC line, the DD line, and the EE line.
FIGS. 3F, 3G, and 3H are schematic cross-sectional views taken along lines EF, GG, and HH of FIG. 1, respectively. Note that the configuration in FIGS. 1 to 3 is merely an example, and the present invention is not limited to this configuration.

In FIG. 1, a plurality of memory cells are arranged in a matrix to form a memory array. The diffusion bit lines are connected to select gates 9 provided on both sides of each memory array block in which memory cells are integrated.
Selected by. The select gate 9 is isolated by an element isolation region 7 in which an oxide film is buried in a trench formed simultaneously with a trench in which a diffusion bit line is formed.

Diffusion bit lines (eg, N ⁺ region 2
0) and the source / drain diffusion regions of the select gate transistor and the peripheral circuit transistor are connected. Further, it is connected via a contact 8 to a main bit line (not shown) formed by metal wiring.

The structure of the select gate transistor is as follows:
The structure of the peripheral circuit transistor may be the same or different.

Hereinafter, a method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 1 will be described with reference to schematic sectional views shown in FIGS. (A) of each drawing shows a cross section of the memory cell portion in the channel length direction, (B) of each drawing shows a cross section of the memory cell portion in the channel width direction, and (B) of each drawing shows a cross section of the peripheral circuit transistor in the channel length direction. (C) shows a cross section in the channel width direction of the peripheral circuit transistor in (D) of each figure.

First, an oxide film 11 to be a gate oxide film of a peripheral circuit transistor is formed on a P-type semiconductor substrate (for example, a silicon substrate) 10 by thermal oxidation (see FIG. 4).

Subsequently, the peripheral circuit transistor forming region other than the memory array portion, which is the region where the tunnel oxide film is formed, is covered with the resist pattern 12 by a photo process. Thereafter, wet etching is performed on the oxide film 11 by HF until the semiconductor substrate 10 is completely exposed (see FIG. 5).

Next, after the resist pattern 12 is removed, thermal oxidation for forming a tunnel oxide film of 9 to 11 nm is performed with the oxide film 11 left in the peripheral circuit transistor formation region. Thus, a gate oxide film 14 having an oxide film thickness of 14 to 16 nm is formed in the peripheral circuit transistor formation region, and a tunnel oxide film 13 having a thickness of 9 to 11 nm is formed in the memory cell portion (see FIG. 6).

Subsequently, a 50 nm polysilicon film (floating gate forming material film) 15 and a 100 nm HT
An O film 16 and a 250 nm silicon nitride film 17 are sequentially formed by a CVD method (see FIG. 7).

Next, a resist pattern 18 having an opening in a region to be a diffusion bit line of a memory cell and an element isolation region of a peripheral circuit transistor is formed by a photo process. Next, the silicon nitride film 17 is formed by dry etching.
HTO film 16, polysilicon film 15, gate oxide film 14
After the tunnel oxide film 13 is sequentially etched, the semiconductor substrate 10 is etched by about 20 nm (see FIG. 8). By this step, the memory array portion and the trench for element isolation of the peripheral circuit transistor can be simultaneously formed.

In order to improve the element isolation characteristics, B is implanted into the trench bottom at an implantation energy of 15 KeV and an implantation amount of 1 B.
E13 to 5E13 ions / cm ² may be implanted. The conductivity imparted to the semiconductor substrate by this implantation is eliminated in the bit line portion of the memory cell because As is implanted at a high concentration in a later step.

Next, the element isolation region of the peripheral circuit transistor is covered with a resist pattern 18 by a photo process.
Using the resist pattern 18 as a mask, As is implanted at an energy of 15 Ke so as to form an N ⁻ region 19 having an asymmetric structure of the memory cell on one side wall of the trench.
V, oblique implantation is performed under the conditions of an implantation amount of 1E13 to 3E13 ions / cm ² (see FIG. 9).

Subsequently, As is implanted at an energy of 15 Ke.
By performing the oblique implantation under the conditions of V and the implantation amount of 3E15 to 5E15 ions / cm ² , the impurity diffusion layer for element isolation of the memory cell and the bit line can be formed in a self-aligned manner (see FIG. 10).

Next, a silicon oxide film 2 serving as an insulating film is formed by HDP-CVD (high-density plasma chemical vapor deposition).
1 is deposited to a thickness of about 400 to 600 nm (see FIG. 11).

Next, the surface of the silicon oxide film 21 is removed by, for example, a wet etch back method using diluted HF, thereby forming the patterned silicon nitride film 17.
Is completely exposed (see FIG. 12).

Thereafter, the silicon nitride film 17 is removed with hot phosphoric acid (see FIG. 13).

Further, the silicon oxide film 21 is round-etched while removing the HTO film 16 by, for example, a wet etch-back method using diluted HF. Thus, the silicon oxide film 21 is buried between the floating gates (see FIG. 14).

Thereafter, to increase the gate coupling ratio, a polysilicon film 22 doped with phosphorus as an impurity is deposited to a thickness of 100 nm (see FIG. 15).

Further, the polysilicon film 22 is polished by the CMP method until the silicon oxide film 21 between the floating gates is exposed. As a result, a floating gate is formed (see FIG. 16). At this time, similarly, the polysilicon film 22 is formed also in the active region of the peripheral circuit transistor. This polysilicon film becomes a part of the gate electrode of the peripheral circuit transistor in a later step.

Thereafter, the ONO film 23 (silicon oxide film SiO ₂ / silicon nitride film / silicon oxide film SiO _{2) serving} as an insulating film between the floating gate and the control gate is formed.
Layer). That is, a 6 nm silicon oxide film is sequentially deposited on the floating gate surface by thermal oxidation, an 8 nm silicon nitride film and a 6 nm silicon oxide film are sequentially deposited by CVD (see FIG. 17).

Next, as a protective film for preventing damage to the ONO film 23 at the time of etching and resist ashing in a later step, a polysilicon film 24 is formed to a thickness of 30 nm to 50 nm.
m (see FIG. 18).

Next, the memory array portion is covered with a resist pattern 18 by a photo process. Thereafter, after removing the polysilicon film 24 in the gate formation region of the peripheral circuit transistor by dry etching, the ONO film 23 is similarly removed by dry etching (see FIG. 19).

Thereafter, the polysilicon film serving as the control gate of the memory cell and the gate of the peripheral circuit transistor is removed by 1
After depositing 00 nm, phosphorus is doped by ion implantation. Further, by depositing a WSi film, 100 nm
(A control gate forming material film) 25 is formed. In this case, only the silicide film made of WSi is present on the element isolation region of the peripheral circuit transistor. The polycide film 25 is a polysilicon film 24 in the memory array portion.
In the peripheral circuit transistor, it is connected to the polysilicon film 22 smoothed by the CMP method (FIG. 2).
0). The polycide film 25 may be replaced with a silicide film. In this case, the deposition of the polysilicon film is omitted and ON
After dry etching of the O film 23, a silicide film can be formed by directly depositing WSi.

Next, a resist pattern 18 is formed by a photo process. Using this pattern as a mask, the control gate of the memory array portion and the gate of the peripheral circuit transistor are processed by reactive ion etching. That is, the polycide film 25, the polysilicon film 24, the ONO film 23, and the polysilicon film 2 serving as control gates
2 are sequentially etched and removed. At this time, when the etching of the polycide film 25 serving as a control gate, the polysilicon film 24, and the ONO film 23 of the memory cell portion is completed, the etching is performed partway in the polysilicon film 22 in the peripheral circuit transistor formation region. After that, the SiO
_The control film and the gate of the peripheral circuit transistor are processed by etching the polysilicon film 22 with high selectivity for the _two films (see FIG. 21).

After removing the resist pattern 18, an impurity diffusion layer for element isolation of a memory cell is formed using the control gate as a mask. For example, 0 degree of boron, an implantation energy of 10 to 40 KeV, and an implantation amount of 5E12 to 5E1.
The implantation is performed under the condition of ³ ions / cm ² (FIG. 22).

Thereafter, peripheral circuit transistors are formed by a known technique (see FIG. 23).

Further, the interlayer insulating film 32 is formed by a known technique.
Is formed, and the contact 8 and the metal wiring are formed, whereby a nonvolatile semiconductor memory device can be obtained.

[0063]

According to the method of the present invention for manufacturing a semiconductor memory device in which a bit line is formed in a trench, a diffusion bit line, a select gate, and a trench in an element isolation region of a peripheral circuit portion are simultaneously formed. Therefore, the steps can be shortened. Further, the trench can be formed by self-alignment. Therefore, the area of the memory array region can be reduced.

Further, in order to connect the floating gate and the control gate, the insulating film on the floating is removed after the protection film for the insulating film on the floating is deposited. Therefore, the treatment with HF can be sufficiently performed before depositing the polysilicon for the control gate, and the particles can be more completely removed. Therefore, since the floating gate and the polysilicon for the control gate can be stably connected to each other with low resistance, the circuit operation becomes stable.

Further, the select gate and the peripheral circuit transistor have a structure in which a polysilicon film as a floating gate and a polysilicon film as a control gate are laminated in the same manner as the memory cell, and the polysilicon film of the floating gate and the control gate are formed. The insulating film on the floating gate is removed to connect with the polysilicon film. In the present invention, in this removal step, after depositing the protective film of the insulating film, the protective film and the insulating film on the floating gate are removed, so that the contact of the resist with the insulating film on the floating gate of the memory cell portion is reduced. Therefore, contamination from the resist and damage to the insulating film on the floating gate during resist ashing are eliminated. Therefore, the insulating film between the floating gate and the control gate in the memory cell portion can be made highly reliable.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 3 is a schematic sectional view of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 4 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 5 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 6 is a schematic sectional view of the process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 7 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 8 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 9 is a schematic cross-sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

10 is a schematic cross-sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

11 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

12 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

13 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

14 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 15 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

16 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

17 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

18 is a schematic sectional view of a process of the nonvolatile semiconductor memory device of FIG. 1;

19 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

20 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

21 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 22 is a schematic sectional view of the process of the nonvolatile semiconductor memory device of FIG. 1;

23 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 1;

FIG. 24 is a schematic plan view of a conventional nonvolatile semiconductor memory device.

FIG. 25 is a schematic sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 26 is a schematic sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 27 is a schematic sectional view of the nonvolatile semiconductor memory device of FIG.

FIG. 28 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 29 is a schematic sectional view of the process of the nonvolatile semiconductor memory device of FIG. 24;

30 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 31 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 32 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 33 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

34 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 35 is a schematic sectional view of the nonvolatile semiconductor memory device shown in FIG. 24;

36 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 37 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 38 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

39 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

40 is a schematic cross-sectional view of a step of the nonvolatile semiconductor memory device of FIG. 24;

41 is a schematic sectional view of the nonvolatile semiconductor memory device in FIG.

FIG. 42 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 43 is a schematic sectional view of the process of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 44 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

FIG. 45 is a schematic process sectional view of the nonvolatile semiconductor memory device of FIG. 24;

[Explanation of symbols]

Reference Signs List 5 gate 7, 31 element isolation region 8 contact 9 select gate 10 semiconductor substrate 11 oxide film 12, 18 resist pattern 13 tunnel oxide film 14 gate oxide film 15, 22, 24 polysilicon film 16 HTO film 17 silicon nitride film 19 N ⁻ Region 20 N ⁺ region 21 silicon oxide film 23 ONO film 25 polycide film 27 source / drain region 32 interlayer insulating film

Continued on front page F-term (reference) 5F101 BA02 BA13 BA36 BB05 BD05 BD06 BD09 BD10 BD32 BD35 BH19 BH21

Claims (2)

[Claims] A selection gate transistor for selecting a diffusion bit line, comprising a plurality of memory cells each including a diffusion bit line formed on at least a part of a bottom surface and a side surface of a trench formed in a semiconductor substrate;
A method of manufacturing a nonvolatile semiconductor memory device including a peripheral circuit transistor and an element isolation region, wherein the element isolation region is formed in the trench, wherein a trench in which a diffusion bit line is formed, a trench for forming an element isolation region, Forming a non-volatile semiconductor memory device at the same time. 2. The gate of the peripheral circuit transistor and the gate of the select gate transistor are formed of the same stacked body of a floating gate and a control gate as a memory cell, and a floating gate forming material film, an insulating film and Forming a protective film in this order;
Removing an insulating film and a protective film in a peripheral circuit transistor or select gate transistor formation region, forming a control gate formation material film, forming a trench for forming an element isolation region, and forming a floating gate formation material film And forming a control gate and a floating gate by patterning the control gate forming material film.