JP3651760B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of a semiconductor equipment, in particular those relating to the shape and control method thereof of the end portion of the insulator separated element regions by shallow trench isolation regions, for example in a non-volatile semiconductor memory of the batch erase type It is used for a NOR type flash EEPROM, a memory-embedded logic integrated circuit, and the like.
[0002]
[Prior art]
FIGS. 7A to 8C show a part of a manufacturing process of a flash EEPROM using the conventional embedded element isolation.
[0003]
First, as shown in FIG. 7A, impurities are introduced into the memory cell array region and the peripheral transistor region of the semiconductor substrate 101 so that the threshold values of the respective transistors have desired values, and then memory cells are formed on the entire surface of the substrate. An oxide film 102 to be a tunnel oxide film of the transistor is formed, and a polysilicon film 103 into which phosphorus is introduced as an impurity, a laminated film 104 of a CVD (chemical vapor deposition) nitride film and a CVD oxide film are deposited thereon.
[0004]
Next, a resist pattern (not shown) is formed on the substrate, and the laminated film 104 is patterned using the resist pattern, and then the resist pattern is removed.
[0005]
Thereafter, as shown in FIG. 7B, using the patterned laminated film 104 as a mask, the polysilicon film 103, the gate oxide film 102, and the silicon substrate 101 corresponding to the element isolation region formation planned portion are removed. Thus, a shallow trench is formed.
[0006]
Next, as shown in FIG. 7C, for example, an LP-TEOS (Low Pressure Tetra-Ethl-Oxide-Silicon) film 105 as a buried insulator is buried in the trench. Thereafter, the entire surface is flattened by a CMP (Chemical Mechanical Polishing) method or an etch back method, and the embedded insulator is moved back to the middle of the laminated film 104. Thereafter, a wet etching process is performed to completely remove the laminated film 104.
[0007]
Next, as shown in FIG. 8A, a polysilicon film 106 into which phosphorus is introduced as an impurity is deposited on the entire surface of the substrate, and a resist pattern (not shown) is formed thereon, which is used. The polysilicon film 106 is patterned. At this time, a slit 107 for dividing the polysilicon film 106 in the memory cell array region on the element isolation region is formed, and the polysilicon films 106 and 103 in the peripheral transistor region are removed. Thereafter, the resist pattern is peeled off.
[0008]
Next, an ONO insulating film (oxide film / nitride film / oxide film laminated film) 108 is formed on the entire surface of the substrate, the memory cell array region is covered with a resist (not shown), and ONO insulation in the peripheral transistor region is then performed. After removing the film 108 and the gate oxide film (tunnel oxide film) 102, the resist covering the memory cell array region is removed.
[0009]
When the slit 107 is formed in the memory cell array region, the polysilicon films 106 and 103 in the peripheral transistor region are left, and the polysilicon film 106 and 103 are removed when the ONO insulating film 108 and the gate oxide film (tunnel oxide film) 102 are removed. The silicon films 106 and 103 may be removed.
[0010]
Next, as shown in FIG. 8B, the gate oxide film 109 of the peripheral circuit transistor is formed.
[0011]
Next, as shown in FIG. 8C shown in a direction orthogonal to FIG. 8B, a polysilicon film into which impurities are introduced is deposited on the entire surface of the substrate, and in the memory cell array region, the polysilicon film, The ONO insulating film 108 and the polysilicon films 106 and 103 are patterned. Thereby, a laminated gate structure in which the control gate 110 and the floating gate 111 (polysilicon films 106 and 103) are formed in two layers is obtained. In the peripheral transistor region, the gate electrode 112 is formed by patterning the polysilicon film.
[0012]
Subsequently, although not shown in the figure, impurities that serve as the source / drain of the transistor are selectively introduced into the surface layer of the substrate, and further, interlayer insulating film deposition, contact opening, wiring formation, and surface protection insulating film deposition are performed. The flash EEPROM is completed.
[0013]
As described above, in a flash EEPROM having an element region insulated and isolated by an embedded element isolation region, the memory cell array region and the peripheral transistor region are each formed in order to optimize the performance of the MOS transistor in each region. Gate oxide films with different thicknesses are used.
[0014]
By the way, when manufacturing a gate oxide film having different film thicknesses in manufacturing a semiconductor device having an element region insulated by a buried element isolation region (for example, when adding two gate oxide films having different film thicknesses), Oxidizes the entire surface of the substrate to once form a gate oxide film having a first thickness, and then peels off the first gate oxide film in a region where a gate oxide film having a second thickness is to be formed. In addition, in the region where the first gate oxide film is to be formed, the gate oxide film having the second thickness is formed after the oxidation species are not supplied.
[0015]
There are various methods for forming gate oxide films having different film thicknesses. However, when considered in relation to the element isolation formation process, (1) a method of performing the element isolation process after forming all gate oxide films; (2) A method of forming all the gate oxide films after the element isolation process, and (3) As shown in FIGS. 7A to 8C, a part of the gate oxide film is an element. The method is roughly classified into a method of forming before the isolation forming step and forming the remainder of the gate oxide film after the element isolation forming step.
[0016]
In the above method (1), the insulating film in the element isolation region is not exposed to the peeling process at the same time in the peeling process necessary for separately attaching a plurality of gate oxide films, but in the thermal process after the gate oxide film is formed. The impurity profile of the channel region becomes gradual and is not suitable for improving the performance of the transistor.
[0017]
The method (2) can reduce the thermal process after forming the gate oxide film, and is suitable for improving the performance of the transistor. However, the element isolation region is not removed in the peeling process before forming the gate oxide film. Since the insulating film is also etched at the same time, a shape that adversely affects the transistor characteristics is formed.
[0018]
FIG. 9A shows a transistor in the memory cell array region in which the gate oxide film 102 is formed before the element isolation insulating film 105 is formed in the semiconductor device formed by using the method (3), for example, the flash EEPROM. An example of the shape in the vicinity of the element isolation region (end portion of the element region) is shown. Here, reference numeral 103 denotes a polysilicon film below the floating gate.
[0019]
FIG. 9B shows an end of the element region in the peripheral transistor region in which the gate oxide film 109 is formed after the element isolation insulating film 105 is formed in the flash EEPROM formed by using the method (3). FIG. 8B shows an example of the shape of the portion, which corresponds to the enlarged end portion corresponding to the portion surrounded by the dotted circle in FIG. 8B. Here, 112 is a gate electrode.
[0020]
The shape shown in FIG. 9B is compared with the shape shown in FIG. 9A in a portion where the element isolation insulating film 105 is etched in the peeling process of the gate oxide film (tunnel oxide film) 102 in the peripheral transistor region. Since the gate electrode 112 has a depressed shape, an electric field concentration occurs in the vicinity of the depressed portion during the operation of the transistor. In this portion, an inversion layer is formed with a lower gate voltage than the flat portion of the element region. As a result, a channel current flows.
[0021]
As a result, the leakage current increases in the region where the gate voltage of the transistor is low (subthreshold current region), and the current consumption increases. Even in the region where the gate voltage of the transistor is low, an inversion layer is formed at the corner of the edge of the device region, so that the subthreshold current characteristic of the transistor becomes discontinuous with respect to the gate voltage. Then, the operation of a transistor operated in a region where the gate voltage is low (for example, a peripheral circuit transistor in which a subthreshold current flows in a standby state) becomes unstable, and the yield of the product is lowered. Further, also in the case where the flash EEPROM is formed by using the methods (1) and (2), the peripheral circuit transistor side in which the gate electrode 112 is formed over the element region and the element isolation insulating film 105, Even if the depressed shape of the gate electrode 112 shown in FIG. 9B does not occur, more or less electric field concentration occurs at the corners of the end of the element region. For this reason, since the substantial threshold voltage at the end of the element region is lowered, the occurrence of the kink characteristic as described above also becomes a problem, and it becomes difficult to operate the transistor stably.
[0022]
On the other hand, in the memory cell array region, as shown in FIG. 9A, a buried element isolation region is formed in a self-aligned manner with the polysilicon film 103 below the floating gate, and the floating gate above the element isolation insulating film 105 is formed. And the end of the element region are not close to each other, the kink characteristics do not become a big problem.
[0023]
[Problems to be solved by the invention]
Manufacturing method of the conventional semiconductor equipment as described above, isolation and due to the shape of the end portion of the element region in the peripheral transistor region area gate voltage is low the transistor forming the gate insulating film after performing Leakage current increases, current consumption increases, the subthreshold current characteristics become discontinuous with respect to the gate voltage, and the operation of the transistor operating in the region where the gate voltage is low becomes unstable. There was a problem that the rate fell.
[0024]
The present invention has been made to solve the above problems, and can suppress leakage current and current consumption in a region where the gate voltage of the peripheral circuit transistor is low, and the subthreshold current characteristic becomes continuous with respect to the gate voltage. , operation of the gate voltage is low region becomes stable, and an object thereof is to provide a semiconductor equipment manufacturing method which makes it possible to improve the yield of products.
[0026]
[Means for Solving the Problems]
According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a nonvolatile semiconductor memory having a memory cell array region and a peripheral transistor region in which a peripheral circuit transistor is formed, the first gate insulation for the memory cell transistor is formed on the entire surface of the semiconductor substrate. Forming a film and forming a polysilicon film and an insulating film thereon; forming a trench for forming an isolation region in the insulating film, the polysilicon film, the first gate insulating film, and the semiconductor substrate; Covering the memory cell array region, removing the first gate insulating film on the end portion of the element region in the peripheral transistor region, the surface of the trench and the end portion of the element region in the peripheral transistor region, and Oxidizing the surface of the portion between the polysilicon film and the insulator embedded in the trench A step of filling and planarizing the entire surface; a step of removing the insulating film on the polysilicon film; and removing the polysilicon film and the first gate insulating film in the peripheral transistor region; Forming a gate insulating film on the second gate insulating film in the peripheral transistor region; and forming a gate electrode on the second gate insulating film in the peripheral transistor region. And a step of selectively introducing an impurity to be a source / drain of a transistor into the surface layer portion of the substrate .
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0028]
<First embodiment>
FIGS. 1A to 2D show a part of the manufacturing process of the NOR type flash EEPROM according to the first embodiment of the present invention. This flash EEPROM has an element region isolated by a buried element isolation region, and the memory cell array region and the peripheral transistor region have different gate oxide film thicknesses.
[0029]
First, as shown in FIG. 1A, impurities are introduced into the memory cell array region and the peripheral transistor region of the semiconductor substrate 101 so that the threshold values of the respective transistors have desired values, and then memory cells are formed on the entire surface of the substrate. A gate oxide film 102 which becomes a tunnel oxide film of the transistor is formed, and a laminated film 104 of a polysilicon film 103, a CDV nitride film and a CVD oxide film is deposited thereon.
[0030]
Next, a resist pattern (not shown) is formed on the substrate, and the laminated film 104 is patterned using the resist pattern, and then the resist pattern is removed.
[0031]
Thereafter, as shown in FIG. 1B, using the patterned laminated film 104 as a mask, the polysilicon film 103, the gate oxide film 102, and the silicon substrate 101 corresponding to the element isolation region formation planned portion are removed. Thus, a shallow trench is formed.
[0032]
Next, after the memory cell array region is covered with a resist (not shown), a wet etching process (or an isotropic dry etching process or both processes) is performed on the peripheral transistor region, and FIG. As shown in FIG. 5, a part of the gate oxide film 102 on the element region in the peripheral transistor region (a part on the end portion of the element region) is removed to make it easy to supply the oxidant to the end portion of the element region.
[0033]
Thereafter, the resist is removed, and an oxide film 113 is formed by oxidation in an atmosphere having a temperature of 900 ° C. to 1000 ° C. and an oxygen concentration of 10% so that the oxide film thickness on the surface of the trench becomes 20 nm or more. To do. At this time, the portion between the element region end of the peripheral transistor region and the polysilicon film 103 thereabove is supplied with an oxidant, so that oxidation proceeds, so as shown in FIG. And the end of the element region has a rounded shape.
[0034]
Subsequently, as shown in FIG. 2A, for example, an LP-TEOS film 105 which is a buried insulator is buried in the trench. Thereafter, the entire surface is flattened by a CMP method or an etch back method, the embedded insulator is retracted to the middle of the laminated film 104, and then a wet etching process is performed to remove the laminated film 104.
[0035]
Next, as shown in FIG. 2B, a polysilicon film 106 into which phosphorus is introduced as an impurity is deposited on the entire surface of the substrate, and a resist pattern (not shown) is formed thereon, which is used. By patterning the polysilicon film 106, slits 107 for dividing the polysilicon film 106 in the memory cell array region on the element isolation region are formed, and the polysilicon films 106 and 103 in the peripheral transistor region are removed. Thereafter, the resist pattern is peeled off.
[0036]
Next, an ONO insulating film 108 is formed on the entire surface of the substrate, the memory cell array region is covered with a resist (not shown), and then the ONO insulating film 108 and the gate oxide film (tunnel oxide film) 102 in the peripheral transistor region are formed. After the removal, the resist covering the memory cell array region is removed.
[0037]
When the slit 107 is formed in the memory cell array region, the polysilicon films 106 and 103 in the peripheral transistor region are left, and the polysilicon film 106 and 103 are removed when the ONO insulating film 108 and the gate oxide film (tunnel oxide film) 102 are removed. The silicon films 106 and 103 may be removed.
[0038]
2D, the gate oxide film 109 of the peripheral circuit transistor is formed as shown in FIG. 2C. Further, FIG. 2D is viewed from the direction orthogonal to FIG. 2C. ), A polysilicon film doped with impurities is deposited on the entire surface of the substrate.
[0039]
In the memory cell array region, the control gate 110 and the floating gate 111 (polysilicon films 106 and 103) are formed in two layers by patterning the polysilicon film, the ONO insulating film 108, and the polysilicon films 106 and 103. A stacked gate structure is formed, and the gate electrode 112 is formed by patterning the polysilicon film in the peripheral transistor region. Subsequently, although not shown in the figure, impurities that serve as the source / drain of the transistor are selectively introduced into the surface layer of the substrate, and further, interlayer insulating film deposition, contact opening, wiring formation, and surface protection insulating film deposition are performed. The flash EEPROM is completed.
[0040]
FIG. 3A shows an end portion corresponding to a portion indicated by a dotted circle in FIG. 2C (that is, an element in a peripheral transistor region in which a gate oxide film is formed after forming an element isolation insulating film). An example of the shape of the end portion of the region is shown enlarged . Further, FIG. 3 (b) shows an enlarged example of a shape after completed device in the portion corresponding to FIG. 3 (a). Here, 101 is a semiconductor substrate, 105 is an element isolation insulating film, 109 is a gate oxide film, and 112 is a gate electrode.
[0041]
As can be seen from FIGS. 3A and 3B, the gate oxide film 109 on the edge of the element region has a shape including a bird's beak, and therefore, compared with FIG. 9B shown in the conventional example in which no bird's beak exists. Thus, film reduction at the end of the element region in the peeling step during the gate attaching step is suppressed, and electric field concentration at the end of the element region is less likely to occur.
[0042]
Further, the shape of the depression of the gate electrode 112 formed on the gate oxide film 109 at the end of the element region in the peripheral transistor region shown in FIGS. 3A and 3B is shown in FIG. 9B shown in the conventional example. The difference d between the height of the flat part of the element region and the height of the lowest part of the gate electrode above it is about 4 nm as a result of actual measurement. Met.
[0043]
<Second embodiment>
FIGS. 4A to 5D show a part of the manufacturing process of the NOR type flash EEPROM according to the second embodiment of the present invention. This flash EEPROM has an element region isolated by a buried element isolation region, and the memory cell array region and the peripheral transistor region have different gate oxide film thicknesses.
[0044]
In the second embodiment, steps similar to those of the conventional example described above with reference to FIGS. 7A to 8A are performed as shown in FIGS. 4A to 5A. At this stage, the corners of the end of the element region in the peripheral transistor region are exposed.
[0045]
Next, with the memory cell array region covered with a resist, as shown in FIG. 5B, wet etching processing (or isotropic dry etching processing, or both processing) is performed, thereby exposing exposed elements. The corner of the region end is etched to form a rounded shape.
[0046]
Next, after removing the resist covering the memory cell array region, as shown in FIG. 5C, a gate oxide film 109 of a peripheral circuit transistor is formed as in the prior art, and further, FIG. As shown in FIG. 5D, viewed from a direction orthogonal to (), a polysilicon film doped with impurities is deposited on the entire surface of the substrate. In the memory cell array region, the polysilicon film, the ONO insulating film 108, the polysilicon films 106 and 103 are patterned, and the control gate 110 and the floating gate 111 (polysilicon films 106 and 103) are formed into two layers. A gate electrode 112 is formed by patterning the polysilicon film in the peripheral transistor region. Subsequently, although not shown in the figure, impurities that serve as the source / drain of the transistor are selectively introduced into the surface layer of the substrate, and further, interlayer insulating film deposition, contact opening, wiring formation, and surface protection insulating film deposition are performed. The flash EEPROM is completed.
[0047]
FIG. 6 shows an end portion corresponding to a portion indicated by a dotted circle in FIG. 5C (that is, an end of the element region in the peripheral transistor region in which the gate oxide film is formed after forming the element isolation insulating film). An example of the shape of the part) is enlarged. Here, 101 is a semiconductor substrate, 105 is an element isolation insulating film, and 109 is a gate oxide film.
[0048]
As can be seen from FIG. 6, since the end of the element region has a rounded shape, electric field concentration at the end of the element region, which has been a problem in the past, is suppressed.
[0049]
In summary, in the conventional manufacturing method, corners are exposed at the end of the element region in the step of removing the ONO film and the tunnel oxide film before forming the gate oxide film in the peripheral transistor region.
[0050]
As a result, electric field concentration occurs at the edge of the element region during the operation of the peripheral circuit transistor, the leakage current of the peripheral circuit transistor increases, the current consumption of the device increases, and the subthreshold characteristic of the peripheral circuit transistor becomes the gate voltage. On the other hand, the discontinuity caused the peripheral circuit to malfunction, resulting in a decrease in product yield.
[0051]
On the other hand, in the manufacturing method according to the embodiment of the present invention, (1) wet etching treatment, isotropic dry etching treatment, oxidation treatment, or a composite treatment thereof is performed on the edge of the device region in the peripheral transistor region. Thus, the curvature of the end portion of the element region is increased, or (2) a bird's beak is placed at the end portion of the element region during the element isolation forming step of the peripheral transistor region.
[0052]
As a result, the gate electrode can be prevented from dropping at the end of the element region so that the gate electrode does not concentrate at the end of the element region, the leakage current of the peripheral circuit transistor is suppressed, and the subthreshold of the peripheral circuit transistor is suppressed. Since the current characteristics are improved, the power consumption of the product can be reduced and the yield can be increased.
[0053]
As a method for rounding off the corners of the exposed element region, it is generally known that when oxidation is performed in a state where oxygen is supplied at a rate, the corners are more easily oxidized than flat portions.
[0054]
Therefore, instead of the processing in each of the above embodiments, before forming the gate of the peripheral circuit transistor, oxidation is performed under conditions of high temperature and low oxygen supply, for example, 1000 ° C., 90% nitrogen, 10% oxygen. Even if this step is added, the corners of the exposed end of the element region can be rounded, and the same effect can be obtained even if the gate oxide film forming step itself of the peripheral circuit transistor is used as the supply-limited oxidation method. Of course, the same effect can be obtained by combining these methods.
[0055]
The semiconductor device of the present invention is not limited to the flash EEPROM of the above embodiment, and a memory cell array region in which a plurality of memory cell transistors are formed, and an element region of the memory cell transistor is insulated and isolated by a buried element isolation region; A plurality of peripheral circuit transistors of the memory cell array, and a peripheral transistor region in which an element region of the peripheral circuit transistor is insulated and isolated by a buried element isolation region, and a curvature of an end portion of the element region of the peripheral circuit transistor is The curvature is set substantially larger than the curvature of the end of the element region of the memory cell transistor. In other words, (1) and (2) as described above. Even when the gate oxide film of the memory cell array region and the peripheral transistor region is separately used by using any of the methods (3), the corners of the end portions of the element regions isolated by the buried element isolation region in the peripheral transistor region are Rounding is extremely effective in suppressing the kink characteristics of the peripheral circuit transistor in which the gate electrode is formed extending from the element region to the element isolation region.
[0056]
The semiconductor device manufacturing method of the present invention is not limited to a flash EEPROM, and a semiconductor in which a part of the gate insulating film is formed before the element isolation forming step and the remainder of the gate insulating film is formed after the element isolation forming step. It can be applied when manufacturing the device.
[0057]
【The invention's effect】
According to manufacturing method of semiconductor equipment of the present invention as described above, it can suppress the leakage current and the current consumption of the region the gate voltage is low the transistor by rounding the shape of the end portion of the element region, subthreshold current The characteristics become continuous with respect to the gate voltage, the operation of the transistor in a region where the gate voltage is low becomes stable, and the yield of the product can be improved.
[0058]
Accordingly, the present invention is applied to, for example, a flash EEPROM and a method for manufacturing the same, and the curvature of the end of the element region in the peripheral transistor region is set larger than the curvature of the end of the element region in the memory cell array region. Leakage current can be reduced and power consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a part of a manufacturing process of a NOR type flash EEPROM according to a first embodiment of the present invention;
2 is a cross-sectional view showing a part of the process that follows the process of FIG. 1. FIG.
FIG. 3 is an enlarged cross-sectional view showing an example of the shape of a portion indicated by a circle in FIG. 2C and an example of the shape of the portion after the device is completed.
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a NOR type flash EEPROM according to a second embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a part of the process that follows the process of FIG. 4;
6 is an enlarged cross-sectional view showing an example of the shape of a portion indicated by a circle in FIG.
FIG. 7 is a cross-sectional view showing a part of a manufacturing process of a flash EEPROM using conventional buried element isolation.
8 is a cross-sectional view showing a part of the process that follows the process of FIG. 7. FIG.
FIG. 9 shows an example of the shape of an element isolation region in the vicinity of an element isolation region (an end portion of an element region) and an element isolation insulating film in a memory cell array region in which a gate oxide film is formed before forming an element isolation insulating film in a conventional flash EEPROM; Sectional drawing which shows an example of the shape of the edge part of the element region in the peripheral transistor area | region which formed the gate oxide film after forming this.
[Explanation of symbols]
101 ... Semiconductor substrate,
102: Tunnel oxide film,
103, 106 ... phosphorous doped polysilicon,
104: a laminated film of a CVD nitride film and a CVD oxide film,
105: buried insulating film,
107 ... Slit,
108 ... ONO insulating film,
109 ... Gate oxide film of peripheral circuit transistor,
110 ... Control gate of memory cell transistor,
111: Floating gate of memory cell transistor,
112: Peripheral circuit transistor gate electrode.

Claims (2)

In manufacturing a nonvolatile semiconductor memory having a memory cell array region and a peripheral transistor region in which peripheral circuit transistors are formed,
Forming a first gate insulating film for a memory cell transistor on the entire surface of the semiconductor substrate, and forming a polysilicon film and an insulating film thereon;
Forming a trench for forming an element isolation region in the insulating film, the polysilicon film, the first gate insulating film, and the semiconductor substrate;
Removing the first gate insulating film on the edge of the element region of the peripheral transistor region after covering the memory cell array region;
Oxidizing the surface of the trench and the surface of the portion between the edge of the element region in the peripheral transistor region and the polysilicon film thereon;
Filling the trench with a buried insulator and planarizing the entire surface;
Removing the insulating film on the polysilicon film;
Forming a second gate insulating film for a peripheral circuit transistor after removing the polysilicon film and the first gate insulating film in the peripheral transistor region;
Forming a stacked gate structure including the polysilicon film as a floating gate in the memory cell array region, and forming a gate electrode on the second gate insulating film in the peripheral transistor region;
And a step of selectively introducing an impurity to be a source / drain of the transistor into a surface layer portion of the substrate. In manufacturing a nonvolatile semiconductor memory having a memory cell array region and a peripheral transistor region in which peripheral circuit transistors are formed,
Forming a first gate insulating film for a memory cell transistor on the entire surface of the semiconductor substrate and forming a polysilicon film thereon;
Forming a trench for forming an isolation region in the polysilicon film, the first gate insulating film and the semiconductor substrate;
Filling the trench with a buried insulator and planarizing the entire surface;
Forming an inter-gate insulating film for insulating between the floating gate and the control gate of the memory cell transistor on the entire surface of the substrate;
Removing the inter-gate insulating film, the polysilicon film and the first gate insulating film in the peripheral transistor region to expose the element region;
Etching the corners of the edge of the device region exposed in the peripheral transistor region to form a round shape;
Forming a second gate insulating film for the peripheral circuit transistor in the peripheral transistor region;
Forming a stacked gate structure including the polysilicon film as a floating gate in the memory cell array region, and forming a gate electrode on the second gate insulating film in the peripheral transistor region;
And a step of selectively introducing an impurity to be a source / drain of the transistor into a surface layer portion of the substrate.

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