CN1267915A - Non-volatile memory of semi-conductor and its producing method - Google Patents

Non-volatile memory of semi-conductor and its producing method Download PDF

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Publication number
CN1267915A
CN1267915A CN00104074A CN00104074A CN1267915A CN 1267915 A CN1267915 A CN 1267915A CN 00104074 A CN00104074 A CN 00104074A CN 00104074 A CN00104074 A CN 00104074A CN 1267915 A CN1267915 A CN 1267915A
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film
technology
memory cell
peripheral circuit
mentioned
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间愽顕
磯边和亚树
山田诚司
松井法晴
森诚一
谷本正男
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Toshiba Corp
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Toshiba Corp
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Priority claimed from JP07307499A external-priority patent/JP3651760B2/en
Priority claimed from JP18511899A external-priority patent/JP3833854B2/en
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Publication of CN1267915A publication Critical patent/CN1267915A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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Abstract

A manufacturing method of nonvolatile semiconductor memory device is disclosed, wherein trench-type devices are separated to form the device region and which have memory cell part disposed with a floating gate and peripheral circuit part. Before an STI trench is embedded with an insulator, a bird's beak oxide film in the upper end of an element region of a peripheral circuit is formed larger than that of a memory cell. Specifically, before an oxidation process for allowing the bird's beak to enter, the memory cell is covered with an oxidation-resistant film or an oxide-nitride film, or an STI trench of the peripheral circuit is formed first, then the bird's beak of the end of the element region of the peripheral circuit is formed large. Otherwise, the oxide-nitride film is formed on the STI sidewall of the peripheral circuit part to prevent film reduction of a sidewall insulation film at the time of etching the oxidation film.

Description

Nonvolatile semiconductor memory device and manufacture method thereof
The present invention relates to integratedly on same chip have control grid and the stack gate polar form memory cell of floating grid and the Nonvolatile semiconductor memory device and a manufacture method thereof of peripheral circuit thereof, be particularly related to floating grid and separate from mating landform grooving element, and be suppressed at Nonvolatile semiconductor memory device and the manufacture method thereof that the bending effect takes place in the peripheral circuit transistor partly with polysilicon layer.
The integrated Nonvolatile semiconductor memory device that has the stack gate polar form memory cell of control grid and floating grid and drive the peripheral circuit of this memory cell is known for people on same chip.General in such semiconductor storage, separate (shallow-trench isolation: STI) with polycrystalline silicon membrane from mating landform grooving element with floating grid, for the transistor of peripheral circuit, after removing the polysilicon that this floating grid uses, carry out once more gate oxidation and electrode and form.
When this floating grid of removal is used polysilicon, the end of exposing the peripheral circuit element region, the gate electrode that forms on its element area falls into and is formed into the upper side of element region sometimes then.If falling into of such gate electrode taken place, then form parasitic transistor at the element region lateral parts, in the drain voltage current characteristics curve of MOSFET, result from the characteristic so-called bending effect of low threshold value of this parasitic transistor with having overlapped.If this bending effect has taken place, the problem of electric current increase etc. in the time of then will causing the memory standby.
In order to prevent such bending effect, need between element region and polysilicon layer, to form in advance a large amount of beaks.Particularly, if the action of extracting electronics out at silicon substrate from floating grid, then in change of shape part electric field will take place will concentrate the dispersion that brings the removing speed of each unit.The dispersion of this removing speed causes removing the Vth distribution range and enlarges, and causes the problem of removing in NOR type flash memory.Yet if only do not become the oxidation of beak degree in memory cell, gate electrode drops into the bending effect will take place among the STI in the peripheral circuit part.Like this, the increase of following the subthreshold value of peripheral circuit to sew, the current sinking when increasing the semiconductor storage standby.
Explain above problem with reference to Figure 24 A～24B to Figure 26 A～26C.
After having formed tunnel oxide film 102 on the silicon substrate 101, deposit constitutes the 1st polysilicon layer 103 (Figure 24 A) of the underclad portion of floating grid.Then, in order to form the element Disengagement zone, form shallow slot (STI district) 104 (Figure 24 B).At this moment, coupling ground forms the end and the STI of floating grid certainly, and floating grid can not fall into the STI groove, is difficult to take place the action dispersion of memory cell.In this sti region, imbed dielectric film 1055, then, in deposit become after the 2nd polysilicon layer 106 of top section of floating grid, separate in each unit (Figure 24 C).
Then, in the above, form the dielectric film 107 between floating grid and the later control grid that forms.The normally three-layer structure of oxide-film/nitride film/oxide-film (Figure 24 D).Begin to illustrate the formation technology of peripheral circuit part from next figure.
Remove the dielectric film 107 of peripheral circuit part, floating grid 103,106, tunnel oxide film 102.In removing the wet corrosion technique of this tunnel oxide film, the STI end imbeds that dielectric film 105 is shunk back and situation that hollow takes place sometimes.In this case, the gate electrode 108 of peripheral circuit when covering the regional side of AA (active area), causing that the AA edge gate electrode that electric field concentrates takes place is overlapping, forms parasitic transistor as shown in figure 25.This parasitic transistor has low threshold property, and the bending effect takes place on the drain voltage current characteristics of this main transistor that will overlap.
As the method that prevents this point, shown in Figure 26 A, like that, have imbedding before the dielectric film 205 in forming STI204, carry out oxidation fully, on the interface of the 1st polysilicon film 203 and silicon substrate 201, be pre-formed the method for beak.If do like this, then in peripheral circuit part, after having removed polysilicon film and tunnel oxide film, also shown in Figure 26 B like that, can prevent the shrinking back of dielectric film in the STI end.Polysilicon layer 206 is the 2nd polysilicon layers that become the top section of floating grid.The 207th, dielectric film, the 208th, polysilicon layer.
Yet, if carry out so sufficient oxidation, known very big problem will take place.Promptly, shown in Figure 26 C, if between the floating grid 203 of memory cell areas and silicon substrate 202, invade beak greatly, then because the face orientation of polysilicon layer is various therefore shape will disperse, and convex shape will appear by oxidation, concentrate electric field here.Disperse if such shape has taken place, for example, the difference of the draw speed when occurring in from action that floating grid has carried out extracting electronics out causes the such problem of Vth distributed expansion of eliminating.Eliminating widely to be distributed in to bring so-called action of removing excessively bad in the NOR type flash memory.
As described above, in STI type Nonvolatile semiconductor memory device in the past,, on polysilicon and silicon substrate interface, strengthen sometimes and form beak in order to suppress the bending effect of peripheral circuit transistor.Yet this will also invade beak in a large number between the floating grid of memory cell part and silicon substrate, and therefore the difference of the draw speed when floating grid has carried out extracting the electronics action out take place, and produce the such problem of Vth distributed expansion of removing.
The present invention produces in view of the above problems, purpose is to provide the characteristic of memory cell part to disperse few, and in peripheral circuit part, do not bend effect, thereby the Nonvolatile semiconductor memory device and the manufacture method thereof of current sinking when not increasing standby.
In order to achieve the above object, the manufacture method of the Nonvolatile semiconductor memory device of a form of the present invention is to separate with groove-shape element to form element region, and have the manufacture method of the Nonvolatile semiconductor memory device of the memory cell part that comprises floating grid and peripheral circuit part thereof, be characterised in that to have the technology that on silicon substrate, forms polysilicon layer via dielectric film; In order to form element region, coupling ground carries out etching to this polysilicon layer and dielectric film, silicon substrate certainly, forms the technology of the element separation in bottom having and embracing element district with a plurality of grooves of groove in silicon substrate; The technology of processing being justified in each end of the element region face relative with polysilicon layer by oxidation; Cover the technology of memory cell part with film with oxidative resistance; Oxidation is added in formation at above-mentioned oxide-resistant film later on, at the element region of peripheral circuit part, forms the technology of the beak shape oxide-film thicker than memory cell part between the end of the silicon substrate face relative with polysilicon layer.
In above-mentioned manufacture method, in deposit after the above-mentioned oxide-resistant film, before the oxidation of carrying out for peripheral circuit part, in the memory cell part, and then can also have the technology of optionally removing above-mentioned oxide-resistant film, make only at the residual oxide-resistant film of floating grid lateral parts.
In addition, can also after the oxidation of having carried out for the peripheral circuit part, remove the oxide-resistant film that covers the memory cell part.
In order to achieve the above object, the manufacture method of the semiconductor storage of another form of the present invention is to separate with groove-shape element to form element region, and have the manufacture method of the Nonvolatile semiconductor memory device of the memory cell part that comprises floating grid and peripheral circuit part thereof, be characterised in that to have the technology that on silicon substrate, forms polysilicon layer via the dielectric film lamination; Only corrode to coupling polysilicon layer and dielectric film, silicon substrate certainly, form the 1st element and separate the technology of using groove in the peripheral circuit part; In the peripheral circuit part, oxidation is carried out in each end of the element region face relative with polysilicon layer, form the technology of beak shape oxide-film; From the polysilicon layer of coupling ground corrosion memory cell part and dielectric film, silicon substrate, form the 2nd element and separate technology with groove; After the separation of the 2nd element forms with groove, oxidation is carried out in each end of the element region of the said memory cells part face relative with polysilicon layer, form the technology of the beak shape oxide-film thinner than the beak shape oxide-film of formation in the peripheral circuit part.
In order to achieve the above object, the manufacture method of the Nonvolatile semiconductor memory device of another form of the present invention is to separate with groove-shape element to form element region, and have the manufacture method of the Nonvolatile semiconductor memory device of the memory cell part that comprises floating grid and peripheral circuit thereof, be characterised in that to have the technology that on silicon substrate, forms oxide-resistant film via the dielectric film lamination; Optionally remove the oxide-resistant film of memory cell part and the technology of dielectric film; On the memory cell part, form tunnel oxide film, then it is carried out the technology that nitrogen treatment constitutes tunnel film nitrogen oxidation film; On the top of the tunnel nitrogen oxidation film of memory cell part and the top of the oxide-resistant film of peripheral circuit part, form the technology of polysilicon layer; From coupling ground corrosion polysilicon and silicon substrate, form the technology of the separatory groove of element; After the element separation forms with groove, between the end of the element region face relative, form beak shape oxide-film, in the peripheral circuit part, form the technology of the beak shape oxide-film thicker than the memory cell part with polysilicon layer by oxidation.
In order to achieve the above object, the manufacture method of the Nonvolatile semiconductor memory device of another example of the present invention is to separate with groove-shape element to form element region, and have the manufacture method of the Nonvolatile semiconductor memory device of the memory cell part that comprises floating grid and peripheral circuit part thereof, be characterised in that to have the technology that on silicon substrate, forms polysilicon layer via dielectric film; From coupling ground this polysilicon layer of corrosion and silicon substrate, form the technology of element separation with groove in order to form element region; By oxidation, the technology that processing is justified in the element region and the end of each relative face of polysilicon; Only cover the technology of memory cell part with silicon fiml; Oxidation is added in covering at above-mentioned silicon fiml later on, between the silicon substrate and the end to the polysilicon layer apparent surface of peripheral circuit part, forms the technology of the beak shape oxide-film thicker than memory cell; The silicon fiml that covers the memory cell part is made the technology of oxide-film.
In order to achieve the above object, the Nonvolatile semiconductor memory device of another form of the present invention is characterised in that and has Semiconductor substrate; Formed the memory cell part on the above-mentioned Semiconductor substrate of a plurality of memory cell; Formed the peripheral circuit part on the above-mentioned Semiconductor substrate of circuit of control said memory cells; Be respectively formed in said memory cells part and the peripheral circuit part a plurality of element regions that separated by a plurality of grooves; Be formed on the nitrogen oxidation film of above-mentioned groove inwall; The dielectric film of the above-mentioned groove of landfill; On the element region of above-mentioned peripheral circuit, via the film formed gate electrode of gate insulator of having stipulated the end with above-mentioned nitrogen oxidation film.
The manufacture method of the semiconductor storage of another form of the present invention is characterised in that to have and forms dielectric film and the technology that becomes the polysilicon layer of floating grid on silicon substrate; From coupling ground this polysilicon layer of corrosion and silicon substrate, form the technology of element separation with groove; Form the technology of silicon nitrogen oxidation film at the sidewall of the inwall of groove and polysilicon.
In this manufacture method, the technology that forms the silicon nitrogen oxidation film at the sidewall of the inwall of groove and polysilicon also can be to have formed silicon nitride film with after-applied nitrogen oxidation processes at the inwall of groove and the sidewall of polysilicon layer, forms the technology of nitrogen oxidation film.
The semiconductor storage of another form of the present invention is characterised in that to have a plurality of semiconductor memory cell transistors of formation, by imbedding the element Disengagement zone the memory cell array district of the transistorized element region insulated separation of said memory cells; Form the peripheral circuit transistor of a plurality of memory cell arrays, by imbedding the element Disengagement zone the peripheral transistor district of the element region insulated separation of above-mentioned peripheral circuit transistor, the curvature of the element region end in above-mentioned peripheral circuit transistor district is set at that the curvature than the transistorized element region of said memory cells end is big in fact.
In this semiconductor device, the height of the flat in said elements district can be more than the 4nm with the difference of the height of the lowermost portion of the gate electrode that is positioned at its top.
In addition, in this semiconductor device, the action of above-mentioned peripheral circuit transistor can provide the bias potential that flows through subthreshold current during for holding state.
In addition, in this semiconductor device, at least a portion of the transistorized gate electrode of said memory cells also can be carried out from coupling with the element Disengagement zone of imbedding in the said memory cells array area.
In addition, in this semiconductor storage, the said memory cells transistor can be the memory cell with nonvolatile semiconductor memory of floating grid.
The manufacture method of the semiconductor device of another form of the present invention is a part that formed the gate insulating film of MOS transistor before element separates formation technology, after forming technology, the element Disengagement zone forms in the manufacturing of semiconductor device of other parts of above-mentioned gate insulating film, be characterised in that the formation MOS transistor, make that separate forming the curvature of element region end that technology forms the MOS transistor of gate insulating film later at said elements compares with the curvature of the element region end of separating the MOS transistor that forms the gate insulating film that forms before the technology at said elements and strengthen substantially.
The manufacture method of the semiconductor device of another form of the present invention is to have the memory cell array district and forming in the manufacturing of nonvolatile semiconductor memory in peripheral transistor district of its peripheral circuit transistor, be characterised in that to have on whole of Semiconductor substrate, to form the 1st gate insulating film that memory cell transistor is used, form the technology of polysilicon film and dielectric film in the above; On above-mentioned exhausted adipose membrane, polysilicon film, the 1st gate insulating film and Semiconductor substrate, form the element Disengagement zone and form the technology of using groove; On the basis that has covered the said memory cells array area, the technology of the 1st gate insulating film on the element region end in removal peripheral transistor district; The surface technology of carrying out oxidation of part between element region end in the surface of above-mentioned groove and the peripheral transistor district and the polysilicon film above it; In above-mentioned groove, imbed, make whole smooth technology imbedding insulator; Remove the technology of the dielectric film on the above-mentioned polysilicon film; After the polysilicon film of having removed above-mentioned peripheral transistor district and the 1st gate insulating film, the technology of the 2nd gate insulating film that the formation peripheral circuit transistor is used; In the said memory cells array area, form the stacked gate structure that has possessed above-mentioned polysilicon film as floating grid, on above-mentioned the 2nd gate insulating film, form the technology of gate electrode in above-mentioned peripheral transistor district; In optionally the mix technology of impurity of source/leakage of transistor formed of underlayer surface part.
The manufacture method of the semiconductor device of another form of the present invention is to have the memory cell array district and forming in the manufacturing of nonvolatile semiconductor memory in peripheral transistor district of its peripheral circuit transistor, be characterised in that on whole of Semiconductor substrate, to form the 1st gate insulating film that memory cell transistor is used, form the technology of polysilicon film in the above; On above-mentioned polysilicon film, the 1st gate insulating film and Semiconductor substrate, form the element Disengagement zone and form the technology of using groove; In above-mentioned groove, imbed, make whole smooth technology imbedding insulator; On whole of substrate, form the technology of dielectric film between the grid that the floating grid control gate electrode insulation of memory cell transistor uses; Remove the technology that dielectric film, polysilicon film and the 1st gate insulating film expose element region between the grid in above-mentioned peripheral transistor district; Formation is corroded in the bight of above-mentioned element region end of exposing in the peripheral transistor district have round-shaped technology; The technology of the 2nd gate insulating film that the above-mentioned peripheral circuit transistor of formation is used in above-mentioned peripheral transistor district; In the said memory cells array area, form the stacked gate structure that has possessed above-mentioned polysilicon film as floating grid, in the peripheral transistor district, on above-mentioned the 2nd gate insulating film, form the technology of gate electrode; Partly mix the technology of impurity of the source/leakage of transistor formed at underlayer surface.
Figure 1A～1D is the profile of manufacture method that the semiconductor storage of the present invention the 1st embodiment is shown interimly.
Fig. 2 A～2C illustrates the profile that is connected the later technology of Fig. 1 D.
Fig. 3 A～3C illustrates the profile that is connected the later technology of Fig. 2 C.
Fig. 4 A～4C illustrates the profile that is connected the later technology of Fig. 3 C.
Fig. 5 illustrates the profile that is connected the later technology of Fig. 4 C.
Fig. 6 is the profile of manufacture method that is used to illustrate the semiconductor storage of the present invention the 2nd embodiment.
Fig. 7 A～7C is the profile of manufacture method that the semiconductor storage of the present invention the 3rd embodiment is shown interimly.
Fig. 8 A, 8B illustrate the profile that is connected the later technology of Fig. 7 C.
Fig. 9 A～9D is the profile of manufacture method that the semiconductor storage of the present invention the 4th embodiment is shown interimly.
Figure 10 A～10C illustrates the profile that is connected the later technology of Fig. 9 D.
Figure 11 A～11D is the profile of manufacture method that the semiconductor storage of the present invention the 5th embodiment is shown interimly.
Figure 12 A～12C illustrates the profile that is connected the later technology of Figure 11 D.
Figure 13 A～Figure 13 C illustrates the profile that is connected the later technology of Figure 12 C.
Figure 14 A～14D illustrates the profile that is connected the later technology of Figure 13 C.
Figure 15 A～15D is the profile of manufacture method that the semiconductor storage of the present invention the 6th embodiment is shown interimly.
Figure 16 A～16C illustrates the profile that is connected the later technology of Figure 15 D.
Figure 17 A～17D illustrates the profile that is connected the later technology of Figure 16 C.
Figure 18 A～18D is the profile of manufacture method that the semiconductor storage of the present invention the 7th embodiment is shown interimly.
Figure 19 A～19D illustrates the profile that is connected the later technology of Figure 18 D.
Figure 20 A, 20B illustrate respectively among Fig. 2 C with zero to represent that the device of shape one example of part and this part finishes the profile of later shape one example enlargedly.
Figure 21 A～21C is the profile of part manufacturing process that the NOR type flash-EEPROM of the present invention the 8th embodiment is shown.
Figure 22 A～22D illustrates the profile that is connected the later part technology of Figure 21 C.
Figure 23 illustrates among Figure 22 C the profile of representing shape one example of part with zero enlargedly.
Figure 24 A～24D is the profile that the manufacture method of semiconductor storage in the past is shown interimly.
Figure 25 is the profile that is used for illustrating the parasitic transistor that takes place in the past semiconductor device.
Figure 26 A～26C is the semiconductor storage that is used for illustrating in the past, forms the method for beak and the profile of problem points thereof.
Inventive embodiments
Below, with reference to the description of drawings embodiments of the invention.
The 1st embodiment
Figure 1A～1D to Fig. 5 illustrates the manufacture method of the semiconductor storage of the present invention the 1st embodiment interimly, is the profile of peripheral circuit part.
At first, on whole of silicon substrate 301, form for example tunnel oxide film 302 of the memory cell of 10nm.Then, form the 1st polysilicon layer 303 (Figure 1A) of underclad portion of the formation floating grid of 70nm at an upper portion thereof.And then, the common in the above for example silicon nitride film 304 of deposit 200nm.The resist figure that has formed the groove of STI formation part opening by photoetching process then is according to this resist figure machine silicon nitride film 304 (Figure 1B).
Then, this nitride film 304 as mask, according to sequentially vertical etching the 1st floating grid of RIE method with polysilicon film 303, tunnel oxide film 302, silicon substrate 301.The shallow slot 305 that digs out on silicon substrate 301 is the separatory groove (shallow-trench isolation: STI) of element.
Secondly,, suppress to make beak too not enter for the oxidation of the least possible amount of oxidation at the interface of the 1st polysilicon 303 that becomes floating grid with silicon substrate 301, for example, the thermal oxidation technology of 10nm.Thus, form heat oxide film 306 (Fig. 1 C).
Secondly, with CVD method unfertile land deposition oxidation film 307 very in the above.And then the oxide-resistant film of deposit 6nm for example in the above, be silicon nitride film 408 (Fig. 1 D) specifically.
Secondly, the resist figure 309 (Fig. 2 B) that only on substrate, has formed at peripheral circuit part opening by photoetching process.With this resist figure 309 is the oxide-resistant film 308 (Fig. 2 B) that mask is removed the peripheral circuit part.For example if silicon nitride film then can use CDE methods such as (chemical drying method corrosion) to remove.The CVD oxide-film 307 that forms below oxide-resistant film in addition also plays the effect that alleviates the damage that enters into silicon substrate later under the situation of dielectric film is imbedded in the inner deposit of STI.
Secondly, be used to oxidation (Fig. 2 C) that beak is entered in the end of the element region (silicon substrate 301) of peripheral circuit part and each opposite face of the 1st polysilicon film 303.The beak 310 that forms by this oxidation can reduce falling into of gate electrode later when peripheral circuit forms.Thereby this oxidation is with fully, and the condition that for example forms the oxide-film of 30nm on silicon substrate is carried out.
At this moment, memory cell partly covers not oxidized with oxide-resistant film 308.Thereby, do not form beak on the opposite face end of the element region (silicon substrate 301) of memory cell part and each of the 1st polysilicon layer 303.Thereby, compare with the curvature of memory cell element region partly, can substantially strengthen the curvature of the element region of peripheral circuit part.In addition, also can remove oxide-resistant film afterwards as required.If near memory cell, there is silicon nitride film, then, therefore also can removes if desired, and the situation that does not have removal is shown in this example owing to exist the possibility that tunnel oxide film sustains damage here from the hydrogen that spreads.In addition, when removing silicon nitride film, after the technology of Fig. 1 D, can be with corroding by hot phosphoric acid or CDE (chemical drying method corrosion) removal.
Then, for landfill is carried out in STI inside, deposit plasma oxide film 311 (Fig. 3 A) for example.Under the high situation of depth-width ratio, use high-density plasma (HDP) CVD method to carry out deposit.For example, make this plasma oxide-film 311 smooth (Fig. 3 B) by CMP (chemico-mechanical polishing) method.
Secondly, remove the 1st floating grid with the silicon nitride film 304 on the polysilicon film 303 by wet etching.As the case may be, in order to be adjusted in the height of the dielectric film of imbedding in the STI 311, before removing nitride film, how many dielectric films 311 is corroded sometimes.Then, form the 2nd floating grid polysilicon layer 312 in the above.And then, on sti region, carry out floating grid and separate etching technics and the corrosion of using zone 313.Thus, the floating grid 312 (Fig. 3 C) that generates separated in each unit.
Then, on floating grid, become the laminated insulation film 314 (Fig. 4 A) of for example oxide-film/nitride film/oxide-film (ONO) of floating grid and control gate interelectrode insulating film.Later figure only illustrates the peripheral circuit part.
Then, cover memory cell areas by photoetching process with resist, with the ONO film 314 of dry etching removal periphery circuit region, the 1st, the 2nd polysilicon film 303,312 of floating grid is removed tunnel oxide film 312 (Fig. 4 B) with wet etching.By forming the grid beak fully, upper end, protection component district when this wet etching can prevent that oxide-film from dropping in the top.
Then, forming thickness of oxidation film at the substrate surface of peripheral circuit for example is the grid oxidation film 315 (Fig. 4 C) of 15nm, forms polysilicon layer 316 (Fig. 5) then at an upper portion thereof.Process this polysilicon layer 316, constitute the gate electrode of peripheral circuit part and the control gate electrode of memory cell part.
In addition, though do not illustrate, carry out the grid processing of peripheral transistor, memory cell transistor, as common carrying out, partly form diffusion layer in memory cell part and peripheral circuit, and then carry out Wiring technique then.Thus, finish memory cell array.
By adopting above such technology, be implemented in the memory cell part and do not invade beak, only invade the semiconductor storage of beak significantly in the peripheral circuit part.That is compare with the curvature of the element region of the memory cell part curvature of the element region that can strengthen the peripheral circuit part substantially.
The 2nd embodiment
In the 1st embodiment, covered the whole surface of memory cell areas with silicon nitride film, yet, will produce the deterioration of the tunnel oxide film 302 of memory cell sometimes if covering whole surface with silicon nitride film heat-treats.For this phenomenon being suppressed to be Min., also can form oxide-resistant film on the sidewall shape ground, side of the floating grid of memory cell.The 2nd embodiment provides such method.
At first, implement the technology of Figure 1A～1D among the 1st embodiment.In Fig. 1 D deposit after the oxide-resistant film 308, on whole, carry out returning corrosion by what RIE implemented, only stay oxide-resistant film at sidewall.Thus, can obtain structure shown in Figure 6.Then, by implementing later identical technology, finish the structure that oxide-resistant film only remains in floating grid sidewall and STI inwall with Fig. 2 of the 1st embodiment.
The 3rd embodiment
Fig. 7 and Fig. 8 are the profiles of manufacture method that the semiconductor storage of the present invention the 3rd embodiment is shown interimly.
At first, on whole of silicon substrate 501, form for example tunnel oxide film 502 of the memory cell of 10nm.Secondly, form the 1st polysilicon layer 503 (Fig. 7 A) of the formation floating grid part of 70nm at an upper portion thereof.And then, by follow-up photoetching process, the resist figure (not shown) that has partly formed the part opening of the groove that forms STI at peripheral circuit only, machine silicon nitride film 504.Secondly, this nitride film 504 as mask, according to the RIE method sequentially vertical etches the 1st floating grid form STI 505 with polysilicon layer 503, tunnel oxide film 502, silicon substrate 501.
Then, carry out to form the oxidation (Fig. 7 C) of for example 30nm of sufficient beak oxide film 506 at the polysilicon layer 503 of peripheral circuit part and the interface of silicon substrate 501.At this moment, memory cell partly goes up with silicon nitride film 504 coverings thereby not oxidized.
Then, form the STI groove 507 (Fig. 8 A) of memory cell part.Then, carry out MIN necessary oxidation on memory cell, for example oxidation of 6～10nm forms oxide-film 508 (Fig. 8 B).Then, carry out the imbed dielectric film to STI inside corresponding and form technology with Fig. 3 of the 1st embodiment.
Even according to above-mentioned technology, also can be implemented in the memory cell part and not invade beak, only in the peripheral circuit part, invade the semiconductor storage of beak significantly.That is compare with the curvature of the element region of the memory cell part curvature of the element region that can strengthen the peripheral circuit part substantially.
The 4th embodiment
Fig. 9 A～Fig. 9 D, Figure 10 A～10C are the profiles of manufacture method that the semiconductor storage of the present invention the 4th embodiment is shown interimly.
At first, form for example oxide-film about 20nm 608 (Fig. 9 A) of the 1st thick oxide film at silicon substrate 601.Then, the oxide-resistant film of deposit 8nm silicon nitride film 603 (Fig. 9 B) for example at an upper portion thereof.
Then,, remove the silicon nitride film 603 (Fig. 9 C) of memory cell part by etching technics residual resist 604 in the peripheral circuit part, and then, the silicon oxide layer of the 20nm of erosion removal memory cell part after having removed resist.
Then, in the memory cell part, for example form tunnel oxide film 605 with thickness 9nm.In peripheral circuit part owing to exist oxide-resistant film (silicon nitride film) 603 that therefore any variation does not take place.Then, between tunnel oxide film 605 and silicon substrate 601, import nitrogen (Fig. 9 D) by nitrogen treatment.When this nitrogenize prevents that beak is invaded in afterwards the technology, general because tunnel oxide film becomes nitrogen oxide, therefore will improve the reliability of memory cell.In addition, at this moment owing to cover the peripheral circuit part with nitride film 603, therefore the interface of the 1st oxide-film 602 and silicon substrate 601 is not by nitrogenize.Nitrogen treatment generally can pass through at ammonia or N 2Implementing heat treatment in the such gas of O, NO carries out.
Secondly, form the 1st polysilicon layer 606 (Figure 10 A) of underclad portion of the formation floating grid of 70nm at an upper portion thereof.And then common in the above deposit is the silicon nitride film 607 of 200nm for example.Then, by etching technics, the resist figure that has formed the part opening of the groove that forms STI is processed this silicon nitride film 607.
Then, with this silicon nitride film 607 is mask, use the RIE method in the peripheral circuit part sequentially vertical etches the 1st floating grid with the 1st oxide-film 602 and the silicon substrate 601 of polysilicon layer 606, silicon nitride film 603, substrate, in the memory cell part sequentially vertical etches the 1st floating grid with polysilicon layer 606, tunnel oxide film 605, silicon substrate 601.The shallow slot that digs out on silicon substrate is that element separates with groove (STI) (Figure 10 D).
Then, be used for the oxidation (Figure 10 C) that beak entered in the end, interface of the element region of peripheral circuit part and silicon nitride film 603.Form oxide-film 609,610 by this oxidation, the beak 610 of the peripheral circuit part that forms thus later can reduce falling into of gate electrode when peripheral circuit forms.Thereby, though carried out the oxidation of abundant amount, at this moment the tunnel oxide film of memory cell part is by nitrogen treatment, and so beak is difficult to invade.
On the other hand, in the peripheral circuit part, owing to exist on element region not by the thick si oxide film 602 of nitrogenize, therefore partly comparing with memory cell at the interface of silicon substrate 601 and silicon oxide layer 602 to add thick beak 610.In addition, the silicon nitride film 603 and 606 on the thick oxide film 602 of peripheral circuit part and top thereof, 607 was all removed (technology that is equivalent to Fig. 4 B of the 1st embodiment) before the grid oxidation film that forms the peripheral circuit part.
Even according to above-mentioned technology, also can be implemented in the memory cell part and not invade beak, only invade the semiconductor storage of beak significantly in the peripheral circuit part.That is compare with the curvature of the element region of the memory cell part curvature of the element region that can strengthen the peripheral circuit part substantially.
The 5th embodiment
Figure 11 A～11D to Figure 14 A～14C is the profile of manufacture method that the semiconductor storage of the present invention the 5th embodiment is shown interimly.
At first, on whole of silicon substrate 701, form for example tunnel oxide film 702 of the memory cell of 10nm.Then form the 1st polysilicon layer 703 (Figure 11 A) of the underclad portion that becomes floating grid of 70nm on top.
And then the common deposit silicon nitride film 704 of 200nm for example in the above.Then by photoetching process, the figure that has formed the part opening of the groove that forms STI.This silicon nitride film is processed.Then, be mask with this nitride film, sequentially process the 1st floating grid polysilicon layer, tunnel oxide film, silicon substrate according to the RIE method.The shallow slot that digs out on silicon substrate is that element separates with groove (STI) (Figure 11 B).
Then, suppressing oxidation for the least possible amount of oxidation makes too do not enter beak on the interface of the 1st polysilicon that becomes floating grid and silicon substrate.For example, carry out the thermal oxidation technology of 10nm.Thus, form heat oxide film 706 (Figure 11 C).
Then, use CVD method deposition oxidation film 707 in the above.And then form silicon fiml in the above.Specifically, for example use the amorphous silicon film 708 (Figure 11 D) of decompression CVD (LPCVD) method deposit 10nm.
Then, the resist figure 709 (Figure 12 A) that has only formed the peripheral part opening by photoetching process.With this anticorrosive additive material is mask, removes the silicon fiml 708 (Figure 12) of peripheral circuit part.For example, if amorphous silicon film then can enough CDE etc. method remove.In addition, be formed on the CVD oxide-film 707 below the silicon fiml, when dielectric film is imbedded in the inner deposit of STI, play the effect that reduces the damage that enters into silicon substrate later on.
Then, be used for entering the oxidation (Figure 12 C) of beak at the STI edge of peripheral circuit.The beak 710 that forms by this oxidation can reduce falling into of gate electrode later when peripheral circuit forms.Thereby, the thermal oxidation of fully measuring.For example, the condition with the oxide-film that forms 30nm is carried out on silicon substrate.
On the other hand, memory cell partly covers with amorphous silicon film 708, and by complete oxidation, amorphous silicon film 708 becomes silicon oxide layer 711 when the beak oxidation of peripheral circuit element region upper end partly, and thickness also becomes about 2 times 20nm.
After amorphous silicon film 708 became silicon oxide layer 711 fully in memory cell part, oxidant was along silicon oxide layer 711 diffusions, also carried out oxidation silicon substrate 701 and as the 1st polysilicon film 703 of the underclad portion of floating grid.
And owing to oxidant spreads along silicon nitride film 711, and then along silicon oxide layer 706 diffusions that form by the CVD method, arrive silicon substrate 701 or polysilicon film 703, therefore suppress silicon substrate 701 significantly and as the oxygenation efficiency of the 1st polysilicon film 703 of the underclad portion of floating grid.Thereby beak enters into the element region upper end of memory cell part hardly in this technology.
Be used for making that amount of oxidation that beak enters need to become the amount of oxidation of silicon oxide layer 711 fully identical with the silicon fiml 708 that is used for the deposit of memory cell part in the element region upper end of peripheral circuit part, and need enter beak hardly in the element region upper end in memory cell part, consider these requirements, set the deposit thickness of silicon oxide layer 708.
Secondly, for landfill STI inside, deposit plasma oxide film 712 (Figure 13 A) for example.Under the high situation of depth-width ratio, also use high-density plasma (HDP) CVD to carry out deposit sometimes.Then, for example make plasma oxide film smooth (Figure 13 B) by the CMP method.
Then, remove the 1st floating grid with the silicon nitride film 704 on the polysilicon film 703 by wet etching.As the case may be, in order to regulate the height of the dielectric film 712 that is embedded to STI inside, before removing nitride film 704, how many dielectric films 712 is corroded sometimes.
Then, on whole of substrate, form the 2nd floating grid with polysilicon layer 713.And then, on sti region, carry out the etching technics and the corrosion of floating grid Disengagement zone 714, be used for separating the processing (Figure 13 C) of floating grid in each unit.
Then, on floating grid 713, become the dielectric film of floating grid and control gate interpolar, for example the laminated insulation film 715 of oxide-film/nitride film/oxide-film (ONO) (Figure 14 A).The peripheral circuit part only is shown later on.
Then, cover the memory cell part with the resist figure, remove the 1st, the 2nd polysilicon film 703,713 that peripheral circuit ONO film 715, floating grid partly used, remove tunnel oxide film (Figure 14 B) with wet etching with dried wet corrosion by photoetching process.When this wet etching, by abundant formation grid beak, upper end, protection component district can prevent that oxide-film from dropping in the upper end.
Then, in the peripheral circuit part, form the grid oxidation film 716 (Figure 14 C) of for example 15nm of necessary oxide thickness, then form polysilicon layer 717 (Figure 14 D) at an upper portion thereof.This polysilicon layer 717 becomes the gate electrode of peripheral circuit part and the control grid of memory cell.
Secondly, though omitted diagram, yet carried out the grid processing of peripheral transistor, memory cell transistor, as common carrying out, partly formed diffusion layer then at memory cell part, peripheral circuit, and then, finish memory cell array by carrying out Wiring technique.
Even by above-mentioned technology, also can be implemented in the memory cell part and not invade beak, only in the peripheral circuit part, invade the semiconductor storage of beak significantly.That is compare with the curvature of the element region of the memory cell part curvature of the element region that can strengthen the peripheral circuit part substantially.
The 6th embodiment
Figure 15 A～15D to Figure 17 A～17D is the profile of manufacture method that the semiconductor storage of the present invention the 6th embodiment is shown interimly.Present embodiment and the 1st～the 5th embodiment is different, be not to form very big beak in the element region upper end of peripheral circuit part, but by cover the STI sidewall of peripheral circuit part with nitrogen oxidation film, carry out STI and imbed returning when corroding of dielectric film, expose the side that prevents element region, suppresses gate electrode the falling into to the element region side of peripheral circuit part.
Below, with reference to the description of drawings manufacturing process, Figure 15～Figure 17 A is applicable to memory cell part and peripheral circuit part two sides, Figure 17 B～D is applicable to the peripheral circuit part.
At first, on whole of silicon substrate 801, form for example silicon oxide layer 802 of the tunnel oxide film that becomes memory cell of 10nm.Then, form the 1st polysilicon layer 803 (Figure 15 A) of the underclad portion that becomes floating grid of 70nm at an upper portion thereof.
And then in the above, the common for example silicon nitride film 804 of deposit 200nm.Then by photoetching process, the resist figure that has formed the part opening of the groove that forms STI is processed this silicon nitride film.Then, be mask with this nitride film, sequentially process the 1st floating grid polysilicon film, tunnel oxide film, silicon substrate by the RIE method.The shallow slot that digs out on this silicon substrate is that element separates with groove (STI) (Figure 15 B).
Then, suppress the oxidation for the least possible amount of oxidation, for example the thermal oxidation technology of 10nm makes not enter beak on the 1st polysilicon that becomes floating grid and silicon substrate interface.Thus, form heat oxide film 806 (Figure 15 C).
Then, the silicon oxide layer 807 of 20nm for example of deposit in the above.Then, carry out silicon oxide layer 806 and 807 is changed into the processing (Fig. 9 D) of hot nitride film.Specifically, at 900 ℃ NH 3Atmosphere in carry out handling in 60 minutes, and then at 900 ℃ O 2Atmosphere in carry out handling in 60 minutes.Handle by this, the boundary zone of silicon oxide layer 806 and silicon and the surface region of silicon oxide layer 807 become the nitrogen oxidation film of the nitrogen that comprises several percentages.
Then, for landfill STI inside, deposit plasma oxide film 812 (Figure 16 A) for example.Under the high situation of depth-width ratio, also use high-density plasma (HDP) CVD to carry out deposit sometimes.Then, for example make this plasma oxide-film smooth (Figure 16 B) by the CMP method.
Then, remove the 1st floating grid with the silicon nitride film 804 on the polysilicon film 803 by wet etching.As the case may be, in order to be adjusted in the height of the dielectric film of imbedding in the STI 812, before removing nitride film 804, how many dielectric films 812 is corroded sometimes.Then, on whole of substrate, form the 2nd floating grid with polysilicon layer 813.And then, carry out the etching technics and the corrosion of floating grid Disengagement zone 814 in the STI district, be used for separating the processing (Figure 16 C) of floating grid in each unit.
Then, on floating grid 813, become the laminated insulation film 815 (Figure 17 A) of for example oxide-film/nitride film/oxide-film (ONO) of floating grid and control gate interelectrode insulating film.The part that becomes peripheral circuit only is shown later.
Then, cover the memory cell part with resist (not shown), remove peripheral circuit ONO film partly with dry etching, the 1st, the 2nd polysilicon layer 803,813 is removed tunnel oxide film 802 (Figure 17 B) with wet etching.When this wet etching, because using by the oxidized nitrogen oxidation film 806,807 of nitrogen, the side of the sidewall silicon of STI and the 1st floating grid electrode 202 covers, this part the corrosion rate of therefore comparing with the corrosion rate of tunnel oxide film 802 is slow.Therefore, do not expose the element region upper side.
Then, partly form the grid oxidation film 816 (Figure 17 C) of for example 15nm of necessary thickness of oxidation film, then form polysilicon layer 817 (Figure 17 D) on top at peripheral circuit.This polysilicon layer becomes the gate electrode of peripheral circuit part and the control grid of memory cell.
In the present embodiment, in STI, form silicon oxide layer 806 by oxidation processes after, deposit silicon oxide-film 807, and silicon oxide layer 806 and 807 might not need to make 2 layers also can be by deposited film or based on the monolayer silicon oxide-film of oxidation processes.
Secondly, though omitted diagram, yet carried out the grid processing of peripheral transistor, memory cell transistor, as common carrying out, in memory cell, peripheral circuit part, formed diffusion layer then, and then, finish memory cell array by carrying out Wiring technique.
In the present embodiment, because the element region upper end side of the gate electrode of peripheral circuit part after forming cover with the nitrogen oxidation film that is formed on the STI inwall at least, therefore the bending effect of the peripheral transistor that the filming by oxide-film causes can not take place.
If according to invention disclosed among the 1st embodiment to the 5 embodiment, then owing between the active region of memory cell and silicon substrate, form beak only bigly, can form very big beak in the peripheral circuit part, the characteristic that therefore can reduce memory cell is disperseed.On the other hand, by forming beak, can prevent the bending effect of MOSFET, the increase of current sinking in the time that standby can being suppressed at peripheral circuit.
In addition, if according to the 6th embodiment invention disclosed, then because the STI inwall uses the silicon nitrogen oxidation film to cover, therefore the film of dielectric film that can upper end, suppression element district when peripheral circuit is partly peeled off tunnel oxide film reduces, can prevent the bending effect of MOSFET equally, the increase of current sinking in the time that standby can being suppressed.
The 7th embodiment
Figure 18 A～18D to Figure 19 A～19D is the profile of manufacture method that the semiconductor storage of the present invention the 7th embodiment is shown interimly.
The semiconductor storage of present embodiment (NOR type flash-EEPROM) have with imbed element Disengagement zone insulated separation element region, the memory cell array district is different with the thickness of the gate insulating film of the MOS transistor in peripheral transistor district.
At first, shown in Figure 18 A, in the memory cell array district of Semiconductor substrate 901 is that memory cell part and peripheral transistor district are after peripheral circuit partly makes each transistorized threshold value become desirable value respectively to have mixed impurity like that, becomes the gate insulating film 902 of the tunnel oxide film of memory cell transistor on whole of substrate.The stack membrane 904 of deposit polysilicon film 903, CVD nitride film and CVD oxide-film in the above then.
Then, on substrate, form resist figure (not shown), use this figure above-mentioned stack membrane 904 graphical the above-mentioned resist figure of later removal.
Then, shown in Figure 18 B, above-mentioned graphical stack membrane 904 as mask, is formed corresponding polysilicon film 903, grid oxidation film 902, the silicon substrate 901 of predetermined portions by removing with the element Disengagement zone, the formation shallow slot.
In addition, after the memory cell array district having been covered with resist (not shown), carry out wet etching for the peripheral transistor district and handle (perhaps isotropism dry etching processing, perhaps these two kinds of processing), shown in Figure 18 C, the part (part on the element region end) of the gate insulating film 902 on the element region in removal peripheral transistor district is made the shape that is easy to supply with to the end of element region oxidant.
Then, remove above-mentioned resist,, carry out oxidation in the atmosphere of oxygen concentration 10%, make the thickness of oxidation film of above-mentioned rooved face become the above oxide-film 913 that forms of 20nm at for example temperature 900 degree～1000 degree.At this moment, element region end and the supply of the part between the polysilicon film above it 903 oxidant in the peripheral transistor district carries out oxidation.Therefore, like that, the end of element region became the shape with circle when so-called beak entered than heavy back shown in Figure 18 D.That is, strengthen the curvature of the element region distribution in peripheral transistor district.
Then, shown in Figure 19 A, in above-mentioned groove, imbed as for example LP-TEOS film 905 of imbedding insulator.Then, use the CMP method or return etch make whole smooth, make and imbed the middle part that insulator moves back to dielectric film 904, then return corrosion treatment, removal stack membrane 904.
Secondly, shown in Figure 19 B, the polysilicon film 906 of phosphorus has been mixed in deposit as impurity on whole of substrate, form resist figure (not shown) in the above, by using this figure that above-mentioned polysilicon film 906 is carried out graphically, be formed on the slit 907 of the polysilicon film 906 in disjunction memory cell array district on the element Disengagement zone, remove the polysilicon film 906,903 in peripheral transistor district.Then, peel off above-mentioned resist figure.
Secondly, on whole of substrate, form ONO dielectric film 908, on the basis that the memory cell array district is covered with resist (not shown), removed after the ONO dielectric film 908 and gate insulating film (tunnel insulator film) 902 in peripheral transistor district, removed the resist that covers the said memory cells array area.
In addition, stay the polysilicon film 906,903 in peripheral transistor district in the time of also can forming slit 907 in advance, removed above-mentioned polysilicon film 906,903 at 902 o'clock at above-mentioned ONO dielectric film 908 of removal and gate insulating film (tunnel insulator film) in the memory cell array district.
Below, with identical in the past, shown in Figure 19 C, form peripheral circuit with transistorized gate insulating film 909, and then such as Figure 19 D shown in watch with the orthogonal direction of Figure 19 C, the polysilicon film of impurity has been mixed in deposit on whole on the substrate.
And, in the memory cell array district by graphical above-mentioned polysilicon film, above-mentioned ONO dielectric film 908, polysilicon film 906 and 903, form control grid 910 and floating grid 911 (polysilicon film 906 and 903) and be 2 layers stacked gate structure, in the peripheral transistor district by above-mentioned polysilicon film is graphically formed gate electrode 912.Then, though do not illustrate, optionally mix the impurity that becomes transistorized source/leakage in the underlayer surface part, and then, carry out the deposit of interlayer dielectric, the contact perforate, wiring forms, and flash-EEPROM is finished in the deposit of surface protection dielectric film.
Figure 20 A illustrate enlargedly with Figure 19 C in the corresponding end of part shown in zero symbol of with dashed lines (promptly, the end of the element region in forming the peripheral transistor district that element separating insulation film forms gate insulating film later on) shape one example, shape one example after the device that this part is shown among Figure 20 B is enlargedly finished.Here, the 901st, Semiconductor substrate, the 905th, element separating insulation film, the 909th, gate insulating film, the 912nd, gate electrode.
As from shown in Figure 20 A, the 20B like that, gate insulating film 909 on the element region end is owing to be the shape that beak enters, the film of element region end minimizing in the stripping technology when therefore being suppressed at the division process of making grid is difficult to cause that the electric field of element region end is concentrated.
In addition, the form that falls into of the gate insulating film 12 that forms on the gate insulating film 909 of the element region end in the peripheral transistor district shown in Figure 20 A, the 20B becomes the few shape of the amount of falling into.Point out in passing, the result of actual measurement, the height of the flat in said elements district is more than the 4nm with the difference in height d of the lowermost portion of the gate electrode that is positioned at its top.
The 8th embodiment
Figure 21 A～21C to Figure 22 A～22D is the profile of manufacture method that the semiconductor storage of the present invention the 8th embodiment is shown interimly.
At first shown in Figure 21 A, after having mixed impurity and make that each transistorized threshold value becomes desirable threshold value respectively in the memory cell array district of Semiconductor substrate 1001 and peripheral transistor district, on whole of substrate, become the oxide-film 1002 of the tunnel oxide film of memory cell transistor, deposit has in the above been mixed the polysilicon film 1003 of phosphorus, the stack membrane 1004 of CVD (chemical vapor-phase growing) nitride film and CVD oxide-film as impurity.
Secondly, on substrate, form resist figure (not shown), use this figure, above-mentioned stack membrane 1004 graphical the above-mentioned resist figure of later removal.
Then, shown in Figure 21 B, above-mentioned graphical stack membrane 1004 as mask, by removing polysilicon film 1003, gate insulating film 1002, the silicon substrate 1001 that forms predetermined portions corresponding to the element Disengagement zone, is formed shallow slot.
Secondly, shown in Figure 21 C, in above-mentioned groove, imbed as for example LP-TEOS (the low pressure tetraethyl oxide silicon) film 1005 of imbedding insulator.Then, by CMP (chemico-mechanical polishing) method or return etch make whole smooth, make and imbed the middle part that insulator moves back to stack membrane 1004.Then, carry out wet etching and handle, remove stack membrane 1004 fully.
Then, shown in Figure 22 A, deposit has been mixed the polysilicon film 1006 of phosphorus as impurity on whole of substrate, forms resist figure (not shown) in the above, uses this figure graphical above-mentioned polysilicon film 1006.At this moment, be formed on the element Disengagement zone, remove the polysilicon film 1006,1003 in peripheral transistor district the slit 1007 of polysilicon film 1006 disjunctions in memory cell array district.Then, peel off above-mentioned resist figure.
Then, on whole of substrate, form ONO dielectric film (stack membrane of oxide-film/nitride film/oxide-film) 1008, covering with resist (not shown) on the basis in memory cell array district, remove after the ONO dielectric film 1008 and grid oxidation film (tunnel oxide film) 1002 in peripheral transistor district, remove the resist that covers the said memory cells array area.
In addition, stay the polysilicon film 1006,1003 in peripheral transistor district in the time of also can in the memory cell array district, forming slit 1007 in advance, removed above-mentioned polysilicon film 1006,1003 at 1002 o'clock at above-mentioned ONO dielectric film 1008 of removal and grid oxidation film (tunnel oxide film).In this stage, the bight of the element region end in peripheral transistor district becomes the state that exposes.
Secondly, under the state that has covered the memory cell array district with resist, shown in Figure 22 B, handle (perhaps isotropic dry etching processing by carrying out wet etching, perhaps these two kinds of processing), the bight of the element region end of exposing is corroded to become have circular shape.
Then, after the resist of having removed covering memory cell array district, shown in Figure 22 C, with identical in the past, form peripheral circuit with transistorized grid oxidation film 1009, and then such as Figure 22 D shown in watch with the orthogonal direction of Figure 22 C, the polysilicon film of impurity has been mixed in deposit on whole of substrate.And, graphical in the memory cell array district above-mentioned polysilicon film, above-mentioned ONO dielectric film 1008, polysilicon film 1006 and 1003, form control grid 1010 and become 2 layers stacked gate structure with floating grid 1011 (polysilicon film 1006 and 1003), in above-mentioned peripheral transistor district by above-mentioned polysilicon film is graphically formed gate electrode 1012.Then, though do not illustrate, on the underlayer surface part, optionally mix the impurity that becomes transistorized source/leakage; and then, carry out the deposit of interlayer dielectric, the perforate of contact; wiring forms, and flash-EEPROM is finished in the deposit of surface protection dielectric film.
Figure 23 illustrates shape one example of the end corresponding with the part of zero symbolic representation of with dashed lines among Figure 22 C (that is, having formed the end of the element region in the peripheral transistor district that element separating insulation film forms grid oxidation film later on) enlargedly.Here, the 1001st, Semiconductor substrate, the 1005th, element separates uses dielectric film, and the 1009th, grid oxidation film.
Known to from Figure 23, because becoming, the end of element region has circular shape, therefore suppressed to become the electric field of the element region end of problem in the past and concentrated.
If narrate manufacture method in the past briefly with the 7th embodiment and the 8th embodiment associated, then in manufacture method in the past, in ONO film before the grid oxidation film that forms the peripheral transistor district, the removal technology of tunnel oxide film, expose the bight in the element region end.
So, in manufacture method in the past, because causing electric field when the action of peripheral circuit transistor in the bight of element region end concentrates, increase the leakage current of peripheral circuit transistor, increase the current sinking of device, the subthreshold value characteristic of peripheral transistor becomes discontinuous for grid voltage, therefore become peripheral circuit misoperation, the reason of the decrease in yield of product.
Different therewith, in the manufacture method of the 7th embodiment and the 8th embodiment, (1). for the element region end in peripheral transistor district, handle by carrying out wet etching, the isotropism dry etching is handled, oxidation processes or its Combined Processing, the curvature of increasing element region end, in addition, (2). the element in the peripheral transistor district separates in the formation technology at element region end introducing beak.
Thus, can fall into the element region end by the suppressor grid electrode, make gate electrode not produce electric field in the element region end and concentrate, the leakage current that suppresses peripheral circuit transistor, improve the subthreshold current characteristic of peripheral circuit transistor, therefore can reduce the power consumption of product, improve rate of finished products.
In addition, as the method for the bight rounding that makes the element region end of exposing, if general known when oxidation by the supply decision reaction speed of oxygen, then compare with flat portions and be easy to oxidation in the angle part.
Therefore, replace the processing in the various embodiments described above, before the grid of peripheral circuit transistor forms, also be added in high temperature and suppressed the condition of oxygen supply, for example 1000 ℃, nitrogen 90%, carry out the technology of oxidation under the condition of oxygen 10%, can justify processing to the bight of the element region end of exposing, be adopted as by the method for oxidation of supplying with the decision reaction speed, also can access same effect even the grid oxidation film of peripheral circuit transistor is formed technology self.In addition, also can access same effect by these methods being made up certainly.
When the separating of the grid oxidation film that carries out memory cell array district and peripheral transistor district, in the peripheral transistor district, justifying processing, cross over aspect the bending effect of the peripheral circuit transistor that the element Disengagement zone forms very effective from element region at the suppressor grid electrode by imbedding the bight that the element Disengagement zone is insulated the element region end of having separated.
In addition, the 7th embodiment and the disclosed manufacturing method for semiconductor device of the 8th embodiment can be applicable to a part that formed gate insulating film before element separate to form technology, separate the manufacturing of the semiconductor device of the remainder that forms gate insulating film after forming technology at element.
By the end shape of element region being justified leakage current and the current sinking that processing can suppress the low zone of transistorized grid voltage, the subthreshold current characteristic becomes continuously for grid voltage, transistorized action in the low zone of grid voltage is stable, and the rate of finished products of product is improved.
Thereby, for example the 7th embodiment and the 8th embodiment are applicable to flash-EEPROM and manufacturing thereof, then big than the curvature of the element region end in memory cell array district by the curvature of the element region end in the peripheral transistor district is set at, can reduce the leakage current of peripheral circuit transistor, reduce power consumption.
Though according to above embodiment the present invention has been described, the present invention for example peripheral circuit can also be the control circuit that only comprises memory cell part, and CPU etc.In above embodiment, be that example is illustrated with the flash-EEPROM, yet the present invention be not limited thereto, in the scope that does not break away from the aim of the present invention that is not subjected to these restrictions, can adopt various distortion.

Claims (17)

1. Nonvolatile semiconductor memory device is characterised in that:
Have
Semiconductor substrate;
Form the memory cell part on the above-mentioned Semiconductor substrate of a plurality of memory cell;
Peripheral circuit part on the above-mentioned Semiconductor substrate of the circuit of formation control said memory cells;
The a plurality of element regions that separated by a plurality of grooves of formation respectively on said memory cells part and the peripheral circuit part;
The nitrogen oxidation film that forms at the inwall of above-mentioned groove;
The dielectric film of the above-mentioned groove of landfill;
On the element region of above-mentioned peripheral circuit part, by stipulated the film formed gate electrode of gate insulator of end with above-mentioned nitrogen oxidation film.
2. Nonvolatile semiconductor memory device is characterised in that:
Have
Form a plurality of memory cell transistors, by imbedding the element Disengagement zone the memory cell array district of the transistorized element region insulated separation of said memory cells;
Form the peripheral circuit transistor of a plurality of memory cell arrays, by imbedding the element Disengagement zone the peripheral circuit transistor district of the element region insulated separation of above-mentioned peripheral circuit transistor,
Compare with the curvature of the transistorized element region of the said memory cells end curvature of element region end of the above-mentioned peripheral circuit transistor of bigger substantially setting.
3. as the Nonvolatile semiconductor memory device of record in the claim 2, be characterised in that:
The height of the flat in said elements district is more than the 4nm with the difference of the height of the lowermost portion of the gate electrode that is positioned at its top.
4. as the non-volatile semiconductor devices of record in the claim 2, be characterised in that:
When the action of above-mentioned peripheral circuit transistor is holding state, provide the bias potential that flows through subthreshold current.
5. as the non-volatile semiconductor devices of record in the claim 2, be characterised in that:
Mate certainly the element Disengagement zone of imbedding of at least a portion of the transistorized gate electrode of said memory cells and said memory cells array area.
6. as the non-volatile semiconductor devices of record in the claim 2, be characterised in that:
The said memory cells transistor is the memory cell that has possessed the nonvolatile semiconductor memory of floating grid.
7. the manufacture method of a Nonvolatile semiconductor memory device, this is to have with groove-shape element to separate the formation element region, and comprise the memory cell part of floating grid and the manufacture method of its peripheral circuit Nonvolatile semiconductor memory device partly, be characterised in that:
Have
On silicon substrate, form the technology of polysilicon layer via dielectric film;
In order to form element region, corrode to coupling this polysilicon layer and dielectric film, silicon substrate certainly, be formed on the technology of the separatory a plurality of grooves of element that have bottom and embracing element district in the silicon substrate;
The technology of processing being justified in each end of the element region face relative with polysilicon layer by oxidation;
Cover the technology of memory cell part with film with oxidative resistance;
Add oxidation after the formation of above-mentioned oxide-resistant film, the element region in the peripheral circuit part between the end of the silicon substrate face relative with polysilicon layer, forms the technology of the beak shape oxide-film thicker than memory cell part.
8. as the manufacture method of the Nonvolatile semiconductor memory device of record in the claim 7, be characterised in that:
Also had in deposit after the above-mentioned oxide-resistant film, before the oxidation of carrying out for peripheral circuit part, optionally remove above-mentioned oxide-resistant film and only make in the memory cell part and to separate technology with the residual oxide-resistant film of inwall of groove at floating grid lateral parts and element.
9. as the manufacture method of the Nonvolatile semiconductor memory device of record in the claim 7, be characterised in that:
After the oxidation of having carried out for the peripheral circuit part, remove the oxide-resistant film that covers the memory cell part.
10. the manufacture method of a Nonvolatile semiconductor memory device, this is to have with groove-shape element to separate the formation element region, and comprise the memory cell part of floating grid and the manufacture method of its peripheral circuit Nonvolatile semiconductor memory device partly, be characterised in that:
Have
On silicon substrate, form the technology of polysilicon layer via dielectric film;
Only in the peripheral circuit part, coupling ground corrosion polysilicon layer and dielectric film, silicon substrate form the 1st element and separate the technology of using groove certainly;
In the peripheral circuit part, each end of the face that the oxidation element region is relative with the 1st polysilicon layer, the technology of formation beak shape oxide-film;
Polysilicon layer and dielectric film, silicon substrate from coupling ground corrosion memory cell part form the 2nd element and separate the technology of using groove;
After formation the 2nd element separated with groove, each end of the face that the element region of oxidation memory cell part is relative with polysilicon layer formed than the technology that is formed on the thinner beak shape oxide-film of peripheral circuit beak shape oxide-film partly.
11. the manufacture method of a Nonvolatile semiconductor memory device, this is to have with groove-shape element to separate the formation element region, and comprise the memory cell part of floating grid and the manufacture method of its peripheral circuit Nonvolatile semiconductor memory device partly, be characterised in that:
Have
On silicon substrate, form the technology of oxide-resistant film via dielectric film;
Optionally remove the oxide-resistant film of memory cell part and the technology of dielectric film;
On the memory cell part, form tunnel oxide film, this film is carried out nitrogen treatment, tunnel film is formed the technology of nitrogen oxidation film;
On the top of the tunnel nitrogen oxidation film of memory cell part and the top of the oxide-resistant film of peripheral circuit part, form the technology of polysilicon layer;
From mating ground corrosion polysilicon film and silicon substrate, separate the technology of using groove in memory cell part and peripheral circuit part forming element;
After the element separation forms with groove,, form beak shape oxide-film, partly form the technology of the beak shape oxide-film thicker at peripheral circuit than the memory cell part in the end of element region each face relative with polysilicon layer by oxidation.
12. the manufacture method of a Nonvolatile semiconductor memory device, this is to have with groove-shape element to separate the formation element region, and comprise the memory cell part of floating grid and the manufacture method of its peripheral circuit Nonvolatile semiconductor memory device partly, be characterised in that:
Have
On silicon substrate, form the technology of polysilicon layer via dielectric film;
From coupling ground this polysilicon layer of corrosion and silicon substrate,, form the technology of element separation with groove in order to form element region;
By oxidation, the technology that processing is justified in the end of element region each face relative with polysilicon;
The technology that only memory cell is partly covered with polysilicon film;
Covering at above-mentioned polysilicon film adds oxidation later on, between the end of the silicon substrate of peripheral circuit part and the opposite face of polysilicon layer, forms than the memory cell technology of thicker beak shape oxide-film partly;
The silicon fiml that covers the memory cell part is formed the technology of oxide-film.
13. the manufacture method of a Nonvolatile semiconductor memory device, this is to have with groove-shape element to separate the formation element region, and comprise the memory cell part of floating grid and the manufacture method of its peripheral circuit Nonvolatile semiconductor memory device partly, be characterised in that:
Have
On silicon substrate, form dielectric film and the technology that becomes the polysilicon layer of floating grid;
From coupling ground this polysilicon film of corrosion and silicon substrate, form the technology of element separation with groove;
Form the technology of silicon nitrogen oxidation film at the sidewall of the inwall of groove and polysilicon.
14. the manufacture method as the Nonvolatile semiconductor memory device of record in the claim 13 is characterised in that:
The technology that forms the silicon nitrogen oxidation film at the sidewall of the inwall of groove and polysilicon is to form silicon oxide layer with after-applied nitrogen oxidation processes at the inwall of groove and the sidewall of polysilicon layer, forms the technology of nitrogen oxidation film.
15. the manufacture method of a Nonvolatile semiconductor memory device, before separating formation technology, element forms the part of the gate insulating film of MOS transistor, when element separate to form technology and forms the manufacturing of Nonvolatile semiconductor memory device of remainder of above-mentioned gate insulating film later on, be characterised in that:
Forming MOS transistor makes and has the curvature of separating the element region end of the MOS transistor that forms the gate insulating film that forms before the technology at said elements and compare to strengthen substantially and have the curvature of separating the element region end of the MOS transistor that forms the gate insulating film that technology forms later at said elements.
16. the manufacture method of a Nonvolatile semiconductor memory device when having the memory cell array district and formed the manufacturing of Nonvolatile semiconductor memory device in peripheral transistor district of its peripheral circuit transistor, is characterised in that:
Have
On whole of Semiconductor substrate, form the 1st gate insulating film that memory cell transistor is used, form the technology of polysilicon film and dielectric film in the above;
On above-mentioned dielectric film, polysilicon film, the 1st gate insulating film and Semiconductor substrate, form the element Disengagement zone and form the technology of using groove;
On the basis that covers the said memory cells array area, the technology of the 1st gate insulating film on the element region end in removal peripheral transistor district;
The surface technology of carrying out oxidation of part between the end of the element region in the surface of above-mentioned groove and peripheral transistor district and the polysilicon film above it;
In above-mentioned groove, imbed, and make whole smooth technology imbedding insulator;
Remove the technology of the dielectric film on the above-mentioned polysilicon film;
After the polysilicon film of having removed above-mentioned peripheral transistor district and the 1st gate insulating film, the technology of the 2nd gate insulating film that the formation peripheral circuit transistor is used;
In the formation of said memory cells array area above-mentioned polysilicon film is constructed as the stacked gate that floating grid possessed, on above-mentioned the 2nd gate insulating film, form the technology of gate electrode in the peripheral transistor district;
The technology of optionally mixing the impurity that becomes transistorized source/leakage in underlayer surface part.
17. the manufacture method of a Nonvolatile semiconductor memory device when having the memory cell array district and formed the manufacturing of Nonvolatile semiconductor memory device in peripheral transistor district of its peripheral circuit transistor, is characterised in that:
Have
On whole of Semiconductor substrate, form the 1st gate insulating film that memory cell transistor is used, form the technology of polysilicon film in the above;
On above-mentioned polysilicon film, the 1st gate insulating film and Semiconductor substrate, form the element Disengagement zone and form the technology of using groove;
In above-mentioned groove, imbed, and make whole smooth technology imbedding insulator;
The technology of dielectric film between the grid that the floating grid control gate electrode insulation that formation memory cell transistor on whole of substrate is used is used;
Remove the technology that dielectric film, polysilicon film and the 1st gate insulating film expose element region between the grid in above-mentioned peripheral transistor district;
The bight of the element region end that above-mentioned peripheral transistor district is exposed is corroded to make and is had round-shaped technology;
Form the technology of the 2nd gate insulating film that above-mentioned peripheral circuit transistor uses in above-mentioned peripheral transistor district;
In the formation of said memory cells array area above-mentioned polysilicon film is constructed as the stacked gate that floating grid possessed, on above-mentioned the 2nd gate insulating film, form the technology of gate electrode in the peripheral transistor district;
The technology of optionally mixing the impurity that becomes transistorized source/leakage in underlayer surface part.
CN00104074A 1999-03-18 2000-03-17 Non-volatile memory of semi-conductor and its producing method Pending CN1267915A (en)

Applications Claiming Priority (4)

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JP07307499A JP3651760B2 (en) 1999-03-18 1999-03-18 Manufacturing method of semiconductor device
JP073074/1999 1999-03-18
JP185118/1999 1999-06-30
JP18511899A JP3833854B2 (en) 1999-06-30 1999-06-30 Method for manufacturing nonvolatile semiconductor memory device

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
CN100411144C (en) * 2005-08-16 2008-08-13 力晶半导体股份有限公司 Nonvolatile memory and manufacturing method
CN100536139C (en) * 2005-03-25 2009-09-02 冲电气工业株式会社 Semiconductor integrated circuit
CN101373776B (en) * 2004-12-24 2010-08-04 株式会社理光 Semiconductor device
WO2022095466A1 (en) * 2020-11-04 2022-05-12 长鑫存储技术有限公司 Semiconductor structure and manufacturing method for semiconductor structure

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JP4290548B2 (en) * 2001-08-06 2009-07-08 エヌエックスピー ビー ヴィ Manufacturing method of semiconductor device including nonvolatile memory including memory cell having access gate, control gate, and charge storage region
JP2004095886A (en) * 2002-08-30 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
KR100479834B1 (en) * 2002-09-03 2005-04-06 주식회사 엑셀반도체 Flash memory fabrication method
KR100881847B1 (en) * 2002-12-28 2009-02-03 동부일렉트로닉스 주식회사 Method For Manufacturing Semiconductor Memory Device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101373776B (en) * 2004-12-24 2010-08-04 株式会社理光 Semiconductor device
CN100536139C (en) * 2005-03-25 2009-09-02 冲电气工业株式会社 Semiconductor integrated circuit
CN100411144C (en) * 2005-08-16 2008-08-13 力晶半导体股份有限公司 Nonvolatile memory and manufacturing method
WO2022095466A1 (en) * 2020-11-04 2022-05-12 长鑫存储技术有限公司 Semiconductor structure and manufacturing method for semiconductor structure

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