CN100411144C - Nonvolatile memory and manufacturing method - Google Patents
Nonvolatile memory and manufacturing method Download PDFInfo
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- CN100411144C CN100411144C CNB2005100920442A CN200510092044A CN100411144C CN 100411144 C CN100411144 C CN 100411144C CN B2005100920442 A CNB2005100920442 A CN B2005100920442A CN 200510092044 A CN200510092044 A CN 200510092044A CN 100411144 C CN100411144 C CN 100411144C
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 90
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 238000000034 method Methods 0.000 claims abstract description 67
- 239000004020 conductor Substances 0.000 claims abstract description 60
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000003989 dielectric material Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 164
- 238000005516 engineering process Methods 0.000 description 10
- 230000001133 acceleration Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000012467 final product Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
The method includes steps: first, a semiconductor component is formed on the substrate, and the top part of the semiconductor component is higher than surface of substrate; next, forming first dielectric layer to cover semiconductor component and substrate; then, removing partial first dielectric layer, but retaining partial first dielectric layer located at sidewall of semiconductor component and partial substrate; afterwards, forming second dielectric layer and conductor layer above substrate in sequence, and forming corresponding mask gap wall on conductor layer on sidewall of semiconductor component; finally, using the mask gap wall as etching mask, the method removes partial conductor layer till surface of the second dielectric layer is exposed.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of non-volatility memorizer and manufacture method thereof.
Background technology
Memory is the semiconductor element in order to storage data or data as its name suggests.Wherein, because non-volatility memorizer has the advantage that the data that deposit in also can not disappear after outage, therefore must possess this type of memory in many electric equipment products, keeping the electric equipment products normal running in when start, and become extensively a kind of memory component of employing of personal computer and electronic equipment institute.
Along with science and technology development with rapid changepl. never-ending changes and improvements, when the function of computer microprocessor more and more stronger, when program that software carried out and computing are more and more huger, the demand of memory is also just more and more higher, particularly about raising to the demand that writes efficient of memory component, in order to make the trend that satisfies this demand, make the technology of memory component, become semiconductor science and technology and continued toward the actuating force of high integration challenge.
Figure 1A to Fig. 1 D is the manufacturing process generalized section according to the existing non-volatility memorizer that is illustrated.
Please refer to Figure 1A, in a substrate 100, form semiconductor element 101, and the top of semiconductor element 101 is higher than the surface of substrate 100.Then, please refer to Figure 1B, in substrate 100, form one deck dielectric materials layer 102, then on dielectric materials layer 102, form one deck conductor layer 104.Subsequently, please refer to Fig. 1 C, on the conductor layer 104 of semiconductor element 101 sidewalls, form clearance wall 106.Continuing it, please refer to Fig. 1 D, is etching mask with clearance wall 106, and etching part conductor layer 104 and part dielectric materials layer 102 are to exposing substrate 100 surfaces.After the step of Fig. 1 D, the conductor layer 104a that is remained on the dielectric layer bed of material 102 can be used as word line (word line).
Yet the manufacture method of above-mentioned non-volatility memorizer has some problems to exist.For instance, to write efficient not high for the data of memory component.In addition, in the etching step of dielectric materials layer 102, produce the phenomenon of rete depression because of etching excessively causes the dielectric layer in the semiconductor element 101 easily, and then influence the reliability of element.Similarly, in the etching step of dielectric materials layer 102, if etching excessively then can cause semiconductor element 101 and word line to produce the phenomenon of breakdown voltage, it can have a strong impact on element efficiency.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of non-volatility memorizer is being provided, can avoid the dielectric layer of non-volatility memorizer to produce the phenomenon that rete caves in, improve the film layer quality of dielectric layer, and can avoid element to produce the phenomenon of breakdown voltage simultaneously, and then improve the reliability of technology.
Another object of the present invention provides a kind of non-volatility memorizer, can improve the efficient that writes of element more, with lift elements usefulness.
The present invention proposes a kind of manufacture method of non-volatility memorizer, and the method is prior to forming semiconductor element in the substrate, and the top of semiconductor element is higher than the surface of substrate.Afterwards, form first dielectric layer in substrate, cover semiconductor component surfaces and substrate, the surface profile that wherein covers the part of first dielectric layer of substrate is stepped that past semiconductor element height increases progressively.Then, on first dielectric layer, form first conductor layer, on first conductor layer of the sidewall of semiconductor element, form the pairing a pair of first mask clearance wall, and then be etching mask with the first mask clearance wall, remove part first conductor layer up to the surface that exposes first dielectric layer, and first conductor layer between the first mask clearance wall and first dielectric layer then forms the pair of conductors clearance wall.
Described according to the preferred embodiments of the present invention, the formation method of the first above-mentioned dielectric layer for example is to form first dielectric materials layer in substrate, covers semiconductor component surfaces and substrate.Then, remove part first dielectric materials layer, be positioned at semiconductor component surfaces, and be positioned at this suprabasil part first dielectric materials layer of part to keep at least.Then, form second dielectric materials layer in the substrate top, and second dielectric materials layer covers first dielectric materials layer and substrate.
Described according to the preferred embodiments of the present invention, above-mentioned part first dielectric materials layer that removes, be positioned at semiconductor component surfaces to keep at least, and the method that is positioned at suprabasil part first dielectric materials layer of part for example is, on first dielectric materials layer of the sidewall of semiconductor element, form the corresponding a pair of second mask clearance wall, then, with the second mask clearance wall is etching mask, remove first dielectric materials layer that part exposes, then remove the mask clearance wall again, remove semiconductor element sidewall and suprabasil part first dielectric materials layer until exposing substrate surface.
Described according to the preferred embodiments of the present invention, above-mentioned remove the semiconductor element sidewall and suprabasil part first dielectric materials layer for example is a wet etching until the method that exposes substrate surface.
Described according to the preferred embodiments of the present invention, the thickness of above-mentioned suprabasil first dielectric materials layer of the part that is positioned at the semiconductor element sidewall that remains is 10～20 dusts.
Described according to the preferred embodiments of the present invention, the material of above-mentioned dielectric materials layer for example is a silica, and its formation method for example is a chemical vapour deposition technique.
Described according to the preferred embodiments of the present invention, first rank that the past semiconductor element of the first above-mentioned dielectric layer increases progressively are 1: 2 with the length surface ratio on second rank.
Described according to the preferred embodiments of the present invention, the material of the first above-mentioned mask clearance wall for example is a silicon nitride.Wherein, the formation method of the first mask clearance wall for example is, forms a layer of mask material on first conductor layer, and then carries out an etch process, removes the part layer of mask material.
Described according to the preferred embodiments of the present invention, above-mentioned semiconductor element for example is a plough groove type semiconductor element.The formation method of plough groove type semiconductor element for example is to form a groove in substrate, then, respectively be formed with one second dielectric layer, one second conductor layer and one the 3rd dielectric layer in regular turn on trenched side-wall, wherein keep an opening in the groove, open bottom exposes the part substrate.Then, form the one source pole line in opening, wherein the material of source electrode line for example is a polysilicon.
Described according to the preferred embodiments of the present invention, above-mentioned is etching mask with the first mask clearance wall, removes part first conductor layer, also comprises removing part first conductor layer up to the surface that exposes first dielectric layer.
The present invention also proposes a kind of non-volatility memorizer, comprises substrate, semiconductor element, first dielectric layer and first conductor layer.Wherein, have a groove in the substrate, semiconductor element is configured in the groove, and the end face of semiconductor element is higher than the surface of substrate.First dielectric layer is disposed in the substrate, and covers semiconductor component surfaces and substrate, and the surface profile that wherein covers the part of first dielectric layer of substrate is stepped that past semiconductor element height increases progressively.In addition, first conductor layer is configured on first dielectric layer, and the conformal part of first dielectric layer that covers the semiconductor element sidewall.
Described according to the preferred embodiments of the present invention, first rank that the past semiconductor element of the first above-mentioned dielectric layer increases progressively are 1: 2 with the length surface ratio on second rank.
Described according to the preferred embodiments of the present invention, the material of above-mentioned dielectric layer for example is a silica.
Described according to the preferred embodiments of the present invention, above-mentioned semiconductor element for example is a plough groove type semiconductor element.The plough groove type semiconductor element comprises second dielectric layer, second conductor layer, source electrode line and the 3rd dielectric layer.Wherein, second dielectric layer is disposed at a trenched side-wall and the part channel bottom in the substrate.Second conductor layer is disposed at trenched side-wall, and is positioned on second dielectric layer.Source electrode line is disposed in the groove, and the top of source electrode line is higher than the surface of substrate.The 3rd dielectric layer is disposed in the groove, and between second conductor layer and source electrode line.The material of above-mentioned source electrode line for example is a polysilicon.
The manufacture method of non-volatility memorizer of the present invention forms the stepped dielectric layer of a surface profile in substrate, so can make near the suprabasil dielectric layer thicknesses of layers of part of semiconductor element sidewall thicker, therefore under the situation that applies bias voltage, can produce higher resistance, and then cause the passage of the thicker dielectric layer below of thicknesses of layers to produce higher electric field, and cause the acceleration of electronics, so can effectively improve the efficient that writes of element.In addition, owing to removing part first dielectric materials layer in the step that exposes substrate surface, the time of the wet etch process that substrate surface is come out and carry out is shorter, therefore can avoid etching solution to corrode in the groove, and cause dielectric layer in the semiconductor element to produce the phenomenon of rete depression (encroach), so can improve the film layer quality of the dielectric layer in the semiconductor element, and lift elements usefulness and improve reliability of technology.And, because the dielectric layer rete between the semiconductor element and first conductor layer is thicker, therefore can avoids producing puncture voltage (breakdown) between the semiconductor element and first conductor layer, and influence element efficiency.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process generalized section according to the existing non-volatility memorizer that is illustrated.
Fig. 2 A to Fig. 2 J is the manufacturing process profile according to the non-volatility memorizer of the preferred embodiment that the present invention illustrated.
The simple symbol explanation
100,200: substrate
101: semiconductor element
102,102a: dielectric materials layer
104,104a, 218: conductor layer
106: clearance wall
201: the plough groove type semiconductor element
202: groove
204: tunnel oxide
206,208: floating grid
209: doped region
210,214,214a, 214b, 216,217: dielectric layer between grid
211: opening
212: source electrode line
215,220: the mask clearance wall
218a: conductor clearance wall
Embodiment
Fig. 2 A to Fig. 2 J is the manufacturing process profile according to the non-volatility memorizer of the preferred embodiment that the present invention illustrated.
At first, please refer to Fig. 2 A, provide substrate 200, and substrate 200 for example is a silicon base, in this substrate 200, form groove 202 afterwards.Wherein, the formation method of groove 202 for example is that the material of the mask layer of this patterning for example is a silicon nitride prior to the mask layer (not illustrating) of formation patterning in the substrate 200, and its formation method for example is a chemical vapour deposition technique.Continuing it, is mask with the mask layer of patterning, etching substrate 200, and form it.
Then, please refer to Fig. 2 B, form tunnel oxide 204 in groove 202 surfaces, for example be silicon oxide layer, and its formation method for example is a thermal oxidation method.
Then, in groove 202, insert one deck conductor layer (not illustrating).Wherein, the material of conductor layer for example is a doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, to carry out the ion implantation step, and form it.Then, remove the segment conductor layer until exposing substrate 200 surfaces, the above-mentioned method that removes the segment conductor layer comprises the etch-back step, and it for example is to finish in the mode of cmp.Then, conductor layer is carried out photoetching etching step (Patternized technique), to form two floating grids 206 and 208 in groove 202 both sides.In one embodiment, after forming two floating grids 206 and 208, can form a doped region 209 in the substrate 200 of groove 202 bottoms, its formation method for example is to carry out ion implantation technology.
Then, in forming dielectric layer 210 between grid in the substrate 200, for example be the polysilicon interlayer dielectric layer (Internal poly oxidation, IPO).Then, remove dielectric layer 210 between the part grid, to keep an opening 211 in groove 202, opening 211 bottoms expose part substrate 200.
Afterwards, please refer to Fig. 2 C, form the source electrode line 212 that for example is made of polysilicon in substrate 200, the top of this source electrode line 212 is higher than the surface of substrate 200, and fills up above-mentioned opening 211.In one embodiment,, after forming source electrode line 212, also can form another layer oxide layer in source electrode line 212 surfaces in forming in one embodiment, with in subsequent technique in order to protection source electrode line 212, but the present invention does not illustrate in this embodiment.
In Fig. 2 C, in opening 211, behind the formation source electrode line 212, in substrate 200, can form a plough groove type semiconductor element 201.Above-mentioned plough groove type semiconductor element 201 comprise tunnel oxide 204, floating grid 206 and 208, source electrode line 212 with and grid between dielectric layer 210.Certainly, the plough groove type semiconductor element among the present invention is other different structure also, and so long as structural top is higher than the semiconductor element of substrate gets final product, and be not limited to plough groove type semiconductor element mentioned in the foregoing description.
Then, please refer to Fig. 2 D, in forming dielectric layer 214 between grid in the substrate 200, for example be silicon oxide layer, and its formation method for example is to utilize chemical vapour deposition technique.
Afterwards, please refer to Fig. 2 E, on dielectric layer 214 between the grid of the sidewall of source electrode line 212, form corresponding a pair of mask clearance wall 215, wherein the formation method of mask clearance wall 215 for example is to form one deck layer of mask material on dielectric layer between grid 214, and its material for example is a silicon nitride, and then carries out an anisotropic etching process and can finish.
Then, please refer to Fig. 2 F, is etching mask with mask clearance 215, removes dielectric layer 214 between the part grid, and forms dielectric layer 214a between grid.Continue it, please refer to Fig. 2 G, remove mask clearance wall 215, and then remove that dielectric layer 214a can form dielectric layer 214b between grid, and the thickness of dielectric layer 214b for example is 10～20 dusts between grid until exposing substrate 200 surfaces between the part grid.Wherein, above-mentionedly remove that dielectric layer 214a for example is isotropic wet etching until the method that exposes substrate 200 surfaces between the part grid.
What deserves to be mentioned is, because the thicknesses of layers of dielectric layer 214a thin (shown in Fig. 2 F) between the grid that the thicknesses of layers of dielectric layer 214a is covered than mask clearance wall 215 between the grid that expose, so removing between the part grid dielectric layer 214a in the step that exposes substrate 200 surfaces, come out in substrate 200 surfaces and the time of the wet etch process of carrying out can comparatively shorten.In other words, because the time of above-mentioned wet etch process of carrying out is shorter, therefore can avoid etching solution to corrode in the groove 202, and cause tunnel oxide 204 to produce the phenomenon of rete depression, so can improve the film layer quality of tunnel oxide 204, lift elements usefulness and the reliability of improving technology.On the other hand, similarly, because the time of above-mentioned wet etch process of carrying out is shorter, so dielectric layer 214 can not removed fully between the grid of source electrode line 212 sidewalls, and still have dielectric layer 214 between the grid that remain with segment thickness, it helps follow-up technology.
Certainly, in another embodiment, the formation method of dielectric layer 214b also can for example be to be etching mask with mask clearance wall 215 between above-mentioned grid, directly removes between the grid of Fig. 2 E dielectric layer 214 until exposing substrate 200 surfaces, and then removes mask clearance wall 215 and get final product.
Continue it, please refer to Fig. 2 H, form dielectric layer 216 between another layer grid in substrate 200 tops, it for example is silicon oxide layer, and its formation method for example is a chemical vapour deposition technique, and between grid dielectric layer 214b and 216 can and usefulness, and be used as the isolation layer of adjacent two conductor layers jointly.Be described in more detail, between grid dielectric layer 214b and 216 surface profile be toward plough groove type semiconductor element 201 highly increase progressively stepped.Therefore, can make near the suprabasil dielectric layer thicknesses of layers of part of semiconductor element sidewall thicker, and under the situation that applies bias voltage, can produce higher resistance, and then cause the passage of the thicker dielectric layer below of thicknesses of layers to produce higher electric field, and cause the acceleration of electronics, so can effectively improve the efficient that writes of element.
It should be noted that the also available single etching step of dielectric layer forms between above-mentioned stair-stepping grid, the present invention is limited to this.
Then, please refer to Fig. 2 I, on dielectric layer between grid 216, form conductor layer 218, and the material of conductor layer 218 for example is a doped polycrystalline silicon.
Then, please refer to Fig. 2 J, on the conductor layer 218 of source electrode line 212 sidewalls, form pairing a pair of mask clearance wall 220.Wherein, the formation method of mask clearance wall 220 for example is to form one deck layer of mask material on conductor layer 218, and its material for example is a silicon nitride, and then carries out an anisotropic etching process and can finish.Afterwards, be etching mask with mask clearance wall 220, remove segment conductor layer 218 up to the surface that exposes dielectric layer 216 between grid, and form pair of conductors clearance wall 218a, it is word line (word line) that this conductor clearance wall 218a can be used as.Wherein, dielectric layer 214b between the above-mentioned grid that are positioned at conductor clearance wall 218a below and is positioned at conductor clearance wall 218a below, and not between covering gate between the grid of dielectric layer 214b the length of dielectric layer 216 ratio be preferably 1: 2.
From the above, because source electrode line 212 sidewalls remain with dielectric layer 214b between grid (shown in Fig. 2 G), therefore the rete of dielectric layer (being that dielectric layer 216 adds dielectric layer 214b between grid between grid) is thicker between the grid between source electrode line 212 and the conductor clearance wall 218a, so can avoid conducting between source electrode line 212 and the word line (being conductor clearance wall 218a), and influence element efficiency and reliability of technology.
Next, the structure of the resulting non-volatility memorizer of formation method that utilizes above-mentioned non-volatility memorizer is described.
Please referring again to Fig. 2 J, the structure of non-volatility memorizer comprises between substrate 200, plough groove type semiconductor element 201, grid dielectric layer 216, conductor clearance wall 218a between dielectric layer 214b, grid.
Wherein, have a groove 202 in the substrate 200, plough groove type semiconductor element 201 is configured in the groove 202, and the end face of plough groove type semiconductor element 201 is higher than the surface of substrate 200.Above-mentioned plough groove type semiconductor element 201 comprise tunnel oxide 204, floating grid 206 and 208, source electrode line 212 with and grid between dielectric layer 210.Tunnel oxide 204 is disposed at the bottom of groove 202 sidewalls and part groove 202, and floating grid 206 and 208 is disposed at groove 202 sidewalls respectively, and is positioned on the tunnel oxide 204.Source electrode line 212 is disposed in the groove 202, and the top of source electrode line 212 is higher than the surface of substrate 200, and wherein the material of source electrode line 212 for example is a polysilicon.Dielectric layer 210 is disposed in the groove 202 between grid, and floating grid 206 and 208 and source electrode line 212 between.
In addition, dielectric layer 214b and 216 can merge into dielectric layer 217 between grid between grid, to be used as the isolation layer between plough groove type semiconductor element 201 and the conductor clearance wall 218a.Dielectric layer 217 is to be disposed in the substrate 200 between grid, and covering groove formula semiconductor element 201 surfaces and substrate 200, the surface profile that wherein covers dielectric layer 217 between the part grid of substrate 200 be toward plough groove type semiconductor element 201 highly increase progressively stepped.Particularly, dielectric layer 217 stepped configurations between above-mentioned grid, the thickness of dielectric layer that therefore is positioned at plough groove type semiconductor element 201 sidewalls is thicker, so can produce higher resistance, and help improving the usefulness of element.
The material of dielectric layer 217 for example is a silica between above-mentioned grid, and the thickness of dielectric layer 214b is 10～20 dusts between grid.First rank that the past plough groove type semiconductor element 201 of dielectric layer 217 increases progressively between grid are preferably 1: 2 with the length surface ratio on second rank.
Conductor clearance wall 218a is configured between grid on the dielectric layer 217, and dielectric layer 217 between the conformal part grid that cover plough groove type semiconductor element 201 sidewalls.
Certainly, the structure that plough groove type semiconductor element of the present invention is not limited in the foregoing description to be illustrated, and also the semiconductor element that the top of all structures is higher than the surface of substrate all can be used method of the present invention.
In addition, what be worth paying special attention to is, when non-volatility memorizer during in the operation that writes data, after the source electrode line in the semiconductor element 201 212 was applied bias voltage, electronics can be injected in floating grid 204 or 206 by the passage (channel) in the substrate 200 of conductor clearance wall 218a below.Yet because dielectric layer 217 is thicker than the thicknesses of layers of dielectric layer between existing single grid between the grid in the substrate 200 of source electrode line 212 sides, and it can produce higher resistance.So, can cause the passage of dielectric layer 217 belows between the grid in the substrate 200 to produce higher electric field, and then cause the acceleration of electronics, and make electronics quicken to be injected in floating grid 204 or 206, so can effectively improve the efficient that writes of data.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1. the manufacture method of a non-volatility memorizer comprises:
Form semiconductor element in a substrate, the top of this semiconductor element is higher than the surface of this substrate;
Form one first dielectric layer in this substrate, cover this semiconductor component surfaces and this substrate, this first dielectric layer of part that wherein covers this substrate is stepped that past this semiconductor element direction height increases progressively;
On this first dielectric layer, form one first conductor layer;
On this first conductor layer of this semiconductor element sidewall, form a pair of first mask clearance wall; And
Is etching mask with this to the first mask clearance wall, removes this first conductor layer of part, makes at this this first conductor layer between first mask clearance wall and this first dielectric layer is formed the pair of conductors clearance wall.
2. the manufacture method of non-volatility memorizer as claimed in claim 1, the formation method of this first dielectric layer wherein comprises:
In this substrate, form one first dielectric materials layer, cover this semiconductor component surfaces and this substrate;
Remove this first dielectric materials layer of part, be positioned at this semiconductor component surfaces, and be positioned at this first dielectric materials layer of this suprabasil part of part to keep at least; And
Form one second dielectric materials layer in this substrate top, and this second dielectric materials layer covers this first dielectric materials layer and this substrate.
3. the manufacture method of non-volatility memorizer as claimed in claim 2 wherein removes this first dielectric materials layer of part, is positioned at this semiconductor component surfaces to keep at least, and is positioned at the method for this this first dielectric materials layer of suprabasil part of part, comprising:
On this first dielectric materials layer of this semiconductor element sidewall, form a pair of second mask clearance wall;
Is etching mask with this to the second mask clearance wall, removes this first dielectric materials layer that part exposes;
Remove this to the second mask clearance wall; And
Remove this semiconductor element sidewall and this first dielectric materials layer of this suprabasil part until exposing this substrate surface.
4. the manufacture method of non-volatility memorizer as claimed in claim 3 wherein removes this semiconductor element sidewall and comprises wet etching with this first dielectric materials layer of this suprabasil part until the method that exposes this substrate surface.
5. the manufacture method of non-volatility memorizer as claimed in claim 2, the thickness of this first dielectric materials layer that is positioned at this semiconductor element sidewall that wherein remains is 10～20 dusts.
6. the manufacture method of non-volatility memorizer as claimed in claim 2, wherein the material of this first dielectric materials layer comprises silica.
7. the manufacture method of non-volatility memorizer as claimed in claim 2, wherein the formation method of this first dielectric materials layer comprises chemical vapour deposition technique.
8. the manufacture method of non-volatility memorizer as claimed in claim 2, this first dielectric materials layer that wherein is positioned at this conductor clearance wall below is 1: 2 with the length surface ratio that is positioned at this conductor clearance wall below and does not cover this second dielectric materials layer of this first dielectric materials layer.
9. the manufacture method of non-volatility memorizer as claimed in claim 1 wherein should comprise silicon nitride to the material of the first mask clearance wall.
10. the manufacture method of non-volatility memorizer as claimed in claim 1 wherein is somebody's turn to do the formation method to the first mask clearance wall, comprising:
On this first conductor layer, form a layer of mask material; And
Carry out an etch process, remove this layer of mask material of part.
11. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein this semiconductor element comprises a plough groove type semiconductor element.
12. the manufacture method of non-volatility memorizer as claimed in claim 11, wherein the formation method of this plough groove type semiconductor element comprises:
In this substrate, form a groove;
Form one second dielectric layer, one second conductor layer and one the 3rd dielectric layer in regular turn on this trenched side-wall, wherein keep an opening in this groove, this open bottom exposes this substrate of part; And
In this opening, form the one source pole line.
13. the manufacture method of non-volatility memorizer as claimed in claim 12, wherein the material of this source electrode line comprises polysilicon.
14. the manufacture method of non-volatility memorizer as claimed in claim 1, be etching mask to the first mask clearance wall wherein with this, remove the part this first conductor layer step also comprise remove the part this first conductor layer up to the surface that exposes this first dielectric layer.
15. a non-volatility memorizer comprises:
One substrate has a groove in this substrate;
Semiconductor element is configured in this groove, and the end face of this semiconductor element is higher than the surface of this substrate;
One first dielectric layer is disposed in this substrate, and covers this semiconductor component surfaces and this substrate, and this first dielectric layer of part that wherein covers this substrate is stepped that past this semiconductor element direction height increases progressively; And
The pair of conductors clearance wall conformally covers this first dielectric layer of part of this semiconductor element sidewall.
16. non-volatility memorizer as claimed in claim 15, wherein this first dielectric layer that increases progressively toward this semiconductor element direction height comprises first highly higher rank and the second highly lower rank, and the length surface ratio on first rank and second rank is 1: 2.
17. non-volatility memorizer as claimed in claim 15, wherein the material of this first dielectric layer comprises silica.
18. non-volatility memorizer as claimed in claim 15, wherein this semiconductor element comprises a plough groove type semiconductor element.
19. non-volatility memorizer as claimed in claim 18, wherein this plough groove type semiconductor element comprises:
One second dielectric layer is disposed at a trenched side-wall and this channel bottom of part in this substrate;
One second conductor layer is disposed at this trenched side-wall, and is positioned on this second dielectric layer;
The one source pole line is disposed in this groove, and the top of this source electrode line is higher than the surface of this substrate; And
One the 3rd dielectric layer is disposed in this groove, and between this second conductor layer and this source electrode line.
20. non-volatility memorizer as claimed in claim 19, wherein the material of this source electrode line comprises polysilicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100920442A CN100411144C (en) | 2005-08-16 | 2005-08-16 | Nonvolatile memory and manufacturing method |
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|---|---|---|---|
| CNB2005100920442A CN100411144C (en) | 2005-08-16 | 2005-08-16 | Nonvolatile memory and manufacturing method |
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| CN1917180A CN1917180A (en) | 2007-02-21 |
| CN100411144C true CN100411144C (en) | 2008-08-13 |
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| CN106876319B (en) * | 2015-12-10 | 2018-03-27 | 华邦电子股份有限公司 | The manufacture method of memory element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1267915A (en) * | 1999-03-18 | 2000-09-27 | 株式会社东芝 | Non-volatile memory of semi-conductor and its producing method |
| CN1375114A (en) * | 1999-08-27 | 2002-10-16 | 马克罗尼克斯美国公司 | Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same |
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2005
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1267915A (en) * | 1999-03-18 | 2000-09-27 | 株式会社东芝 | Non-volatile memory of semi-conductor and its producing method |
| CN1375114A (en) * | 1999-08-27 | 2002-10-16 | 马克罗尼克斯美国公司 | Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same |
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