TW452834B - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

A manufacturing method of nonvolatile semiconductor memory device is disclosed, wherein trench-type devices are separated to form the device region and which have memory cell part disposed with a floating gate and peripheral circuit part. Before an STI trench (305) is embedded with an insulator, a bird's beak oxide film (310) in the upper end of an element region of a peripheral circuit is formed larger than that of a memory cell. Specifically, before an oxidation process for allowing the bird's beak to enter, the memory cell is covered with an oxidation-resistant film (308) or an oxide-nitride film, or an STI trench of the peripheral circuit is formed first, then the bird's beak of the end of the element region of the peripheral circuit is formed large. Otherwise, the oxide-nitride film is formed on the STI sidewall of the peripheral circuit part to prevent film reduction of a sidewall insulation film at the time of etching the oxidation film. The above-mentioned steps can be used to suppress current consumption at a waiting time by preventing formation of a parasitic transistor in a peripheral circuit of a nonvolatile memory using an STI (shallow trench isolation).

Description

5 2 8 3 4 _Case No. 89103960_ ^ January / Amendment_ V. Description of the invention (I) Background of the invention _ The present invention relates to a stack-type memory cell with a control gate and a floating gate, and its peripheral circuits. Non-volatile semiconductor memory device on the same wafer and manufacturing method thereof, particularly regarding formation of polysilicon tube for floating gate and separation of self-aligned channel-type elements, and suppressing non-volatile of transistor having distortion characteristics occurring in peripheral circuit portion Semiconductor memory device and manufacturing method thereof. Non-volatile semiconductor memory devices with control gates and floating gates and non-volatile semiconductor memory devices assembled on the same chip with peripheral circuits driven by them are known. Generally, in such a semiconductor memory device, a polycrystalline silicon layer for floating gate is formed to be separated from a self-aligned channel element (Shallow Trench Isolation: ST I). After the polysilicon for floating gate is removed by a transistor in a peripheral circuit, gate oxidation is performed again. And electrode formation. When the polycrystalline silicon for floating gates is removed, the area with peripheral circuit elements is exposed. Thereafter, the gate formed on the element area also falls into the side surface formed on the upper part of the element area. Once this gate sinks, a parasitic transistor is formed on the side of the element area. The low threshold characteristic curve caused by this parasitic transistor overlaps with the drain voltage and current characteristic curve of the MOSFET (metal oxide semiconductor field effect transistor). So-called distortion characteristics occur. When such distortion occurs, problems such as an increase in current when the memory device is in standby will be brought about. In order to prevent such twisting characteristics, it is necessary to form a plurality of bird beak portions (b i, t d s s be e k) in advance between the element region and the polycrystalline layer. In particular, once the action of attracting electrons to the silicon substrate from the floating gate is performed, the electric field concentration occurs in the part of the shape change, which is related to the error of the erasing speed of each cell. This error in erasing speed will cause the erased Vth distribution to widen, causing over-erasing problems in B0R type memory. However, if only performed in memory cells

O: \ 63 \ 63080.ptc Page 5 ^ 52834 _Case No. 89103960 January / Revised_ V. Explanation of the invention (2) To the extent that the bird's beak is formed at the end, the gate of the peripheral circuit will fall into ST Twisting characteristics of I. This is related to the increase of the subthreshold leakage of the peripheral circuit, and the current consumed by the semiconductor memory device during standby will increase. Please refer to Figures 24A-24D and 27A-27C to prove the above problems in detail. After the tunnel oxide film I 0 2 is formed on the silicon substrate I 0 I, polycrystalline silicon 1 03 (FIG. 24 A) is deposited to form a lower layer portion of the floating gate. Next, in order to form an element separation region, a shallow trench (ST I region) 104 is formed (FIG. 24B). At this time, the end of the floating gate is formed by self-alignment with the STI, and there is no case where the floating gate sinks into the STI channel, and it is not easy to cause a memory cell operation error. The ST I area was buried with an insulating film 105, and then the second polycrystalline silicon layer 106 in the upper part of the floating gate was deposited by deposition, and the cells were separated one by one (Figure 24C). Next, an insulating film 107 is formed between the floating gate formed by the upper opening and the control gate formed later. Generally, it is a three-layer structure film of oxide film / nitride film / oxide film (Figure 24D shows the steps for forming the peripheral circuit section. The insulating film of the peripheral circuit section is removed 1 0, the floating gate 1 0 3, 1 0. Tunnel oxide film 102. In the wet etching step of removing the accompanying oxide film, there is a case where the insulating film 10 embedded in the end of the STI is retracted to form a ridge. In this case, as described in Section 25, As shown in the figure, the gate electrode 108 of the peripheral circuit is close to the side of the active area of the aac. At the same time, the gate electrode overlaps the AA edge that causes the electric field to concentrate, forming a parasitic transistor. This parasitic transistor has a low valve. Value characteristics, which will overlap with the drain voltage and current of the main transistor.

The way to prevent this is as shown in Figure 2 7A.

^ 9 >, _Case No. 89103960_Jinian Yueyue / _i ± L · _ V. Description of the Invention (3) Before the insulating film 2 0 5 in 2 0 4 is fully oxidized, the first polycrystalline silicon Method for forming a bird's beak at the interface between 2 0 3 and silicon substrate 2 0 1. In this way, after removing the polycrystalline silicon and the tunnel oxide film in the peripheral circuit portion, as shown in FIG. 27B, the insulating film can be prevented from retreating at the end of the ST I. The polycrystalline silicon layer 206 forms a second polycrystalline silicon layer on the upper part of the floating gate. 2 0 7 series insulation film, 2 0 8 series polycrystalline silicon layer. However, if such a sufficient oxidation is carried out, a big problem will obviously occur. That is, as shown in Figure 7C, if the beak portion is enlarged to invade the floating gate 2 0 3 and the silicon substrate 2 2 of the memory cell area, the orientation of the polycrystalline silicon will be diversified. In terms of the shape error, the shape of the convex portion due to oxidation occurs, and the electric field is concentrated. As soon as such a shape error occurs, a difference in attraction speed occurs, for example, in the case of performing an operation of attracting electrons from a floating gate, causing a problem that the erased Vth distribution becomes wide. The large erasing distribution layer caused poor erasure action in N0R type flash memory. As described above, in order to suppress the distortion characteristics of the transistor of the peripheral circuit, the conventional ST I type non-volatile semiconductor memory device enlarges the interface between the polycrystalline stone substrate and the stone substrate to form a bird's beak. However, the bird's beak greatly invades between the floating gate of the memory cell and the silicon substrate. Therefore, a difference in the speed of attraction occurs when the self-floating gate is used to attract electrons, which causes the problem of the so-called erasing V t h widening. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile non-volatile memory cell that has less characteristic errors and does not have distortion characteristics in the peripheral circuit portion, so that current consumption does not increase during standby. Semiconductor memory device and manufacturing method thereof. In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is to form a device region by separating a channel-type device.

O: \ 63 \ 630SO.ptc Page 7 452834 _Case No. 89103960_ ^ January / Year Revised_ V. Description of the invention (4) Non-volatile memory cell with floating gate and peripheral circuit The method for manufacturing a semiconductor memory device is characterized by having a step of forming a polycrystalline silicon layer on a silicon substrate through an insulating film; in order to form a device region, the polycrystalline silicon layer, the insulating film, and the silicon substrate are self-aligned and etched, and formed in the silicon substrate. A step of using multiple channels at the bottom and surrounding the device separation of the device region; a step of rounding the individual ends of the device region and the polycrystalline silicon layer opposite to each other by oxidation; and a film with oxidation resistance covering only the memory cell And adding the step of forming the bird's beak-shaped oxide film in the element area of the peripheral circuit portion between the opposite end of the silicon substrate and the polycrystalline silicon layer on the opposite side of the memory cell portion, in addition to the oxidation after the formation of the oxidation-resistant film. . In the above manufacturing method, before the oxidation-resistant film is deposited, the peripheral circuit portion may be oxidized, the oxidation-resistant film may be selectively removed in the memory cell portion, and the oxidation-resistant film may be left only on the side of the floating gate. . Alternatively, after the peripheral circuit portion is oxidized, the opposite oxide film covering the memory cell portion may be removed. In order to achieve the above object, another method of manufacturing a semiconductor-to-memory memory device according to the present invention is to form a device region by separating a channel-type device, and to provide a non-volatile memory cell portion and a peripheral circuit portion. A method for manufacturing a volatile semiconductor memory device is characterized by having the steps of: forming a polycrystalline silicon layer on a silicon substrate through an insulating film; and only self-aligning etching the polycrystalline silicon layer, the insulating film, and the silicon substrate of the peripheral circuit portion to form a first element separation. The step of using a channel; the step of oxidizing the individual ends of the device region and the polycrystalline silicon layer facing each other in the peripheral circuit part to form a beak-shaped oxide film; the self-aligned etching of the polycrystalline silicon layer, the insulating film, and the silicon substrate Step of forming a second element separation channel; and after the second element separation channel is formed, it will be recorded

O: \ 63 \ 63080.ptc Page 8 452834 ^., _Case No. 89103960_Θ January 7th __ V. Description of the invention (5) Oxidation of the element region of the memory cell and the individual ends of the polycrystalline silicon layer facing opposite A step of forming a bird's beak-shaped oxide film which is thinner than the black-beak-shaped oxide film formed in the peripheral circuit portion. In order to achieve the above object, another method of manufacturing a non-volatile semiconductor memory device according to the present invention is to form a device region by separating a channel-type device, and to provide a non-volatile semiconductor memory device with a floating gate and a peripheral circuit portion. The manufacturing method of a volatile semiconductor memory device is characterized by: a step of forming an oxidation-resistant film on a silicon substrate by stacking an insulating film; a step of selectively removing an oxidizing film and an insulating film attached to a memory cell portion; and forming a tunnel oxidation The film is oxidized on the memory cell, like a step of forming an oxynitride film on a tunnel film. Polycrystalline stones are formed on the upper part of the tunnel oxynitride film of the memory cell and the upper part of the oxidation resistance film of the peripheral circuit part. Step of forming a layer; a step of self-aligning the #etched polycrystalline silicon layer and the silicon substrate to form a channel for element separation; and by oxidizing the channel after the formation of the element separation channel, the surface of the element region facing the polycrystalline silicon layer is oxidized. A step of forming a beak-shaped oxide film between the ends and forming a thicker beak-shaped oxide film at the peripheral circuit portion than the memory cell portion. In addition, in order to achieve the above object, another method of manufacturing a nonvolatile semiconductor memory device according to the present invention is to form a device region by using a channel element as a separation, and to include a memory cell portion provided with a floating gate and its peripheral circuit The method for manufacturing a non-volatile semiconductor memory device includes the steps of: forming a polycrystalline silicon layer on a silicon substrate through an insulating film; and self-aligning etching the polycrystalline silicon layer and the silicon substrate to form a channel for element separation and forming the element. Steps in the field; a step of rounding the individual ends of the device region and the polycrystalline silicon layer facing each other by oxidation; a step of covering only the memory cell portion with a silicon film; adding the aforementioned silicon film coating and oxidizing the peripheral circuit portion Silicon substrate and polycrystalline silicon layer

O: \ 63 \ 63030.ptc Page 9 9 PQ / • W L_ / Bu. _ Case No. 89103960_ To the year of the month / Yue __ V. Description of the invention (6) Between the opposite ends, a relatively A step of forming a bird-like oxide film on the memory cell; and a step of oxidizing the silicon film covering the memory cell. In order to achieve the above-mentioned object, another aspect of the non-volatile semiconductor memory device of the present invention is characterized by having: a semiconductor substrate; forming a plurality of memory cells, the memory cell portion located on the semiconductor substrate; and forming a circuit that controls the memory cell, located Peripheral circuit portions on the semiconductor substrate; a plurality of device regions formed on the memory cell portion and the peripheral circuit portion, separated by a plurality of channels; an insulating film buried in the channel; and an end portion embedded in the aforementioned oxynitride The gate insulating film defined by the film is a gate electrode formed on the element region of the peripheral circuit portion. The method for manufacturing a semiconductor memory device according to another aspect of the present invention is characterized by having the steps of forming an insulating film on a silicon substrate and forming a polycrystalline silicon layer of a floating gate; self-aligned etching the polycrystalline silicon layer and the silicon substrate to form a trench for element separation; A step of forming a channel; and a step of forming hafnium oxynitride on the inner wall of the channel and the side wall of the polycrystalline silicon layer. In this manufacturing method, the step of forming a silicon oxynitride film on the inner wall of the channel and the side wall of the polycrystalline silicon layer may also be performed by forming an oxynitride film on the inner wall of the channel and the side wall of the polycrystalline silicon layer, and then applying an oxynitriding treatment to form oxygen. Step of nitride film. According to another aspect of the present invention, a semiconductor memory device is characterized by comprising a memory cell array region in which the element region of the memory cell crystal is insulated and separated by a buried element separation region, and a peripheral circuit portion transistor forming a plurality of memory cell arrays. The peripheral transistor region of the peripheral circuit transistor is insulated and separated from the peripheral transistor region of the embedded element isolation region, and is set so that the curvature of the end of the element region of the peripheral circuit transistor is substantially larger than that of the element region of the memory cell transistor. The curvature of the part is large.

O: \ 63 \ 63080.ptc Page 10 452834 _Case No. 89103960_gf year 0f / Revision_ V. Description of the invention (7) In this semiconductor memory device, the height of the flat portion of the aforementioned element area is higher than the upper gate The height difference of the lowest part of the electrode can also be more than 4 nm. In this semiconductor memory device, at least a part of the gate electrode of the memory cell transistor may be configured to align itself with the embedded component separation area in the memory cell display area. In this semiconductor memory device, the aforementioned memory cell transistor may also be a memory cell of a non-volatile semiconductor memory device having a floating gate. The manufacturing method of another aspect of the present invention is characterized in that a part of the gate insulating film of the M 0s transistor is formed before the element separation forming step, and the remaining part of the foregoing gate insulating film is formed after the element separation forming step. When manufacturing a semiconductor memory device, a MOS transistor is formed, and the curvature of the end of the device region of the MOS transistor having the gated insulating film formed after the aforementioned element separation forming step is implemented more than that before the aforementioned element separation forming step. The element field of the MOS transistor forming the gate insulating film has a large curvature. The method for manufacturing a semiconductor memory device according to another aspect of the present invention is characterized in that: when manufacturing a non-volatile semiconductor memory device having a memory cell array region and a peripheral transistor region forming a peripheral circuit transistor, a memory cell is formed. The first gate insulating film for crystals is applied to the semiconductor substrate in its entirety, in the steps of forming a polycrystalline silicon film and an insulating film thereon; and forming a trench for forming a separation region of the aforementioned insulating film, polycrystalline silicon film, first gate insulating film, and a semiconductor substrate. The step of covering the area of the memory cell array and removing the first gate insulating film on the end of the element region of the peripheral transistor region; the surface of the aforementioned channel and the element region of the peripheral transistor region

O: \ 63 \ 63080.ptc Page 11 4 523 3 Amendment No. 89103960 V. Description of the invention (8) Surface oxidation step of the part between the end and the polycrystalline silicon film thereon; special buried insulator is buried in the aforementioned channel A step of flattening the whole surface; a step of removing the insulating film on the polycrystalline silicon film; and removing the polycrystalline silicon film and the first gate insulating film of the peripheral transistor region to form a second gate insulating film for the peripheral circuit transistor Steps: forming a stacked gate structure having a polycrystalline silicon film as a floating gate in the aforementioned memory cell array region, and forming a gate electrode on the aforementioned second gate insulating film in a peripheral transistor region; and forming a transistor A step of selectively introducing the source / drain impurities into the surface layer portion of the substrate. A method for manufacturing a semiconductor memory device according to another aspect of the present invention is characterized in that a memory cell transistor is formed when a nonvolatile semiconductor memory device having a memory cell array region and a peripheral transistor region forming a peripheral circuit transistor is manufactured. A step of using a first gate insulating film to meet a semiconductor substrate and forming a polycrystalline silicon film thereon; a step of forming a polysilicon film on the aforementioned polycrystalline silicon film, the first gate insulating film, and a semiconductor substrate forming element separation region; a buried insulator The step of burying the aforementioned channel to completely flatten it; forming a floating gate of the memory cell transistor on the substrate to control the inter-gate insulating film for inter-gate insulation; removing the inter-gate insulation of the peripheral transistor region Film, polycrystalline silicon film, and first gate insulating film to expose the element region; step of etching the corners of the end of the element region exposed to the peripheral transistor region to make it or a circular shape; to the peripheral transistor region A step of forming the second gate insulating film for the aforementioned peripheral circuit transistor; The structure of the stacked gate of the aforementioned polycrystalline silicon film for the floating gate, the step of forming a gate electrode on the aforementioned second gate insulating film in the peripheral transistor region; and a source / drain hybrid that will constitute the transistor

O: \ 63 \ 630SO.ptc Page 12 4528 3 4 _Case No. 89103960_ Contains% 芍 月 / 曰 __ V. Description of the invention (9) The step of mass selective introduction into the surface layer of the substrate. Brief Description of the Drawings Figs. 1A to 1D are sectional views showing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention in sections. Figures 2A-2C are sectional views showing the subsequent steps of Figure 1D. Figures 3A-3C are sectional views showing the subsequent steps of Figure 2C. Figures 4A-4D are sectional views showing the subsequent steps of Figure 3C. Figure 5 is a sectional view showing the subsequent steps of Figure 4D. 6A to 60 are sectional views for explaining a method for manufacturing a semiconductor memory device according to a second embodiment of the present invention. Figure 7 Λ _ 7C is a sectional view showing a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention in sections. Figures 8A and 8B are sectional views showing subsequent steps of Figure 7C. Figures 9Λ-9D are sectional views showing a method for manufacturing a semiconductor memory device according to a fourth embodiment of the present invention. Figures 10 A-10 C are sectional views showing subsequent steps of Figure 9 D. Figures 1 1 A-1 1 D are sectional views showing a method of manufacturing a semiconductor memory device according to a fifth embodiment of the present invention in sections. Figures 1 2 A-1 2 C are sectional views showing the subsequent steps of Figure 11 D. Figures 1 3 A-1 3 C are sectional views showing the subsequent steps of Figure 1 2 C. Figures 14A-14D are sectional views showing subsequent steps of Figure 13D. 15A-15D are sectional views showing a method for manufacturing a semiconductor memory device according to a sixth embodiment of the present invention. Figures 16 A-1 6 C are sectional views showing the subsequent steps of Figures 15 D. Figures 1 7 A-1 7 D are sectional views showing the subsequent steps of Figure 16 C.

O: \ 63 \ 63080.ptc Page 13 4 528 3 4 _Case No. 89103960 V. Description of the Invention (10) Sections 8A-18D are sectional views showing a method for manufacturing a semiconductor memory device according to a seventh embodiment of the present invention. . Figures 19 A-1 9 D are sectional views showing the subsequent steps of Figure 18 D. Figures 20A and 20B are enlarged sectional views showing an example of the shape of the part shown in 0 in Figure 2C of the present invention and an example of the shape of the part after the device is completed. Figures 2 1 A-2 1 C are sectional views showing a part of the manufacturing process of the N 0 R type flash EEPROM according to the eighth embodiment of the present invention. Figures 2 2 A-2 2 D are sectional views showing part of the subsequent steps of Figure 2 1 C. Fig. 23 is an enlarged sectional view showing an example of the shape of the portion indicated by 0 in Fig. 2 2C. 24A-24D are sectional views showing a conventional method for manufacturing a semiconductor device in sections. Fig. 25 is a cross-sectional view for explaining a parasitic transistor occurring in a conventional semiconductor memory device. Fig. 26 is an enlarged cross-sectional view of a portion 0 in Fig. 25. Figures 2 7 A-2 7 C are cross-sectional views illustrating the method of forming a bird's beak in a conventional semiconductor memory device and its problems. Fig. 28 is an enlarged cross-sectional view of a portion 0 in Fig. 25. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A to 1D to 5 are sectional views showing a method of manufacturing a semiconductor memory device according to a first embodiment of the present invention, and a sectional view of a peripheral circuit portion.

O: \ 63 \ 6308O.ptc Page 14 452834 __Case No. 89103960__sf Health q Month / -------- V. Description of the invention (11) ^ First of all, on the silicon substrate 3 〇1, for example, 10 nm ( Nanometer) of the cell tunnel oxide film 3 02. Next, a first polycrystalline stone layer 303 (FIG. 1A) constituting the lower part of the sub-i is formed on the upper part of 70 nm. It is usually further thereon; for example, an oxide stone film of 4,000 nm. Thereafter, a resistive pattern forming part of the opening of the ST I channel is formed by photolithographic steps, and a silicon oxide film 3 0 4 is formed according to the resistive pattern (FIG. 1B). > Next, the oxide film 3 04 was masked, and the first floating gate polycrystalline silicon 3 0 3, the tunnel oxide film 3 0 2 and the silicon substrate 3 0 1 were sequentially etched by the RI method. The trench 305, which is dug out from the silicon substrate 3 0 1, is a trench for separating elements (Shaw Trench Isolation: STI). Secondly, at the interface between the first polycrystalline silicon 3 0 3 and the silicon substrate 3 01 that becomes the floating gate, suppression is made to the minimum amount of oxidation. The edge of the bird's edge projects into a small amount of oxidation, such as 10 nm. Thermal oxidation step. Thereby, a thermal oxide film 3 0 6 is formed (Fig. 1C).

Next, a thin oxide film 307 is deposited by a CVD method. Further, an oxidation-resistant film is deposited thereon, specifically, for example, a 6 nm silicon oxide film 3 08 (Figure 1 D). Next, through a photolithography step, a resistive pattern 309 (FIG. 2A) having only peripheral circuit openings is formed on the substrate. The resistance pattern 309 is masked to remove the oxidation-resistant film 3 0 8 in the peripheral circuit portion (Fig. 2B). For example, if it is a silicon nitride film, it can be removed by methods such as CDE (Chemical Dry Etching). Furthermore, the CVD oxide film 307 formed under the oxidation-resistant film is deposited and buried in ST I. In the case of an insulating film, it achieves the function of reducing damage deep into the silicon substrate. Second, the device region is formed to form a beak portion on the peripheral circuit portion.

O: \ 63 \ 63080.ptc Page 15 452834 _ Case No. 89103960__1 Month / _iMi___ V. Description of the invention (12) (Silicon substrate 3 0 1) and the first polycrystalline silicon layer 3 〇3 Opposite end portions Oxidation (Figure 2C). The bird's edge portion 31 formed by this oxidation reduces the gate sink when the peripheral circuit is formed later. Therefore, 'this oxidation is performed under the condition that a sufficient amount is formed, for example, a 30 nm oxidized film on a silicon substrate. At this time, the memory cell was covered with an oxidation-resistant film 3 0 8 without being oxidized. Therefore, the 'bird's beak portion is not formed on the opposite end portions of the element area of the memory cell portion (the silicon substrate 3 001) and the first polycrystalline silicon layer 3 03. Therefore, the curvature of the element area of the peripheral circuit portion can be made substantially larger than the curvature of the element area of the memory cell portion. Furthermore, the oxidation resistant film may be removed later if necessary. If the silicon nitride film exists near the memory cell, there is a possibility that the tunnel oxide film will be damaged by nitrogen diffused from the bottom surface, so 'it is very good to remove the silicon nitride film if necessary', but this example shows that it is not removed. . In addition, in the case of removing the silicon nitride film, it can be removed by the etching using hot galvanic acid or CDE (CHEMICAL DRY ETCHING) after the step in FIG. 1D. Secondly, 'for burying inside the STI' is deposited. For example, plasma oxide film 3 11 (Figure 3A). In the case of high aspect ratio, high density plasma (HdP) CVD method is also used for deposition. For example, by CMP (Chemical Mechanical Polishing (Ch em i ca 1 Mechanical Polishing) to planarize the plasma oxide film 311 (Fig. 3B). Next, the silicon nitride film 3 0 4 on the first polycrystalline silicon 3 3 for floating gate is removed by a wet etching method. In order to adjust the height of the insulating film 3 11 embedded in the ST I, it is also possible to etch several insulating films 3 1 1 before removing the nitride film. Thereafter, a second polysilicon layer 3 for floating gates is formed thereon. 1 2. Further perform the photolithography step and etching of the floating gate separation area 3 1 3 on the ST I area, thereby forming the floating separation 3 1 2 of cells one by one (Figure 3C).

O: \ 63 \ 63080.ptc Page 16 528 3 4 _Case No. 89103960_ Said year, month, month, month, day, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month. The insulating film is, for example, a laminated insulating film 314 (FIG. 4A) that forms an oxide film / nitride film / oxide film (0 N 0). Thereafter, the drawings show only peripheral circuit portions. Secondly, through the photolithography step, the memory cell region * is dry-etched to remove the 0 N 0 film 3 1 4 in the peripheral circuit area, and the floating gate is removed with the first and second polycrystalline silicon 3 0 3, 3 1 2 and removed by wet etching. Tunnel oxide film 3 1 2 (Figure 4B). By fully forming the gate beak portion, the upper end portion of the device region can be protected during this wet etching to prevent the oxide film from sinking into the upper end portion. Next, a gate oxide film 3 1 5 of 15 nm is formed on the surface of the substrate of the peripheral circuit (FIG. 4C), and then a polycrystalline silicon layer 3 1 6 is formed on the surface (FIG. 5). The polycrystalline silicon layer was worked for 316 times to form a gate electrode of a peripheral circuit portion and a control gate electrode of a memory cell portion. Secondly, although not shown, gate processing of peripheral transistors and memory cell transistors is performed as usual thereafter. A diffusion layer is formed in the memory cell and peripheral circuit portions, and further wiring steps are performed. This completes the memory cell line. By adopting the above steps, the bird's beak portion is prevented from invading the memory cell portion, and the bird's beak portion is only large enough to invade the semiconductor memory device of the peripheral circuit. That is, the curvature of the element region of the peripheral circuit portion can be made substantially larger than the curvature of the element region of the memory cell portion. (Second embodiment) Although the first embodiment covers the entire memory cell area with a silicon oxide film, if the silicon oxide film covers the entire area and is subjected to heat treatment, the tunnel oxide film 3 with the memory cells deteriorates. In order to limit this phenomenon to a minimum, the oxidation-resistant film can also be formed into a sidewall shape on the side of the floating gate of the memory cell. 2nd Real

O: \ 63 \ 63030.ptc Page 17 452 3 Case No. 89103960 Amendment V. Description of Invention (14) The method is provided in the embodiment. _ First, the steps 1A-1D of the first embodiment are performed. After depositing the oxidation resistant film 308 in Fig. 10, the entire surface was etched with R I E, leaving only the oxidation resistant film on the sidewall. Thereby, the structure shown in FIG. 6 is obtained. After that, by performing the same steps as in FIG. 1 and subsequent steps of the first embodiment, a structure in which the oxidizing film remains only on the side wall of the floating gate and the inner wall of the STI is completed. (Third Embodiment) Figs. 7 and 8 are sectional views showing a method of manufacturing a semiconductor memory device according to a third embodiment of the present invention. First, a tunnel oxide film 502 of, for example, a memory cell of 10 nm is formed on the entire surface of the silicon substrate 501, and secondly, a polycrystalline silicon layer 5 0 3 constituting a part of the floating gate at a thickness of 70 nm is formed on the silicon substrate (FIG. 7A). ). Further, a 200 nm silicon nitride film 504 is deposited thereon (FIG. 7B). Thereafter, through a photolithography step, a resistive pattern (not shown) forming a part of the opening of the ST I channel only in the peripheral circuit portion is formed, and processed to form a gasified stone film 504. Next, the nitride film is masked, and the first polycrystalline silicon layer for floating gate 501, the tunnel oxide film 50, and the silicon substrate 501 are etched vertically and sequentially by the RIE method to form STI 505. Next, for example, an oxidation of 30 nm is performed, and a sufficient bird's beak-shaped oxide film 506 is formed at the interface between the polycrystalline silicon layer 503 on the peripheral circuit portion and the silicon substrate 501 (Fig. 7C). At this time, the upper surface of the memory cell portion is covered with a silicon nitride film 504 so as not to be oxidized. Next, the STI channel 5 07 of the memory cell portion is formed (FIG. 8A). Then, the memory cell performs the minimum necessary oxidation, for example, the oxidation of 6 10 nm. An oxide film 508 is formed (Fig. 8B). After that, a step of forming the insulating film embedded in the STI corresponding to FIG. 3 of the first embodiment is performed.

O: \ 63 \ 63080.ptc Page 18, 4528 3 4 _Case No. 89103960_January / Amendment_5. Description of the invention (15) The bird's beak does not invade the memory cell by the above steps. The bird's beak portion is only large enough to invade the semiconductor memory device of the peripheral circuit portion. That is, the curvature of the component area of the peripheral circuit portion can be made substantially larger than the curvature of the component area of the memory cell portion. (Fourth embodiment) Figures 9 A-9 D, 10 A-1 0 C are sectional views showing a method of manufacturing a semiconductor memory device according to a fourth embodiment of the present invention in sections. First, a first thick oxide film is formed on the broken substrate 601, for example, an oxide film 602 having a degree of 20 nm (FIG. 9A). Next, a pair of oxidizing films of 8 nm, such as a nitrided film 603, are deposited on the upper portion. Secondly, the residual resistor 604 is left in the peripheral circuit part by the photolithography step, and the silicon nitride film 6 0 3 in the memory cell part is removed (FIG. 9C). After removing the resistance, the 20 nm silicon oxide in the memory cell part is etched. membrane. Next, a tunnel oxide film 605 having a thickness of 9 nm is formed on the memory cell. Since there is an oxidation-resistant film (silicon nitride film) 603 in the peripheral circuit portion, no change occurs. Next, nitrogen is introduced into the tunnel between the oxide film 605 and the silicon substrate 601 by a nitriding process (Fig. 9D). Since this nitriding prevents the beak of the black beak from invading in the subsequent steps, and generally speaking, the tunnel oxide film is made of oxynitride, so the reliability of the cell is improved. And since the peripheral circuit portion is covered with the nitride film 603 at this time, the interface between the first nitride film 602 and the silicon substrate 601 is not nitrided. Nitriding treatment is generally performed by thermal treatment in a gas of ammonia, N20, or NO. Next, a first polycrystalline silicon layer 606 having a floating gate lower layer portion of 70 nm is formed on the upper portion (FIG. 10A). Usually, a silicon nitride film 607 of 200 nm is further deposited thereon. Thereafter, a STI channel is formed by a photolithography step.

O: \ 63 \ 63080.ptc Page 19 4 5283 4 _Case No. 89103960_gf Years / Months / Revisions_ V. Description of the invention (16) The resistance pattern of the part of the opening, this silicon nitride film 6 0 7 is processed. Next, the nitride film 6 0 7 is masked, and the first polycrystalline silicon layer for floating gate 6 6, the silicon nitride film 6 0 3, and the first oxide film 6 0 2 on the bottom layer are sequentially etched vertically by the RIE method. And a silicon substrate 6 0 1, a polycrystalline silicon layer 6 0 6 for a floating gate of a memory cell, a tunnel oxide film 6 Q 5, and a silicon substrate 6 0 1. Shallow trenches (STIs) for trench isolation on silicon substrates (Fig. 10B). Next, a black beak is formed on the end of the interface between the device region of the peripheral circuit portion and the silicon oxide film 603 (Fig. 10C). Although the oxide films 6 0 9 and 6 1 are formed by this oxidation, the peripheral beak portion 6 1 0 formed by the peripheral circuit can be reduced below the gate electrode when the peripheral circuit is formed. Therefore, although this oxidation is performed in a sufficient amount, at this time, the tunnel oxide film of the memory cell portion is nitrided, so that the bird's beak portion is difficult to invade. On the other hand, since there is an unoxidized original silicon oxide film 6 0 2 on the element region, a bird's beak portion 6 1 0 which is more primitive than the memory cell portion can be formed at the interface between the silicon substrate 6 0 1 and the silicon oxide film 6 0 2. . In addition, the original silicon oxide film 602 of the peripheral circuit portion and the silicon nitride films 603, 606, and 609 on the upper portion are all removed before the gate oxide film of the peripheral circuit portion is formed (corresponding to the fourth Β of the first embodiment). Figure steps). Also by the above steps, the black beak portion is prevented from invading the memory cell portion. The beak portion is only large enough to invade the semiconductor memory device of the peripheral circuit portion. That is, the curvature of the element region of the peripheral circuit portion can be made substantially larger than the curvature of the element region of the memory cell portion. (Fifth Embodiment) Figures 1 1 A-1 1 D to 1 4 A-1 4 C are sectional views showing a method of manufacturing a semiconductor memory device according to a fifth embodiment of the present invention in sections.

O: \ 63 \ 63080.ptc Page 20 452834 Case No. 89103960 Month / Amendment V. Description of the Invention (17) First of all, on the Shi Xi substrate 7 0 1 a full formation of memory cells such as 1 0 m Oxide film 7 0 2. Next, a first polycrystalline stone layer 703 (Fig. 11A) constituting the lower layer portion of the floating gate is formed at a height of 70 m. On the other hand, a nitride film of 700 nm, for example, 2000 nm, is further deposited thereon. Thereafter, a silicon nitride film is processed by 'forming a pattern of a part of the opening constituting the ST I channel by a photolithography step'. Next, the nitride film is masked, and the polycrystalline silicon layer for the first floating gate, the hafnium oxide tunnel, and the silicon substrate are sequentially processed by the R] E method. A trench (s τ 丨) for the isolation of a shallow trench system, which is dug in a silicon substrate (Figure 1 i B).

Secondly, oxidization is performed to reduce the amount of oxidation as low as possible, so that the beak portion of the black owl does not extend too far into the interface D between the first polycrystalline silicon and the stone substrate that forms the floating gate. For example, a 10 nm thermal oxidation step is performed. Thereby, a thermal oxide film 706 is formed (FIG. 11C). Next, an oxide film 707 is deposited thereon by a CVD method. Further, a silicon film is formed thereon. Specifically, a 10 nm amorphous silicon film 7 0 8 was deposited by a low pressure CVD (LPCVD) method (Fig. 11D). Secondly, a resist pattern 7 0 9 (the first 2 A) is formed by the photolithography step with only the peripheral circuit portion opened. For example, if it is an amorphous silicon film, it can be removed by a method such as c d E. In addition, the CVD oxide film 704 formed under the silicon film can reduce the damage and penetrate deep into the silicon substrate when a buried insulating film is deposited inside the ST I. Secondly, oxidation is carried out, and the beak portion of the scorpion stalk extends into the ST I end edge of the peripheral circuit portion (Figure 1 C) ^ The beak portion 7 1 0 formed by this oxidation can reduce the gate electrode when the peripheral circuit portion is formed later Fall into. Therefore, this oxidation proceeds in sufficient amount. For example, it is performed under the condition that a 30 nm oxide film is formed on a silicon substrate.

O: \ 63 \ 63080.ptc Page 21 452834 ____Serial number 89103960_ # 年 彳 月 / 日 五 、 Description of the invention (18) On the other hand, the memory cell is covered by an amorphous silicon film 7 0 8 The bird's beak at the upper end of the element area of the peripheral circuit portion is completely oxidized when oxidized, and the amorphous silicon film 708 forms a silicon oxide film 711, and the film thickness is also about 20 times that of 20 nm. After the crystalline film 7 0 8 is completely formed in the amorphous portion of the cell, the oxidant diffuses in the silicon oxide film 7 1 1, the silicon substrate 7 0 1 and the first polycrystalline silicon in the lower part of the floating gate. The layer 7 0 3 is also oxidized. 8 However, the oxidant diffuses in the silicon oxide film 7 1 1 and further diffuses in the oxide film 7 0 6 formed by the c VD method, and reaches the Shi Xi substrate 7 0 1 or the polycrystalline sand film 7 0 3, so ' The oxidation rate of the silicon substrate 7 0 1 and the first polycrystalline silicon film 7 0 3 in the lower part of the floating gate is greatly suppressed. Therefore, in this step, the beak portion hardly extends into the upper end portion of the element area of the memory cell portion. The amount of oxidation required for the bird's beak to reach the upper end of the device area of the peripheral circuit part must be equal to the amount of oxidation used to completely form the silicon film 7 08 deposited on the memory cell 7 1 1 'In addition, it is necessary to prevent the beak portion from almost reaching the upper end of the element region of the memory cell portion. In consideration of this situation, the deposition film thickness of the oxidized dream film 708 is set. Next, a plasma oxide film 7 1 0 is deposited, for example, and buried in ST I (1 3 A1). In the case of high aspect ratio, high density plasma (HDP) C VD is also used for deposition. Next, the plasma oxide film is planarized by, for example, the CMP method (Fig. 13B). Next, the silicon oxide film 704 on the polycrystalline silicon 703 for the first floating gate is removed by a wet etching method. Depending on the circumstances, in order to adjust the height of the insulating film 712 embedded in the STI, a number of insulating films 71 2 are also etched before the oxide film 70 4 is removed. Thereafter, a second polysilicon layer 7 1 3 for a floating gate is formed on the entire surface of the substrate. Further performing the photolithography step and etching of the floating gate separation region 7 1 4 on the ST region,

O: \ 63 \ 630SO.ptc Page 22 452834 _Case No. 89103960_Sf / January __ V. Description of the invention (19) Processing is performed to enable the floating gate to be separated according to each cell-(Figure 1 3 C ). Next, an insulating film between the floating gate and the control gate is formed on the floating gate 7 1 3, for example, a laminated insulating film 715 (FIG. 14A) formed with an oxide film / nitride film / oxide film (0 N 0). Hereinafter, only the peripheral circuit portion is illustrated. Next, through the photolithography step, the memory cell portion is covered with resistance, the ON0 film of the peripheral circuit portion is wet and dry 7 1 5. The first and second polycrystalline silicon 7 0 3, 7 1 3 are used for the floating gate, and the tunnel oxide film is removed by wet etching (Figure 1 4B). During this wet etching, the gate bird's beak portion is fully formed to protect the upper end of the device region and prevent the oxide film from sinking into the upper end. Secondly, a necessary oxide film thickness is formed on the peripheral circuit portion, for example, a gate oxide film 7 1 6 of 15 nm (Fig. 14C), and secondly, a polycrystalline silicon layer 7 1 7 is formed on the upper portion (Fig. 14D). This polycrystalline silicon layer 7 1 7 constitutes a gate electrode and a memory cell control gate of a peripheral circuit portion. Secondly, although the illustration is omitted, the gate processing of the peripheral circuit body and the memory cell transistor is usually performed after that. A diffusion layer is formed on the memory cell portion and the peripheral circuit portion, and further wiring steps are performed to complete the memory cell array. Also by the steps described above, the black beak portion is prevented from invading the memory cell portion, and the bird's beak portion is only large enough to invade the semiconductor memory device of the peripheral circuit portion. That is, the curvature of the element region of the peripheral circuit portion can be made substantially larger than the curvature of the element region of the memory cell portion. (Sixth embodiment) Figures 15A-15D to 17A-17D are sectional views showing a method of manufacturing a semiconductor memory device according to a fifth embodiment of the present invention in sections. This embodiment is different from the first to fifth embodiments in that it does not form a large bird's beak portion at the upper end of the element area of the peripheral circuit portion, and covers the S T I sidewall of the peripheral circuit portion with an oxynitride film.

O: \ 63 \ 63080.ptc Page 23 45283 Case No. 89103960 Rev. V. Description of the Invention (20) When the ST I buried insulating film is etched, the side of the device region is prevented from being exposed, thereby suppressing peripheral circuit parts The element trapped in the gate electrode is on the side of the area. Although the following describes the manufacturing process with reference to the drawings, the drawings Nos. 15 to 17 are applicable to both the memory cell and peripheral circuit parts, and the Nos. 17B to D are applicable to the circuit parts of the peripheral circuit part. First, a silicon oxide film 8 0 2 of a random oxide film constituting a memory cell is formed on the Shi Xi substrate 8 0 1 in its entirety. Next, a first polycrystalline silicon layer 80 which constitutes a lower part of the floating gate 70 is formed on the upper part 80 (FIG. 15A). Further, a nitride nitride film 804 of, for example, 200 nm is usually deposited thereon. Thereafter, a resist pattern of a part of the opening constituting the ST I channel is formed by a photolithography step, and the silicon nitride film is processed. Next, the nitride film is masked, and the first polycrystalline silicon layer for the floating gate, the tunnel oxide film, and the sand substrate are sequentially processed by the R 1 E method '. A trench (ST j) for separating a shallow trench system on a silicon substrate is dug (FIG. 15B). Step Interface of the substrate. Thereby, a thermal oxide film 806 is formed (FIG. 15C). Secondly, by a CVD method, for example, an oxide film J 6 of 20 nm is deposited thereon, and then a process of turning the silicon oxide films 80 6 and 80 7 into a thermal oxide film is performed). Specifically, 'the processor 60 is known in an atmosphere of 900 t'-further processing is performed in an atmosphere of 900 ec for 60 minutes. By this, an interface region between the silicon oxide film 806 and silicon and a surface region of the silicon oxide film 807 are formed, and an oxynitride film containing several% of nitrogen is formed. Secondly, deposit, for example, plasma oxide film 8 1 Secondly, perform oxidation with the lowest possible amount of oxidation. For example, thermal oxidation at 10 nm will not allow the beak of the bird to extend too far into the first polycrystalline silicon and silicon pattern forming the floating gate.) Embedded in STI (16A also uses high density plasma (HDP) CVD for high aspect ratios)

45283 4 __Case No. 89103960_ # January / _____ V. Description of the invention (21) Deposition. Next, the plasma oxide film is planarized by, for example, the CMP method (Fig. 16B). Next, the wet-etching method removes the oxide film 804 on the polycrystalline silicon 803 for the first floating gate. Depending on the situation, in order to adjust the height of the insulating film 8 1 2 embedded in the ST I, a number of insulating films 8 1 2-are etched before the nitride film 8 0 4 is removed, and a second floating layer is formed on the substrate. Polycrystalline silicon layer for gate 8 1 3. Further, the photolithography step and etching of the floating gate separation region 8 1 4 are performed on the ST T region, and processing is performed so that the floating gate is processed according to each cell-separation (FIG. 16C). Next, a laminated insulating film 815 (FIG. 17A) is formed on the floating gate 8 1 3 to form an insulating film between the floating gate and the control gate, for example, to form hafnium oxide, hafnium nitride, or oxide film (ONO). Hereafter, only a part constituting the peripheral circuit portion is illustrated. Secondly, the memory cell portion is covered with a resistor (not shown), and the ONO film, the first and second polycrystalline silicon 8 0 3, and 813 in the peripheral circuit portion are removed dry and wet, and the tunnel oxide film 8 0 2 (the first 7 B is removed by wet etching). Figure). When this wet sweet is performed, the side wall of < 5 evening and the side of the first floating closure 8 0 2 are covered with an oxynitride film 8 0 6 '8 0 7, so the etching of this part The speed is slower than the etching speed of the tunnel oxide film 802. Therefore, the side surface of the upper end portion of the 'element region is not exposed. Its-man 'forms a necessary oxide film thickness on the peripheral circuit portion, for example, an open-electrode oxide film 8 1 6 (Fig. 17 C) of 15 ^ m'. Secondly, a polycrystalline silicon layer 8 1 7 ( Figure 17 D). This polycrystalline silicon layer constitutes the gate electrode of the peripheral circuit portion and the control gate of the memory cell. In this embodiment, a silicon oxide film 807 is formed on the inner wall of ST I by an oxidation process, but silicon oxide films 806 and 807 do not need to be two layers. A single-layer silicon oxide film is also fine. Secondly, although the illustration is omitted, the peripheral circuit section and the memory cell transistor are performed.

O: \ 63 \ 63O80.ptc Page 25 452834 _Case No. 89103960_β 年月 月 / 日 改 _ Five. Invention description (22) The gate processing is usually carried out after this, forming diffusion in the memory cell and peripheral circuit Layer, further performing a wiring step, thereby completing the memory cell array. In this embodiment, the side surface of the upper end portion of the element region after the gate electrode of the peripheral circuit portion is formed is covered with at least the oxynitride film formed on the inner wall of the ST I, so the distortion characteristics of the peripheral transistor will not occur due to the thin film of the oxide film. . According to the inventions disclosed in the first to fifth embodiments, since a large bird's beak portion is not formed between the active area of the memory cell and the silicon substrate, a large black beak portion can be formed in the peripheral circuit portion, so the size can be reduced. Memory cell characteristics error. On the other hand, by forming a black beak on the peripheral circuit, it is possible to prevent the MOSFET from twisting and to suppress an increase in current consumption during standby. In addition, according to the invention disclosed in the sixth embodiment, since the inner wall of the STI is covered with an oxynitride film, it is possible to suppress the reduction of the film of the insulating film at the upper end of the element region when the tunnel oxide film is peeled off from the peripheral circuit portion. , Can prevent the distortion characteristics of MOSFEF, can suppress the increase in current consumption during standby. (Seventh Embodiment) The eighteenth through eighteenth through eighteenth through nineteenth through nineteenth through nineteenth nineteenth sections are sectional views showing a method for manufacturing a semiconductor memory device according to a seventh embodiment of the present invention. The semiconductor memory device (NOR-type fast-closing EEPROM) of this example has a device region that is insulated and separated by a buried element isolation region, and the gate oxide film thickness of the MOS transistor in the memory cell array region and the peripheral transistor region is different. First, as shown in FIG. 18A, after the impurities are introduced into the memory cell array region of the semiconductor silicon substrate 901, that is, the memory cell portion and the peripheral transistor region, that is, the peripheral circuit portion, the threshold value of the individual transistor reaches the individual desired value, and the memory is formed Gate oxide film 9 0 2 of tunnel oxide film of cell crystal is formed on substrate

O: \ 63 \ 63080.ptc Page 26 4528 Case No. 89103960 Amendment V. The description of the invention (23) is comprehensive, and a polycrystalline silicon film 9 0 3 is deposited thereon. A laminated film 904 of a CDV oxide film and a CVD oxide film. Next, a resistive pattern (not shown) is formed on the substrate, and the laminated film 904 is patterned with the resistive pattern, and then the resistive pattern is removed. Thereafter, as shown in FIG. 18B, the patterned laminated film 9 0 4 is masked, and the polycrystalline silicon film 9 0 3 corresponding to the predetermined portion forming the element separation region is removed. The gate oxide film 9 0 2 and the silicon substrate 9 0 are removed. 1. This forms shallow trenches. Second, after the memory cell array area is covered with a resistor (not shown), the surrounding transistor area is wet-etched (or isotropic dry-etched, or both), as shown in Figure 18C. A part of the gate oxide film 902 on the element region of the peripheral transistor region (the part on the end of the element region) is shaped to facilitate the supply of oxidant to the end of the element region. After that, the resistance is removed, and the oxidation in an atmosphere with a temperature of 900 to 100 degrees and an oxygen concentration of 10%, for example, causes the surface oxide film thickness of the channel to exceed 20 nm to form an oxide film 9 1 3. At this time, an oxidant is supplied to a part between the end of the device region of the peripheral transistor region and the polycrystalline silicon film 903 thereon to perform oxidation. Therefore, as shown in Fig. 18D, the so-called bird's beak portion is gradually thickened, and at the same time, the end portion of the element region has a circular shape. That is, the curvature of the edge of the element region of the peripheral transistor region becomes large. Next, as shown in FIG. 19A, for example, a buried insulator of the L P-T E 0 S film 9 05 is buried in the aforementioned channel. Thereafter, the entire surface is flattened by the CMP method or the back surface etching method, and the buried insulator is retracted in the middle of the main laminated film 904. Next, wet etching is performed to remove the laminated film 904. Secondly, as shown in FIG. 19B, a polycrystalline silicon film 906, which is implanted with radon as an impurity, is fully deposited on the substrate, and a resistance pattern (not shown) is formed thereon.

O: \ 63 \ 63O80.ptc Page 27 4 528;. _Case No. 89103960_January Cantonese Amendment _ V. Description of the invention (24) Use it to pattern the aforementioned polycrystalline evening film 9 0 6 In this way, a polycrystalline silicon film 906 that divides the memory cell array region on the element separation region is formed, and the polycrystalline silicon film 906 and 903 in the peripheral transistor region are removed. Thereafter, the aforementioned resistance pattern is peeled. Secondly, a 0 M 0 insulating film 9 0 8 is completely formed on the substrate. After covering the memory cell array region with a resistor (not shown), the 0 0 N 0 insulating film 9 0 8 and the gate oxide film are removed from the surrounding transistor region. (Tunnel oxide film) 902, and thereafter, the resistance covering the aforementioned memory cell array region is removed. In addition, when the slit 9 0 7 is formed in the memory cell array region, polycrystalline silicon films 9 0 6 and 9 3 in the peripheral transistor region may be left, and the above 0 Ν 0 insulating film 908 and the gate oxide film (tunnel) may be removed. (Oxide film) 902, the polycrystalline silicon films 906 and 903 are removed. Hereinafter, as in the case of the known person, as shown in FIG. 19C, a gate oxide film 909 of a transistor for peripheral circuits is formed, and further as shown in FIG. 19D taken in a direction orthogonal to FIG. 19C. As shown, a polycrystalline silicon film with impurities introduced is fully deposited on the substrate. In addition, in the memory cell array region, the polycrystalline silicon film, the aforementioned ΝΟΟ insulating film 9 0 8, the polycrystalline silicon films 9 0 6 and 9 0 3 are patterned, thereby controlling the gate 9 1 0 and the floating gate 9 1 1 (polycrystalline silicon film 9). The gate electrode 9 2 is formed by patterning a polycrystalline silicon film in a peripheral transistor region in a two-layer stacked gate structure of 0 6 and 9 0 3). Next, although not shown, the impurities constituting the source / drain of the transistor are selectively introduced into the surface layer of the substrate, and the interlayer insulating film is further deposited, the openings of the joints, the wiring is formed, and the surface protective insulating film is deposited. Flash EEPR0M. The enlarged view in Fig. 2A corresponds to the part indicated by the dotted line 0 in Fig. 19C

O: \ 63 \ 63080.ptc Page 28 4 52 8 Amendment No. 89103960 V. The end of (25) of the description of the invention (that is, the element area of the transistor region surrounding the gate oxide film after the element separation insulating film is formed An end) is an example of a shape, and the 20th B shows an example of the shape after the device in this part is enlarged. Among them, 901 series semiconductor substrate, 905 series element separation insulation film, 9.0 series gate oxide film, and 912 series gate electrode. As can be seen from Figures 20A and 20B, the gate oxide film 109 on the end of the element region has a black beak shape, so it is suppressed in the stripping step of the gate separation step. The reduced film makes it difficult to concentrate the electric field at the end of the element region. In addition, at the end of the device region in the peripheral transistor region shown in Figs. 20A and 20B, the gate electrode 1 12 formed on the gate oxide film 9 0 9 is sunk into a shape with a small amount of sunk, by the way. The measured results show that the difference between the height of the flat part of the aforementioned device region and the lowest part of the gate electrode above it is more than 4 nm. (Eighth embodiment) Figures 2 1 A-2 1 C to 2 2 A-2 2 D are sectional views showing a method of manufacturing a semiconductor memory device according to an eighth embodiment of the present invention in sections. First, as shown in FIG. 21A, after the impurity is introduced into the memory cell array region and the surrounding transistor region of the semiconductor silicon substrate 1001, after the threshold value of the individual transistor reaches a desired value, a tunnel of the memory cell transistor is formed. The gate oxide film 1002 of the oxide film is formed on the entire surface of the substrate, and a polycrystalline silicon film 1003, which is introduced with radon as an impurity, is deposited thereon. A laminated film 1004 of a CD V (chemical vapor deposition) oxide film and a CVD oxide film. Next, a resistive pattern (not shown) is formed on the substrate, and the laminated film 1004 is patterned using the resistive pattern, and then the resistive pattern is removed.

O: \ 63 \ 63080.ptc Page 29

Amendment S 2 8 3 4 _ Case No. 89103960 V. Description of the invention (26) Thereafter, as shown in Fig. 2 B, the patterned laminated film 1 0 0 4 is masked, and the predetermined portion corresponding to the element separation area is removed to form a predetermined portion. The polycrystalline silicon film 1 0 3, the gate oxide film 1 0 2 and the silicon substrate 1 0 1 form a shallow trench. Next, as shown in FIG. 21C, a buried insulating film of, for example, LP-TE 0 S (Low Pressure Terta-Ethyl-Oxide-Silicon) film 1 0 5 is buried. Within the aforementioned channel. Thereafter, the back surface is subjected to a CMP (Chemical Mechanical Polishing) method! The etch method is used to flatten the entire surface, so that the buried insulator is retracted halfway through the main laminated film 104. Subsequently, a wet etching process is performed to completely The laminated film 100 4 is removed. Next, as shown in FIG. 2A, a polycrystalline silicon film 1006 is deposited and introduced as an impurity on the entire surface of the substrate, and a resistance pattern (not shown) is formed thereon, and the foregoing is used to make the foregoing The polycrystalline silicon film 1 0 6 is patterned. At this time, a slit 1 0 7 is formed and the polycrystalline silicon film 1 0 6 of the memory cell array region is divided on the element separation region, and the polycrystalline silicon film 1 0 0 of the peripheral transistor region is removed. 6. 1 0 0 3. After that, the aforementioned resistance pattern is peeled off. Next, a 0N0 insulating film (oxide film / nitride film / oxide film laminated film) is formed on the substrate, and the memory cells are covered with a resistor (not shown). After the array region, the ON 0 insulating film 1 0 8 and the gate oxide film (tunnel oxide film) 1 0 2 of the surrounding transistor region are removed, and the resistance covering the aforementioned memory cell array region is removed. Sew 1 0 0 7 to memory cell In the array region, the polycrystalline silicon films 1006 and 1003 in the peripheral transistor region remain, and when the 0N0 insulating film 1 0 8 and the gate oxide film (tunnel oxide film) 1 0 2 are removed, the polycrystalline silicon film 1 0 0 is removed. 6. 10 0 3. At this stage, the corners of the end of the device region in the peripheral 'transistor region are exposed.

O: \ 63 \ 63080.ptc Page 30 4528 0 Case No. 89103960 Amendment V. Description of the Invention (27) Secondly, the memory cell array is covered with a resistor in the area, as shown in Figure 2 2B, and the wet etching processor ( Or isotropic dry etching treatment, or both treatments). The corners of the ends of the exposed element regions are thereby etched to form a pattern. Secondly, after removing the resistance of the area covering the memory cell array, as shown in FIG. 2C, the gate oxide film 1009 of the transistor for peripheral circuits is formed like the conventional one, further from the direction orthogonal to the 22C The 22D image taken shows that a polycrystalline silicon film with impurities introduced is fully deposited on the substrate. In addition, in the memory cell array region, the polycrystalline silicon film, the aforementioned 0 Ν 0 insulating film 1 0 8, the polycrystalline silicon film 1 0 6 and 1 0 0 3 are patterned to form a control gate 1 0 1 0 and a floating gate 1 0 1 1 (Polycrystalline silicon film 1 0 6 and 1 0 0 3 (to form a two-layer laminated gate structure, and the gate electrode 1 0 1 2 is patterned in the peripheral transistor region by patterning the aforementioned polycrystalline silicon film). Then, Although not shown, the source / drain material constituting the transistor is selectively introduced into the surface layer of the substrate, and the interlayer insulation film is further deposited, the openings of the connectors, the wiring is formed, and the surface protective insulation film is deposited. Flash EEPROM. Fig. 23 shows the end corresponding to the part indicated by the dashed line 0 in Fig. 2 C (ie, the end of the device region in the periphery of the transistor area after the gate insulation film is formed after the element separation insulating film is formed). One example of the shape. Among them, 1001 series semiconductor substrates, 105 series device isolation insulation films, and 1009 series gate oxide films. As can be seen from FIG. 23, since the end of the device region Or has a circular shape, so suppressing the component area that constitutes a conventional technical problem The electric field at the end of the field is concentrated. The conventional manufacturing of the seventh embodiment and the eighth embodiment will be briefly described.

O: \ 63 \ 63080.ptc Page 31 4 52 8 3 / '_ Case No. 89103960_year f month / day _ charm_ V. Description of the invention (28) The method, in the conventional manufacturing method, In the step of removing the gate oxide film and the tunnel oxide film before the gate oxide film in the crystal region, the corner of the end of the element region will be exposed. Therefore, in the conventional manufacturing method, when the peripheral circuit transistor is operated, an electric field concentration occurs at the corner of the end of the element region, the leakage of the peripheral circuit transistor increases, and the power consumption of the device increases. Threshold characteristics are discontinuous relative to the gate voltage, so peripheral circuits may malfunction by mistake, resulting in lower product yields. In contrast, the manufacturing method of the seventh embodiment and the eighth embodiment (1) performs wet etching treatment on the end of the device region of the peripheral transistor region, isotropic dry etching treatment, oxidation treatment, or a combination thereof, thereby Increasing the curvature of the end of the element region, or (2) forming a beak portion at the end of the element region in the step of forming the element in the periphery of the transistor region. Thereby, the end of the gate electrode element region can be suppressed from falling, the gate electrode does not cause electric field concentration at the end of the element region, the leakage of peripheral circuit transistors is suppressed, and the secondary threshold current characteristics of the peripheral circuit transistors are improved. Reduce the power consumption of products and improve the yield. In addition, for the method of rounding the corners of the exposed ends of the device region, it is generally known that if oxidation is performed at a regular rate of oxygen supply, the corners will be more easily oxidized than the flat parts. Therefore, instead of the processing in the foregoing embodiments, before the gate of the peripheral circuit transistor is formed, under high temperature and suppressed oxygen supply conditions, for example, at 100 ° C, nitrogen 90%, and oxygen 10% Under the conditions of oxidation, the corners of the exposed end of the device region can also be rounded. Even the oxidation method that makes the gate oxide film forming step of the peripheral circuit transistor itself have a regular supply rate can also be obtained.

O: \ 63 \ 63080.ptc Page 32 4 52 8 -s Case No. 89103960 Month / Year_Amendment V. Description of Invention (29) The same effect was obtained. And, of course, by combining these methods, the same effect can be obtained. In the case of separating the gate oxide film of the memory cell array region and the surrounding transistor, the corners of the ends of the element region insulated and separated by the buried element isolation region in the peripheral transistor region are rounded to suppress the gate electrode from The distortion characteristics of the peripheral circuit transistor formed by the component region across the component separation region are extremely active. The semiconductor memory device manufacturing method disclosed in the seventh embodiment and the eighth embodiment can be applied to forming a part of the gate insulating film before the element separation forming step, and forming the remaining part of the gate insulating film after the element separation forming step. Of semiconductor memory devices. By rounding the shape of the end of the element region, the leakage and power consumption of the region where the gate voltage of the transistor is low can be suppressed, and the sub-threshold current characteristic can be continuous with respect to the gate voltage, and the transistor operation in the field where the gate voltage is low is stable. To improve the product yield. Therefore, the seventh embodiment and the eighth embodiment are suitable for use in, for example, flash EEPROM and its manufacture. By setting the curvature of the end of the element region of the peripheral transistor region to be larger than the curvature of the end of the element region in the memory cell array region , Can reduce the leakage of peripheral circuit transistors, reducing power consumption. Although the above describes the present invention according to the embodiment, the present invention can be configured, for example, that the peripheral circuit section contains only the extracted circuit of the memory cell section, further including the CPU, etc. The above embodiments take flash EEPROM as an example for illustration, but The present invention is not limited thereto, and may be variously modified without departing from the spirit of the invention.

O: \ 63 \ 63080.pic Page 33

Claims (1)

4 52 8 Case No. 89103960 '^ month > > Amendment VI. Patent application scope 1. A non-volatile semiconductor memory device characterized by having: a semiconductor substrate; a plurality of memory cells formed on the semiconductor substrate; A cell; a circuit for controlling the aforementioned memory cell with a floating gate, and a peripheral circuit part located on the semiconductor substrate; a region of a plurality of elements separately formed on the memory cell and the peripheral circuit part by a plurality of channels; buried An insulating film of the aforementioned channel; a beak-shaped oxide film formed between the element region of the memory cell portion and the floating gate electrode; and '' formed between the element region of the peripheral circuit portion and the gate electrode, The component region of the aforementioned memory cell and the bird's beak-shaped oxide film of the floating gate electrode gate have a thicker bird's beak-shaped oxide film. 2. A non-volatile semiconductor memory device, comprising: a semiconductor substrate; a circuit for controlling the memory cell, and a peripheral circuit portion located on the semiconductor substrate; formed on the memory cell portion and the peripheral circuit portion, respectively; A plurality of element regions separated by a plurality of channels; an oxidation-resistant film formed on an inner wall of the aforementioned channel and a side wall of the floating gate electrode in the aforementioned memory cell; an insulating film which buryes the aforementioned channel; a element formed on the aforementioned memory cell Gate between the area and the aforementioned floating gate electrode O: \ 63 \ 63080.ptc Page 1 2001.06. 22. 035 45283; _Case No. 89103960_ ^ Month > "Amendment__ VI. Patent application scope. Extreme insulation film; and components formed in the aforementioned peripheral circuit section Gate insulation film for area and gate electrode gates. 3. The non-volatile semiconductor memory device according to item 2 of the application, wherein the aforementioned oxidation-resistant film is a silicon nitride film. 4. A non-volatile semiconductor memory device, comprising: a semiconductor substrate having a plurality of memory cells formed on the semiconductor substrate; and a peripheral circuit portion controlling the memory cells on the semiconductor substrate; * Multiple element regions formed in the aforementioned memory cell section and peripheral circuit sections separated by a plurality of channels; only an oxidizing film formed on the sidewall of the aforementioned channel and the sidewall of the floating gate electrode in the aforementioned memory cell section; A channel insulating film; a gate insulating film formed between the element region of the memory cell portion and the floating gate electrode; and a gate insulating film formed between the element region of the peripheral circuit portion and the gate electrode. 5. The non-volatile semiconductor memory device according to item 4 of the patent application > wherein the aforementioned oxidation-resistant film is a silicon nitride film. 6. A non-volatile semiconductor memory device, comprising: a semiconductor substrate; O: \ 63 \ 63080.ptc Page 2 2001.06. 22. 036 452834 _ case number 89103960_ office year June June ___ 6, the scope of the application for a patent formed a plurality of memory cells, located on the aforementioned semiconductor substrate memory cells; Forming a circuit for controlling the memory cell, and a peripheral circuit part located on the semiconductor substrate; and forming an insulating film for the channel by burying the channel area separately from the memory cell part and the peripheral circuit part; An oxynitride film between the element region of the memory cell portion and the floating gate electrode; and an oxide film formed on the element region of the peripheral circuit portion and the gate electrode. * 7. A nonvolatile semiconductor memory device, comprising: a semiconductor substrate; a plurality of memory cells formed on the semiconductor substrate; and a circuit for controlling the memory cells formed on the semiconductor substrate. A peripheral circuit portion on the top; a plurality of device regions formed in the memory cell portion and the peripheral circuit portion separately by a plurality of channels; an oxidation-resistant film formed at least on an inner wall of the channel in the peripheral circuit; An insulating film; a gate insulating film formed between the element region of the aforementioned memory cell portion and the floating gate electrode; and O: \ 63 \ 63080.ptc Page 3 2001.06. 22. 037 45283,,, 7 _Case No. 1Q3960_V Jun ._ ^ __ VI. The scope of patent application is formed in the component area and gate of the peripheral circuit Gate insulation film between electrodes "8. The non-volatile semiconductor memory device according to item 7 of the application, wherein the aforementioned oxidizing film is an oxynitride film. 9. The non-volatile semiconductor memory device according to item 7 of the application, further comprising an oxidizing film formed on the inner wall of the channel and the side wall of the floating gate in the memory cell. 10. The non-volatile semiconductor memory device according to item 9 of the scope of patent application, wherein the oxidation-resistant film is an oxynitride film formed on the inner wall of the channel and the side wall of the floating gate in the memory cell. 1 1. A non-volatile semiconductor memory device, comprising: a semiconductor substrate; and a memory cell array section, wherein a plurality of memory cell crystals are formed in a device region of the semiconductor substrate ^ a device region of the memory cell crystal It is opposite to the gate electrode of the memory cell transistor, and is insulated and separated by the embedded component separation area; the peripheral transistor part, which has a plurality of peripheral circuit transistors formed on the element area of the semiconductor substrate, and describes the peripheral circuit The element region of the transistor is opposite to the gate electrode of the transistor of the peripheral circuit, and is insulated and separated by the embedded element isolation region; the curvature of the element isolation end of the element region of the peripheral circuit transistor is set to be substantially higher than the aforementioned memory cell. The element separation portion of the transistor element has a large curvature. 1 2. If the non-volatile semiconductor memory device of item 11 of the patent application scope O: \ 63 \ 6308O.ptc Page 4 2001.06. 22. 038 4 5 2 8 _ Case No. 89103960_ Such as the year and month W. ___ 6, the scope of the patent application, where the height of the flat part of the aforementioned element area and The difference in height between the lowest portion of the gate electrode located relatively above is 4 nm or more. 1 3. The non-volatile semiconductor memory device according to item 11 of the scope of patent application, wherein when the operation of the peripheral circuit transistor is in a standby state, the peripheral circuit transistor is given a bias potential that causes a sub-threshold current to move. 14. The non-volatile semiconductor memory device according to item 11 of the scope of patent application, wherein the gate electrode portion of the memory cell transistor is aligned with the lead-out area of the embedded element in the memory cell array portion. 1 5. The non-volatile semiconductor memory device according to item 11 of the scope of patent application, wherein the aforementioned memory cell crystal system is provided with a memory cell of the non-volatile semiconductor memory of the floating gate. '· 16. — A method for manufacturing a non-volatile semiconductor memory device, which is formed by separating a device region by a channel-type element, and is provided with a non-volatile semiconductor memory in a memory cell portion having a floating gate and a peripheral circuit portion thereof. The device manufacturing method is characterized by having the steps of: forming a polycrystalline silicon layer on a silicon substrate through an insulating film; in order to form an element region, the polycrystalline silicon layer, the insulating film, and the silicon substrate are self-alignedly etched, and a bottom is formed in the silicon substrate, The step of separating the plurality of channels around the device region; oxidizing the individual ends of the device separation side of the device region facing the polycrystalline silicon layer to perform rounding; and covering the memory cell only with an oxidation-resistant film Steps; and-after covering the memory cell portion with an oxidation-resistant film, additional oxidation is performed, in the device region of the peripheral circuit portion, at the end of the silicon substrate and the polycrystalline silicon layer facing the opposite side O: \ 63 \ 63080.ptc Page 5 2001.06.22. 039 45283. _Case No. 891Q3960_Yan Yueyue _ ^ __ VI. Between patent application areas, a thick beak-shaped oxide film is formed which is thicker than the memory cell area. The steps. 1 7. The method for manufacturing a nonvolatile semiconductor memory device according to item 16 of the scope of patent application, wherein the aforementioned oxidation-resistant film is a silicon nitride film. 1 8. The method for manufacturing a nonvolatile semiconductor memory device according to item 16 of the scope of patent application, wherein the oxidation-resistant film covering the memory cell portion is removed after performing the aforementioned additional oxidation treatment. 1 9. A method for manufacturing a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device having a memory cell portion provided with a floating gate and a peripheral circuit portion formed by forming a device region by channel-type element separation. The manufacturing method is characterized by: a step of forming a polycrystalline silicon layer on a silicon substrate through an insulating film; in order to form an element region, the polycrystalline silicon layer, the insulating film, and the silicon substrate are etched in a self-aligned manner, and a bottom is formed in the silicon substrate to surround the element A step of using multiple channels for element separation in a region; a step of rounding by oxidizing individual end portions of the device region and a polycrystalline silicon layer facing each other; a step of covering only a memory cell portion with an oxidation-resistant film; The step of selectively removing the oxidation resistant film from the memory cell, and leaving the oxidation resistant film only on the side wall of the floating gate electrode and the element and the side wall of the separation channel; and after selectively removing the oxidation resistant film, additional oxidation is performed, In the component area of the peripheral circuit portion, a thick beak thicker than the memory cell portion is formed between the opposite ends of the silicon substrate polycrystalline silicon layer. Of the oxide film. 2 0. Non-volatile semiconductor memory device as claimed in item 19 O: \ 63 \ 63080.ptc 2001.06.22. 040 Page 6 4 52 8 Dagger_Case No. 89103960_June June > 7 ______ 6. Manufacturing method in the scope of patent application, in which the aforementioned oxidation resistant film Is a silicon nitride film. 2 1. The method for manufacturing a nonvolatile semiconductor memory device according to item 16 of the patent application scope, wherein the oxidation-resistant film covering the memory cell portion is removed after the aforementioned additional oxidation treatment is performed. 2 2. —A method for manufacturing a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device having a memory cell portion provided with a floating gate and a peripheral circuit portion formed by forming a device region by channel-type element separation. The manufacturing method is characterized by: a step of forming a polycrystalline silicon layer on a silicon substrate through an insulating film; a step of etching the polycrystalline silicon layer of the peripheral circuit portion, the insulating film, and the silicon substrate only by self-alignment to form a first element separation channel; · Steps of oxidizing each end of the component area in the peripheral circuit section facing the first polycrystalline silicon layer to form a bird's beak-shaped oxide film; self-aligningly etch the polycrystalline silicon layer, insulating film, and silicon substrate of the memory cell to form A step of forming a second device isolation channel; and after the second device isolation channel is formed, oxidizing respective end portions of the element region of the memory cell portion and the polycrystalline silicon layer facing each other to form a darker layer than the peripheral circuit portion Step of thinner beak-shaped oxide film β 2 3. —A method for manufacturing a non-volatile semiconductor memory device by using a channel element A method for manufacturing a non-volatile semiconductor memory device having a memory cell portion and a peripheral circuit portion provided with a floating gate separately formed in an element region, comprising: a step of forming an oxidation-resistant film on a silicon substrate through an insulating film; A step of selectively removing the oxidation-resistant film and the insulating film of the memory cell; O: \ 63 \ 63080.ptc 2001.06.22. 041 Page 7 4 ^ 283 Case No. 89103960 Amendment 6. The scope of the patent application is to form a tunnel oxide film on the memory cell, nitriding it, and make the tunnel oxide film oxygen nitrogen film Steps of forming; forming a polycrystalline silicon layer on the upper part of the tunnel oxynitride film of the memory cell part and the upper part of the oxidation resistance film of the peripheral circuit part; self-integrated etching of the polycrystalline silicon layer and the silicon substrate, and the memory cell part and the peripheral circuit Forming a trench for element separation; and forming a bird's beak-shaped oxide film on the end of each surface of the element region facing the polycrystalline silicon by oxidizing after forming the trench for element separation, forming a memory cell portion in the peripheral circuit portion Step of thick beak-shaped oxide film. 2 4. —A method for manufacturing a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device having a memory cell portion provided with a floating gate and a peripheral circuit portion formed by forming a device region by channel-type element separation. The manufacturing method is characterized by: a step of forming a polycrystalline silicon layer on a silicon substrate through an insulating film; a step of self-aligning etching the polycrystalline silicon layer and the silicon substrate to form a channel region for element separation to form an element region; and by oxidation, The steps of rounding the device area and the ends of the polycrystalline silicon on each side; the step of covering the memory cell portion with a silicon film; adding the oxidation after the silicon film coating, the silicon substrate on the peripheral circuit portion and the polycrystalline silicon layer facing the opposite side A step of forming a black beak-shaped oxide film thicker than the memory cell between the ends; and a step of forming an oxide film of a silicon film covering the memory cell. 25. Non-volatile semiconductor memory device as claimed in item 24 0: \ 63 \ 630S0, ptc Page 8 2001.06.22. 042 45283 _Case No. 89103960_Year Month > 7 ______ 6. Manufacturing method in the scope of patent application, in which only the silicon film of the aforementioned memory cell is covered Department of amorphous film. 2 6. —A method for manufacturing a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device having a memory cell portion provided with a floating gate and a peripheral circuit portion formed by forming a device region by channel-type element separation. The manufacturing method is characterized by: a step of forming an insulating film on a silicon substrate and a polycrystalline silicon layer constituting a floating gate; a step of self-aligning etching the polycrystalline silicon and the silicon substrate to form a channel for element separation; and an inner wall of the channel And a step of forming a silicon oxynitride film on the polycrystalline silicon sidewall. 27. The method for manufacturing a nonvolatile semiconductor memory device according to item 26 of the patent application, wherein the step of forming a silicon oxynitride film on the inner wall of the channel and the side wall of the polycrystalline silicon layer is to form a silicon oxide film on the inner wall of the channel and A step of forming an oxynitride film by applying an oxynitriding treatment to the sidewall of the polycrystalline silicon layer. 2 8. A method for manufacturing a nonvolatile semiconductor memory device, characterized in that a part of a gate insulating film of a MOS transistor is formed before the element separation step, and a part of the foregoing gate insulating film is formed after the element separation forming step When manufacturing the remaining non-volatile semiconductor memory device, a MOS transistor is formed so that the curvature of the end of the element region of the MOS transistor having the gate insulating film formed after the aforementioned element separation and formation step is more practical than that of the aforementioned element. The edge of the element region of the MOS transistor of the gate insulating film formed before the separation forming step has a large curvature. 2 9. —A method for manufacturing a non-volatile semiconductor memory device O: \ 63 \ 63080.ptc Page 9 2001.06. 22. 22. 043 4 5283 d ~ ι ^ _ 'Case No. 89103960_minutes? June > a _ ^ __ VI. The scope of the patent application is formed by the separation of channel-type elements A method for manufacturing a non-volatile semiconductor memory device including a memory cell portion of a floating gate and a peripheral circuit portion of the device region, comprising: forming a first gate insulating film for a memory cell transistor on the entire semiconductor substrate; A step of forming a polycrystalline silicon film and an insulating film thereon; a step of forming a channel for forming an element separation region on the aforementioned insulating film, the polycrystalline silicon film, the first gate insulating film, and the semiconductor substrate; and after covering the aforementioned memory cell array region, A step of removing the first gate insulating film on the end portion of the device region in the peripheral transistor area; oxidizing the surface of the aforementioned channel surface and a portion between the end portion of the device region in the peripheral transistor region and the polycrystalline silicon film thereon Steps: a step of embedding a buried insulator in the aforementioned channel to completely flatten it; a step of removing the insulating film on the aforementioned polycrystalline silicon film; a step of removing the aforementioned peripheral transistor field A step of forming a second gate insulating film for a peripheral circuit transistor after the crystalline silicon film and the first open-electrode insulating film; forming a stacked gate structure including the polycrystalline silicon film as a floating gate in the memory cell array region; A step of forming a gate electrode on the second gate insulating film in the peripheral transistor region; and a step of selectively introducing impurities constituting the source / drain of the transistor into the surface layer portion of the substrate. 3 0. — A method for manufacturing a non-volatile semiconductor memory device, which is a non-volatile semiconductor memory device having a memory cell portion provided with a floating gate and a peripheral circuit portion formed by forming a device region by channel-type element separation. The manufacturing method is characterized by: O: \ 63 \ 63080.ptc Page 10, 2001.06.22.044 A ^ 〇r > r… j heart_ case number 89103960_year month > V ______ Sixth, apply for a patent scope to form the first The step of forming the gate insulating film on the entire semiconductor substrate and forming a polycrystalline silicon film thereon; the step of forming a channel for forming an element separation region on the aforementioned polycrystalline silicon film, the first gate insulating film, and the semiconductor substrate; and embedding the buried insulator in The steps of flattening the aforementioned channel in an all-round way; the step of forming a floating gate of the memory cell crystal and controlling the inter-gate insulating film for inter-gate insulation on the substrate; A step of exposing the device region by the polycrystalline silicon film and the first gate insulating film; a step of removing the corners of the end of the device region exposed at the aforementioned peripheral transistor region so as to have a circular shape; The step of forming the second gate insulating film for the aforementioned peripheral circuit transistor in the crystal field; forming a stacked gate structure with the aforementioned polycrystalline silicon film as a floating gate in the aforementioned memory cell array field; Transistor region in the second gate insulating film formation step of the gate electrode; and a transistor constituting a source of the source / drain impurity is selectively introduced into the step of a surface layer portion of the substrate. O: \ 63 \ 63080.ptc Page 11 2001.06. 22. 045