KR100479834B1 - Flash memory fabrication method - Google Patents

Abstract

A flash memory manufacturing method comprising a cell region / peripheral region ISO process, a gate poly formation process, and a cell region source / drain ion implantation process, wherein the ISO process is a cell region trench target and a cell region and a peripheral region. Trenching all, and opening only the peripheral area with the peripheral area ISO mask to further etch the peripheral area trench target to form a peripheral area trench, wherein the gate poly formation process deposits a nitride film on the gate poly layer. By using a barrier layer during oxidation of the gate poly, and the cell region source / drain ion implantation process includes depositing and etching an insulator to form cell region spacers before ion implantation. The present invention relates to a flash memory manufacturing method. The above ISO process can be implemented in other ways.

Description

Flash memory fabrication method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to flash memory in the semiconductor field, and more particularly, to a structure improvement and a process of a flash memory cell.

1 to 3 are diagrams each showing a conventional flash memory manufacturing process step by step. These processes are well known to those skilled in the semiconductor manufacturing arts. Each figure shows each memory component and process step in English letters, and representative terms used in the present specification are as follows.

Arsenic (arsenic), BOE dip (Buffer oxide echant dipping), BPSG (Boron-phosphor Silicate glass), Cell (cell area), CLN (cleaning), CMP (Chemical-mechanical polishing), DDD (Double Diffused Drain), Densification (Densification process), Dep (deposition), HTO (High temperature oxidation), HVN (High voltage NMOS), HVP (High voltage PMOS), IMP or Implantation (ion implantation), IPO (inter-poly oxide), ISO (Isolation (Separation), LDD (Lightly Doped Drain), Liner (Liner), LVN (Low Voltage NMOS), LVP (Low Voltage PMOS), MK (Masking), Nitride (Nitride), ONO (Oxide-Nitride-Oxide layer) ), Oxidation (oxide formation), Oxide (oxide), P / R (photoresist), Periphery (peripheral), SAC (Sacrificial), Salicide (Self-aligned silicide), SAS (Self-aligned source), Strip (Removed), Sub (substrate), THVN (Triple well high voltage NMOS)

In Figs. 1A to E, conventionally, a shallow trench isolation (STI) method is used to manufacture a flash memory. In this method, a pad oxide layer 17 and a pad nitride layer 15 are formed on a P-sub substrate (P-Sub) as a whole, followed by a cell region 11 and a peripheral region. ) 13 is formed using a separate mask process. On the right side of each drawing of FIGS. 1A-E, the order of processes is displayed in order. Indeed, the STI method shown in FIGS. 1A-E is well known to those skilled in the art.

However, according to the STI method shown in Figs. 1A to E, in order to reduce the resistance of the source line (19 in Fig. 1E) of the memory chip cell, the STIs of the cell region 11 and the peripheral region 13 are used by using respective masks. As shown in FIG. 1C, a problem arises in that the overlap region “d” is reduced or enlarged to a desired size due to misalignment of the cell region ISO mask 19 and the peripheral region ISO mask 18. The characteristics may vary, and even if the area is not used, this unnecessary portion increases the chip size. Also, in case of mask process after separation process, if you need to align with ISO alignment key, if you align with the peripheral ISO mask, the misalignment can be severely on the cell side. It is likely to be severe.

On the other hand, Figures 2a to e introduce a process for forming a conventional poly-crystalline amorphous silicon (a-Si) gate (hereinafter, abbreviated as "gate poly"). This process is well known to those skilled in the semiconductor manufacturing field. In this method, since the oxidized portion occurs in the oxidation process in Figs. 2C and 2D (which causes damage to the ONO film), it must be removed by BOE dip as in Fig. 2E.

However, removing the oxidized portion of the amorphous silicon (a-Si) is an unstable process, and if it is not removed, a defect in which the bias is not transferred to the gate of the cell occurs. In other words, the removal of the oxidized portion is a difficult process, which is a factor that reduces the yield of the wafer during product production.

3A and 3B show a process of forming S / D (source / drain) of a conventional memory cell. Conventionally, after forming the stacked gate of the cell as shown in Fig. 3a, it is formed by ion implantation (IMP) immediately. As a result, as shown in Fig. 3b, the arsenic 31 is trapped on the sides of the ONO film and the tunnel oxide film. Or arsenic ions damage the crystal lattice, causing electrons stored in the gate poly to escape. This is called a "Data Retention Problem." Data retention problem is the most important item among the reliability of flash memory cells. For reference, arsenic (As) as a dopant is more damaging to the crystal lattice because the mass is larger than other dopants.

In order to solve the problems of FIGS. 1A through E, after trenching both the cell region and the peripheral region with the cell region trench target, only the peripheral region is opened with the mask for separating the peripheral region, and the peripheral region is formed by using a hard mask made of oxide film or a nitride layer as a blocking layer. To further etch the trench target and to solve the problems of FIGS. 2A through E, a nitride film is deposited on poly (a-Si / amorphous silicon) to prevent a-Si from being oxidized during oxidation, and the problems of FIGS. 3A and B. In order to solve the problem, the present inventors have devised an improved method for manufacturing a flash memory under the idea of depositing a cell spacer nitride film and then performing spacer etching to protect the ONO film and the tunnel oxide film during cell S / D ion implantation.

According to a first aspect of the present invention, in a flash memory manufacturing method including a cell region / peripheral region ISO process, a gate poly formation process, and a cell region source / drain ion implantation process, the ISO process is a cell region trench target. Trenching both the cell region and the peripheral region, and forming only the peripheral region trench by opening only the peripheral region with the peripheral region ISO mask to further etch the peripheral region trench target. Depositing a nitride film on the layer to use as a blocking layer during oxidation of the gate poly, and the cell region source / drain ion implantation process includes depositing and etching an insulator to form cell region spacers before ion implantation. Steps are included.

According to a second aspect of the present invention, there is provided a flash memory manufacturing method including a cell region / peripheral region ISO process, a gate poly formation process, and a cell region source / drain ion implantation process.

The ISO process may include forming a pad oxide film and a pad nitride film to form an ISO, followed by trenching in accordance with the peripheral area ISO, filling the polysilicon (a-Si), and then oxidizing the filled polysilicon.

The gate poly formation process includes depositing a nitride film on the gate poly layer to use the blocking layer when the gate poly is oxidized.

The cell region source / drain ion implantation process includes depositing and etching an insulator to form cell region spacers prior to ion implantation.

Hereinafter, an embodiment of a flash memory manufacturing method according to the present invention will be described. 4A to ED are diagrams sequentially showing processes of a flash memory manufacturing method according to the present invention. This figure illustrates the entire flash memory manufacturing process from the beginning to the end of the present invention will be described in detail centering on the process corresponding to the present invention.

Solving the Problems Addressed in Figures 1a-e

4A to 4A illustrate an ISO (isolation) process. In the conventional STI, the cell region and the peripheral region are formed by using a separate mask process (see FIGS. 1A to E). The hard mask 41 is formed as a whole on the pad nitride film 15 (see Fig. 4aa), and both cell and peripheral regions are trenched (see Fig. 4ab). In FIG. 4ab, it can be seen that the depth of the cell region trench and the depth of the peripheral region trench are the same (compare with FIG. 1b).

After the trench processing of the cell region and the peripheral region, the cell region is blocked by the peripheral region separation mask 43, and only the peripheral region is opened, and the trench target of the peripheral region is formed using the hard mask 41 of the oxide film, the nitride film, or the polysilicon as a blocking layer. The trench is further etched to form trenches (see FIG. 4ac, where the trench depth in the peripheral region is deeper by etching than in FIG. 4ab).

By doing so, the problem mentioned in Figs. 1A to E, that is, the cell area ISO mask 19 and the peripheral area ISO mask 18 are formed separately, so that the overlap area ("d") becomes smaller than the desired size due to misalignment of the mask. Or increasing problems can be solved.

The rest of the process is the same as the conventional process. That is, FIGS. 4A to 4A show a process of filling a dielectric in a trench, and FIGS. 4A and 4B show a process of forming a well and a channel. Since such a conventional process is obvious to those skilled in the art, a detailed description thereof will be omitted.

Solution of the problem mentioned in Figures 2a-e

4ca to cf illustrate gate forming processes of the cell region and the peripheral region. Conventionally, after forming the gate poly layer, the BOE dip method was used to remove the surface oxidized with amorphous silicon (a-Si) (see FIG. 2E). However, in the present invention, as shown in FIG. 4C, the gate poly layer 44 is used. By depositing the nitride film 45 thereon, a-Si is prevented from being oxidized together in the oxidation process for forming the gate.

The remaining processes FIGS. 4cc to cf illustrate a process for processing the gate poly layer 44 covered by the nitride film 45 to form a gate electrode in a desired shape at a desired position. This is a process that is apparent to those skilled in the art. The completed gate electrode can be seen in FIG. 4cf.

Solution of the problem mentioned in Figures 3a, b

4D and 5B show an ion implantation process for forming a source electrode and a drain electrode. In the conventional process shown in Fig. 3A, the source and the drain are formed by ion implantation (IMP) immediately after the stacked gate of the cell region is formed. In the present invention, spacer etching is performed after the deposition of the cell region spacer nitride film. This protects the ONO film and the tunnel oxide film during ion implantation of the cell region S / D.

That is, unlike in the case of FIG. 3A, as shown in FIG. 4D, before the cell region S / D ion implantation, the cell region spacer nitride film is deposited and etched to form the spacer 47, and then ion implantation is performed to perform the cell region S / D ion implantation. D It prevents the damage of ONO and tunnel oxide which occurred during ion implantation. The spacers 47 and 48 may be formed from not only nitrides, but also oxides or polycrystalline silicon.

4db shows a peripheral region spacer 48 formed before the peripheral region S / D ion implantation. The remaining drawings, Figure 4ea ~ ed shows a metallization (passivation) process, the same process as known in the prior art and is obvious to those of ordinary skill in the art to which the present invention belongs Description is omitted.

Other Modified Embodiments

5A to 5G are process drawings showing another embodiment for solving the problems (mask misalignment problem in the ISO process of reducing the resistance of the cell region source) mentioned in Figs. 1A to E described above (in FIGS. 4A to AE). to be.

According to the present embodiment, first, in the ISO (isolation) process for forming the N-junction, as in the conventional method or the present invention, a pad oxide film and a pad nitride film are formed to form ISO, but the cell area ISO and the peripheral area ISO are separated separately. After forming the trench according to the surrounding area ISO as shown in Fig. 5b, the polycrystalline silicon (a-Si) poly-51 of P type is filled (see Fig. 5b), and the upper P-type poly is then subjected to the ISO poly oxidation process. By oxidation, isolation is formed as shown in Fig. 5D.

In the next process, as shown in FIG. 5E, an oxide film is removed by etching using a SAS (self-aligned source) mask 53 to form a source line, and ion implantation is performed on the poly 51 filled in the N-junction process. Resistance can be reduced.

According to the present embodiment, a source line is formed by connecting source terminals using poly doped by ion implantation of the cell region S / D, thereby reducing the source resistance while reducing the source resistance. The mask misalignment problem can be overcome when separately.

As described above, according to the present invention, unlike the FIGS. 1A through E, the overlap region is reduced or increased from the desired size due to misalignment of the cell region ISO mask and the peripheral region ISO mask, and the characteristics of the transistors are changed and the region is different. Unnecessary increase in chip size due to avoiding use can be suppressed, and excessive misalignment to either the cell region or the peripheral region can be prevented during the subsequent mask process by using two conventional ISO masks. In addition, unlike the conventional method using the ISO mask of the cell region and the peripheral region as a critical layer, according to the present invention, since the peripheral ISO mask can be used as a non-critical layer, the mask process cost can be reduced.

In addition, in the problems mentioned in FIGS. 2A through E, by depositing a nitride film on the gate poly (a-Si), it is possible to prevent the oxidation of a-Si during oxidation, so that the oxidized material must be removed by BOE dip as in the conventional method. There is no need to use an uneasy process. Therefore, it is possible to prevent a factor that lowers the yield of the wafer during production.

In addition, for the problems mentioned in FIGS. 3A and 3B, the spacer etching is performed after deposition of the nitride film for the cell region spacer, thereby protecting the ONO film and the tunnel oxide film during the cell region S / D ion implantation, thereby arsenicing the side surfaces of the ONO film and the tunnel oxide film. By preventing ions As from being trapped or damaging the lattice, it is possible to solve the problem of "data preservation" in which electrons stored in the first poly escape.

1 is a process chart showing a conventional trench isolation method for reducing source resistance.

Figure 2 is a conventional polycrystalline (Cover Poly) structure diagram for preventing ONO film damage

3 is a schematic diagram showing a conventional situation of implanting ions into a cell S / D for data preservation.

Figure 4 is a flow diagram of a flash memory manufacturing process of the present invention.

5 is another embodiment of the present invention, an ISO formation diagram for reducing the cell source resistance

<Description of Drawing>

Pad oxide film 17, Pad nitride film 15, Cell region 11, Peripheral region 13, Cell region ISO mask 19, Peripheral region ISO mask 18, Arsenic ion 31, Hard mask 41 ), Peripheral region separation mask 43, gate poly layer 44, nitride film 45, cell region spacer 47, peripheral region spacer 48, polysilicon (poly) 51, SAS mask 53 ), Source Line (55)

Claims (9)

In the flash memory manufacturing method including an ISO process, a gate poly forming process, a source line forming process, The ISO process, Trenching both the cell region and the surrounding region with the cell region trench target; Additionally forming a peripheral region trench by opening only the peripheral region with a peripheral region ISO mask to further etch the peripheral region trench target so that the trench depth of the peripheral region is deeper than the trench depth of the cell region, The gate poly forming process Depositing a nitride film on the gate poly layer and using the barrier layer when the gate poly is oxidized; The source line forming process Depositing and etching an insulator to form cell region spacers prior to ion implantation. delete delete The method of claim 1, wherein the peripheral area ISO mask of the peripheral area trench forming step is a hard mask. The method of claim 4, wherein the hard mask is selected from an oxide series, a nitride series, and a polysilicon series. The method of claim 1, wherein the insulator of the cell region spacer is selected from a nitride film series, an oxide film series, and a polysilicon series. In the flash memory manufacturing method including an ISO process, a gate poly forming process, a source line forming process, The ISO process, Forming a pad oxide film and a pad nitride film to form an ISO, and trenches in accordance with the peripheral area ISO, and then filling the polysilicon (a-Si) and then oxidizing the filled polysilicon, The gate poly forming process Depositing a nitride film on the gate poly layer and using the barrier layer when the gate poly is oxidized; The source line forming process A method of manufacturing a flash memory, comprising the steps of: removing an oxide film by etching using a self-aligned source (SAS) mask; and implanting ions into the polysilicon filled in the ISO process. The method of claim 7, wherein the peripheral area ISO mask of the peripheral area trench forming step is a hard mask. The method of claim 8, wherein the hard mask is selected from an oxide series, a nitride series, and a polysilicon series.