KR100761393B1 - Method for forming gapfill test pattern for isolation of flash memory device - Google Patents

Abstract

The present invention is to provide a method of forming a gap fill margin test pattern that can proceed the gap fill margin test by forming a pattern that can adjust the gap while maintaining the pitch as needed, the method of forming a gap fill margin test pattern of the present invention Preparing a first reticle having a normal test pattern having the same pitch as the real cell pattern and having a different CD size; Preparing a second reticle having an arbitrary test pattern having the same pitch as that of the real cell pattern and having a different CD size; And offsetting the arbitrary test pattern to expose the normal test pattern in a double exposure form to form a test pattern in which the normal test pattern and the arbitrary test pattern overlap each other. As such, the active region and the field oxide film are most useful when the straight pattern is used. Since the CD can be appropriately adjusted to perform the gap fill test, various gap fill tests can be performed.

Gap Fill Test Pattern, Flash Memory Device, Reticle, Exposure

Description

Gap Fill Test Pattern Formation Method for Device Separation of Flash Devices {METHOD FOR FORMING GAPFILL TEST PATTERN FOR ISOLATION OF FLASH MEMORY DEVICE}

1 is a layout of a test pattern having a constant active area size and a different space formed for a gap fill margin test according to the prior art;

2 is a layout of test patterns for various shapes having a constant active area and a field oxide film size formed for a gap fill margin test according to the prior art;

3 is a layout of a test pattern in a scribe lane having the same pitch as a real cell and different CD sizes according to an embodiment of the present invention;

4 is a layout of a test pattern outside a frame having the same pitch as a real cell and different CD sizes according to an embodiment of the present invention;

5 is a view illustrating a state in which the test patterns of FIG. 3 and FIG. 4 are superimposed and offset;

6 is a detailed view of FIG. 5;

FIG. 7 is a view schematically illustrating a device isolation method using a mask on which a final test pattern of FIG. 5 is formed.

* Explanation of symbols for main parts of the drawings

100: first reticle 102: normal test pattern

200: second reticle 202: arbitrary test pattern

300: final test pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a gap fill test pattern for a gap fill margin test of a field oxide film.

As the degree of integration of semiconductor devices increases, the ISO cell pitch continues to decrease. However, as the field oxide gap fill margin does not quickly respond to the decrease in pitch, the gap fill margin issue of the field oxide layer is increasing.

In order to test this, a test or a test pattern is generally inserted in a real cell, and the inserted test pattern is a pattern that does not accurately reflect the real cell.

The current gap fill test pattern is shown in FIG. 1.

1 is a layout of a test pattern having a constant active area size and a different space formed for the gap fill margin test according to the prior art, and FIG. 2 shows an active area formed for the gap fill margin test according to the prior art. It is a layout of test patterns for various shapes having a constant field oxide film size.

As shown in FIG. 1, a plurality of active regions 11 in the form of a line L having a predetermined line width CD are defined, and the line line widths L of each active region 11 are all constant. In addition, the spacings Space and S between neighboring active regions 11 become smaller as disposed in one direction. Here, the interval between the adjacent active regions 11 is a field oxide film.

In the above-mentioned prior art, the line fill width L of the active region 11 and the line width S of the field oxide film are kept constant, and the gap fill margin in each pattern is checked by CD-SEM. Since there is not a pattern having a constant pitch like a pattern and there is one pattern for each interval or a cell pattern having a predetermined interval is fixed in advance as shown in FIG. 2, there is no method of actually changing the pattern.

Referring to FIG. 2, the A-type cell pattern is 100/100 L / S (Line / Space), the B-type cell pattern is 100/95 L / S, and the C-type cell pattern is 100/95 L / S. 90, and the D-type cell pattern is 100/85 L / S.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and provides a method of forming a gap fill margin test pattern that can proceed with gap fill margin test by forming a pattern capable of adjusting the gap while maintaining a pitch as necessary. Its purpose is to.

Method for forming a gap fill margin test pattern of the present invention for achieving the above object comprises the steps of preparing a first reticle having a normal test pattern of the same pitch as the real cell pattern and different CD size; Preparing a second reticle having an arbitrary test pattern having the same pitch as that of the real cell pattern and having a different CD size; And offsetting the arbitrary test pattern to expose the normal test pattern in a double exposure form to form a test pattern in which the normal test pattern and the arbitrary test pattern are overlapped with each other. The reticle is characterized in that the scribe lane area between the product die exposure area and the product die exposure area is defined, the normal test pattern is formed in the scribe lane area, the second reticle is product die exposure area and product die exposure area A basic exposure area having a scribe lane area therebetween and an external area outside the basic exposure area are defined, and the arbitrary test pattern is formed in the external area.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

An embodiment of the present invention described below may arbitrarily form a pattern to be tested by adjusting a space while maintaining a cell pitch, thereby changing only a gap while maintaining a pitch that is the same as a real cell pitch. I want to test it.

As mentioned earlier, as the integration of semiconductor devices increases, ISO cell pitch decreases, and the field oxide gap margin is gradually decreasing.

Therefore, although a gap-fill oxide film material having a high selectivity has been developed, it is not actually following the device shrinkage. Therefore, the gap fill test in the real cell pattern is performed for each integrated device. Also, the real product reticle is applied and the test reticle is applied. There is a very sensitive margin.

Therefore, timely testing should be done according to trench etch depth (STI Etch Depth), profile and cell active CD.

However, in order to test such gap fill margins, an investigation in a real cell having a constant active area CD or an irradiation pattern using a predetermined pattern inserted in a test pattern is used. Its size is fixed, making it difficult to test.

Therefore, the present invention is intended to test by inserting a flexible (flexible) pattern to compensate for this disadvantage. The gap fill test pattern to be used in the present invention may set a test pattern by combining a normal test pattern (FIG. 3) to be normally exposed and an arbitrary pattern (FIG. 4) on a mask that can be flexibly controlled by overlapping with the normal test pattern (FIG. 3). will be.

3 is a layout of a test pattern in a scribe lane having the same pitch as a real cell and different CD sizes, and FIG. 4 is the same pitch as a real cell and a CD size according to an embodiment of the present invention. 5 is a layout of a test pattern outside another frame, and FIG. 5 is a view showing a state in which the test patterns of FIGS. 3 and 4 are overlapped with each other, and FIG. 6 is a detailed view of FIG. 5.

Referring to FIG. 3, in the first reticle 100, four product die regions 101 in which a real cell pattern is formed are formed, and a normal test is performed in a scribe lane region between the product die regions 101. Pattern 102 is formed. In this case, the product die area 101 is a region where the real cell pattern is formed, and the normal test pattern 102 is arranged in a chrome pattern 102a having the same pitch as the real cell pattern and having a different CD size. Test pattern. For example, the real cell pattern has an L / S of 100/100, and the chrome pattern 102a of the normal test pattern 102 has an L / S of 140/60.

Referring to FIG. 4, the second reticle 200 defines a basic exposure reticle region 201 that is basically exposed to a predetermined region. Here, similar to the layout of FIG. 3, the basic exposure reticle region 201 is formed with four product die regions 201a, and a scribe lane region between the product die regions 101 is defined. have.

In addition, an arbitrary test pattern 202 is formed in an outer region of the mask frame outside the basic exposure reticle region of the second reticle, that is, the region outside the basic exposure reticle region 201. At this time, the arbitrary test pattern 202 is a test pattern in which chrome patterns 202a having the same pitch as the real cell pattern of the basic exposure reticle region 201 and having different CD sizes are arranged. For example, the real cell pattern has an L / S of 100/100, and the chrome pattern 202a of an arbitrary test pattern 202 has an L / S of 140/60.

Referring to FIG. 5, the normal test pattern 102 to be normally exposed on the first reticle 100 is designed in the form of a constant L / S pattern (Line / Space) in consideration of the cell pitch to the scribe lane. It will always be exposed.

Subsequently, an offset of an arbitrary test pattern 202 formed in a basic exposure mask frame of the second reticle 200, that is, in an external region other than the basic exposure reticle region 201 is provided. The test pattern 300 in which the normal test pattern 102 and the arbitrary test pattern 202 are finally overlapped is exposed by exposing the normal test pattern 102 formed in the scribe lane region of 100 in a double exposure form. Form.

The final test pattern 300 exposed as described above can be flexibly controlled by L / S according to the offset degree. For example, the cell pitch L / S 100nm / 100nm will be described in more detail as follows.

Basically, the chromium pattern 102a of the normal test pattern 102 shown in FIG. 3 formed on the scribe lane has L / S having a size of 140 nm / 60 nm. This is because the pattern of the active region in which the line L is formed is offset so that the line part is largely designed in consideration of any pattern size to be exposed. Since the double pattern will be exposed again, the line pattern will be exposed again in advance. It is drawn in a large size.

In this way, the test pattern 202 of FIG. 4 is offset to the normal test pattern 102 on the scribelane firstly exposed, so that the double exposure is performed. When 202a) is exposed to the normal test pattern 102 with a size of 140 nm / 60 nm, assuming that the region where the chrome pattern overlaps is 120 nm, the final test pattern 300 has a L / S of 120 nm / 80 nm. Is defined as.

Referring to FIG. 6, which shows the final test pattern 300 of FIG. 5 in detail, an area in which the chromium region overlaps on the mask becomes a non-exposed region where no photoresist receives energy at all, thus forming a pattern to form an active region. The double exposure area 401, the area 402 where the normal test pattern of FIG. 3 is exposed, and the area 403 where any test pattern of FIG. 4 is exposed are all developed because the photoresist receives energy. And the field oxide region 400 is formed.

However, the random test pattern 202 of FIG. 4 arbitrarily adjusts the offset amount to set the overlapping portion of the chromium region to 140 nm, which is the maximum line size, and the spacing (field oxide region) is controlled to 60 nm. If the area where the chrome area overlaps is controlled at 80nm, the gap is controlled at 120nm.

Such overlapping areas can be freely adjusted when giving an offset to any test pattern of FIG. 4 on a photo exposure recipe, thereby allowing flexible control of the field oxide film size.

In addition, the field oxide film size can be controlled regardless of the exposure conditions of the cell region, and since the cell pitch is always maintained even under exposure by arbitrarily specifying the size of the pattern to be tested, the field oxide film CD has the same mask. The most accurate test can be carried out on the gap fill issue when adjusting.

FIG. 7 is a view schematically illustrating a device isolation method using a mask in which the final test patterns of FIGS. 5 and 6 are formed. Here, the mask (or reticle) is along the line II ′ of FIG. 6.

Referring to FIG. 7, after the pad mask 102 is formed on the semiconductor substrate 101, the photoresist 103 is coated on the pad mask 102, and the final test pattern 300 of FIG. 5 is formed. The exposure process is performed using the formed mask.

In this exposure process, the final test pattern is formed by exposing the normal test pattern and an arbitrary test pattern in a double exposure form, and is a non-exposed area where the photoresist 103 does not receive energy. The double exposure area 401, the area 402 where the normal test pattern is exposed, and the area 403 where an arbitrary test pattern is exposed, are areas where the photoresist receives energy. That is, the final test pattern 300 is a region in which energy is not passed through the chrome pattern.

Next, the lower pad mask 102 is etched using the post-exposure developed photoresist 103, and the semiconductor substrate 101 exposed the photoresist 103 or the pad mask 102 as an etch barrier is removed. The trench 104 is etched to a predetermined depth to form a trench 104 to be an isolation region.

As above, after the process using the final test pattern 300 is L / S 120nm / 80nm. Where L is the CD of the active region and S is the CD of the trench between the active regions.

In the above-described embodiment, the test pattern for the active region and the field oxide film has been described, but the present invention can be applied to the gate electrode, the metal wiring, and the like, which are likely to cause voids, in the same manner.

For example, an area where the normal test pattern and an arbitrary test pattern overlap is a gate electrode area, an area exposed by the normal test pattern, an area exposed by an arbitrary test pattern, and a double of the normal test pattern and an arbitrary test pattern. The exposure area becomes a gap fill area between the gate electrodes.

In addition, the region where the normal test pattern and the arbitrary test pattern overlap is a metal wiring region, the area exposed by the normal test pattern, the area exposed by the arbitrary test pattern, and the double of the normal test pattern and the arbitrary test pattern. The exposure area becomes a gap fill area between metal wirings.

The test pattern of the present invention may be formed in the ISO mask of the cell region (the mask is also called a reticle), in the ISO mask of the peripheral region, or in the ISO mask of the cell and the peripheral region.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above is most usefully used when the active region and the field oxide film are a straight pattern, such as a flash device, and such a pattern can perform various gap fill tests because the CD can be appropriately adjusted for the gap fill test. It works.

In addition, by forming a test pattern outside the exposure area, such as the pattern of Figure 4 in a variety of forms to adjust the area for double exposure can be made in the active region and the field oxide film in a variety of forms from Undersize (Oversize) to Oversize (Oversize), Since the pattern in the basic scribelane has only a small size, there is an effect that can maximize the utilization of the scribelane.

Claims (9)

Preparing a first reticle having a normal test pattern having the same pitch as the real cell pattern and having a different CD size; Preparing a second reticle having an arbitrary test pattern having the same pitch as that of the real cell pattern and having a different CD size; And Offsetting the arbitrary test pattern to expose the normal test pattern in a double exposure form to form a test pattern in which the normal test pattern and the arbitrary test pattern overlap each other; Method of manufacturing a gap fill test pattern of a flash memory device comprising a. The method of claim 1, The first reticle, A scribe lane region is defined between a product die exposure area and a product die exposure area, and the normal test pattern is formed in the scribe lane area. The method of claim 2, The second reticle, A flash memory device, characterized in that a basic exposure area having a scribe lane area between a product die exposure area and a product die exposure area and an external area outside the basic exposure area, and wherein the arbitrary test pattern is formed in the external area. The manufacturing method of the gap fill test pattern of this. The method of claim 3, And the normal test pattern and the arbitrary test pattern have the same line / space (L / S) pattern. The method of claim 4, wherein The real cell has a line / space (L / S) of 100/100, and the normal test pattern and the arbitrary test pattern have a line / space (L / S) of 140/60. Manufacturing method of gap fill test pattern The method according to any one of claims 1 to 5, The area where the normal test pattern and the arbitrary test pattern overlap each other becomes an active area, an area exposed by the normal test pattern, an area exposed by the arbitrary test pattern, and the normal test pattern and the arbitrary test. The method of manufacturing a gap fill test pattern of a flash memory device, wherein the double exposure area of the pattern is a field oxide film area. The method according to any one of claims 1 to 5, The region where the normal test pattern and the arbitrary test pattern overlap is a gate electrode region, an area exposed by the normal test pattern, an area exposed by the arbitrary test pattern, and the normal test pattern and the arbitrary test pattern. The double exposure region of the test pattern is a gap fill region between the gate electrodes, the manufacturing method of the gap fill test pattern of the flash memory device. The method according to any one of claims 1 to 5, The region where the normal test pattern and the arbitrary test pattern overlap is a metal wiring region, an area exposed by the normal test pattern, an area exposed by the arbitrary test pattern, and the normal test pattern and the arbitrary test pattern. And a double exposure region of the test pattern is a gap fill region between the metal wirings. The method of claim 1, The test pattern may be formed in an ISO mask of a cell region, an ISO mask of a peripheral region, or both of the cell region and an ISO mask of a peripheral region.

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