KR20000076914A - Nonvolatile semiconductor memory and manufacturing method thereof - Google Patents

Abstract

In the method of manufacturing a nonvolatile semiconductor memory device having an element region formed by groove-type isolation and having a memory cell portion having a floating gate and a peripheral circuit portion, the peripheral circuit portion is formed before the grooves 305 of the STI are filled with an insulator. The buzzvik oxide film 310 in the upper portion of the element region is formed larger than that of the memory cell portion.

Specifically, the memory cell portion is covered with the oxidation resistant film 308 or the oxynitride film or the STI grooves in the peripheral circuit portion are formed before the oxidation step of inserting the buzzvik to form a large buzz beak at the end of the peripheral circuit element region. . Alternatively, an oxynitride film is formed on the STI sidewall of the peripheral circuit portion, and film shrinkage of the sidewall insulating film at the time of oxide film etching is prevented. By the above process, the formation of parasitic transistors in the peripheral circuit portion of the nonvolatile memory using STI is prevented, and the standby current consumption is suppressed.

Description

Nonvolatile semiconductor memory device and manufacturing method thereof {NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a stack gate type memory cell having a control gate and a floating gate, and a peripheral circuit integrated on the same chip, and a method of manufacturing the same. Therefore, the present invention relates to a nonvolatile semiconductor memory device in which trench element isolation is formed and suppressed generation of kink characteristics in a transistor of a peripheral circuit portion.

BACKGROUND ART A nonvolatile semiconductor memory device in which a stacked gate type memory cell having a control gate and a floating gate and a peripheral circuit for driving the same are integrated on the same chip. In general, in this type of semiconductor memory device, trench element isolation (Sha11ow Trench Isolation: STI) is formed in a self-aligned manner with the polycrystalline silicon layer for the floating gate, and for the transistor of the peripheral circuit, the polycrystal for the floating gate is formed. After the silicon is removed, gate oxidation and electrode formation are performed again.

When the floating gate polycrystalline silicon is removed, the end portion of the peripheral circuit element region is exposed, and a gate electrode formed on the element region is then formed in the upper side of the element region in a recessed manner. When the gate electrode is recessed, a parasitic transistor is formed on the side surface of the element region, and a so-called kink characteristic occurs in which the characteristic characteristic of the low threshold due to the parasitic transistor is superimposed on the drain voltage current characteristic curve of the MOSFET. . If this kink characteristic occurs, it causes a problem such as an increase in current when the memory is waiting.

In order to prevent this kink characteristic, it is necessary to form a large amount of buzzbee between the device region and the polycrystalline silicon layer in advance. In particular, when electrons are drawn from the floating gate to the silicon substrate, electric field concentration occurs at the portion where the shape is changed, leading to a gap in the erase speed for each cell. This gap in erase speed causes an increase in the erase Vth distribution width, and causes a problem of over-erasing in the NOR flash memory. However, if oxidation can only be performed so that the memory cell does not become buzz big, the gate electrode is recessed in the STI in the peripheral circuit portion, and the kink characteristic is generated. This leads to an increase in the subthreshold leakage in the peripheral circuit, and increases the standby current consumption of the semiconductor memory device.

The above problem is explained in detail with reference to FIGS. 24A-24D-27A-27C.

After the tunnel oxide film 102 is formed on the silicon substrate 101, the first polycrystalline silicon 103 serving as the lower layer portion of the floating gate is deposited (FIG. 24A). Next, in order to form the device isolation region, a shallow groove (STI region) 104 is formed (FIG. 24B). At this time, the ends of the floating gate and the STI are formed self-aligned, the floating gate does not fall into the STI grooves, and operation gaps of the memory cells are not easily generated. The inside of the STI region is filled with an insulating film 105, and then second polycrystalline silicon 106, which is an upper layer portion of the floating gate, is deposited and separated for each cell (FIG. 24E).

Next, an insulating film 107 is formed between the floating gate and the control gate formed later. Usually, it is a three layer structure film | membrane of an oxide film / nitride film / oxide film (FIG. 24D). The subsequent drawing shows the process of forming the peripheral circuit portion.

The insulating film 107, the floating gates 103 and 106, and the tunnel oxide film 102 of the peripheral circuit portion are removed. In the wet etching step of removing the tunnel oxide film, the buried insulating film 105 at the STI end part may retreat and a pit may occur. In this case, as shown in FIGS. 25 and 26, the gate electrode 108 of the peripheral circuit is caught on the side of the active area (AA) area, and the gate electrode overlaps the AA edge where electric field concentration occurs, thereby causing parasitic transistors. Is formed. This parasitic transistor has a low threshold characteristic, which is superimposed on the drain voltage and current characteristics of the main transistor to generate a kink characteristic.

As a method of preventing this, as shown in Fig. 27A, before forming the buried insulating film 205 in the STI 204, it is sufficiently oxidized, so that the first polycrystalline silicon 203 and the silicon substrate 201 are formed. There is a method of forming at the interface. In this way, even after the polycrystalline silicon and the tunnel oxide film are removed in the peripheral circuit portion, as shown in 26b, retraction of the insulating film at the end of the STI can be prevented. The polycrystalline silicon layer 206 is a second polycrystalline silicon layer serving as an upper layer portion of the floating gate. 207 is an insulating film, and 208 is a polycrystalline silicon layer.

By the way, when such sufficient oxidation is performed, it turned out that a big problem arises. In other words, as shown in 26c, if BuzzBik is largely intruded between the floating gate 203 and the silicon substrate 202 in the memory cell region, the shape of the polycrystalline silicon is varied, so that the shape becomes uneven and oxidization occurs. A convex shape appears, where the electric field is concentrated. When such nonuniformity occurs, a difference in extraction speed occurs when, for example, the operation of drawing out electrons from the floating gate occurs, which causes a problem that the erase vth distribution is enlarged. The wide erase distribution leads to an operation failure of excessive erase in the N0R type flash memory.

As described above, in the conventional STI type nonvolatile semiconductor memory device, in order to suppress the kink characteristic of the peripheral circuit transistor, a large amount of buzz is sometimes formed at the interface between the polycrystalline silicon and the silicon substrate. By the way, there is a large invasion between the floating gate of the memory cell portion and the silicon substrate, which causes a difference in the extraction speed in the case of taking out the electrons from the floating gate, resulting in an enlarged erase Vth distribution. Occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device having a small characteristic gap in a memory cell portion, no occurrence of kink characteristics in a peripheral circuit portion, and thus no increase in current consumption during standby, and a fabrication thereof. To provide a way.

1A to 1D are cross-sectional views showing step by step a manufacturing method of a semiconductor memory device according to the first embodiment of the present invention.

2A to 2C are cross-sectional views showing a process following FIG. 1D.

3A-3C are cross-sectional views illustrating a process following FIG. 2C.

4A-4D are cross-sectional views illustrating a process following FIG. 3C.

FIG. 5 is a sectional view of a process following FIG. 4D. FIG.

6A to 6O are cross-sectional views for explaining the method for manufacturing a semiconductor memory device according to the second embodiment of the present invention.

7A to 7C are cross-sectional views showing step by step manufacturing methods of a semiconductor memory device according to the third embodiment of the present invention.

8A and 8B are cross-sectional views illustrating a process following FIG. 7C.

9A to 9D are cross-sectional views showing step by step manufacturing methods of the semiconductor memory device according to the fourth embodiment of the present invention.

10A to 10C are cross-sectional views illustrating a process following FIG. 9D.

11A to 11D are cross-sectional views showing step by step manufacturing methods of a semiconductor memory device according to the fifth embodiment of the present invention.

12A to 12C are cross-sectional views illustrating a process following FIG. 11D.

13A to 13C are cross-sectional views illustrating a process following FIG. 12C.

14A-14D are sectional views of a process following FIG. 13C.

15A to 15D are cross-sectional views showing step by step manufacturing methods of the semiconductor memory device according to the sixth embodiment of the present invention.

16A to 16C are cross-sectional views illustrating a process following FIG. 15D.

17A to 17D are cross-sectional views illustrating a process following FIG. 16C.

18A to 18D are cross-sectional views showing step by step manufacturing methods of the semiconductor memory device according to the seventh embodiment of the present invention.

19A to 19D are sectional views showing a process following FIG. 18D.

20A and 20B are enlarged cross-sectional views illustrating one example of a shape of a portion indicated by ○ in FIG. 19C and an example of a shape after device completion of this portion, respectively.

21A to 21C are cross-sectional views each illustrating part of the manufacturing process of the N0R-type flash EEPR0M according to the eighth embodiment of the present invention.

22A to 22D are cross-sectional views each illustrating part of a process following the process of FIG. 21C.

FIG. 23 is an enlarged cross-sectional view of an example of the shape of a portion indicated by ○ in FIG. 19C. FIG.

24A to 24D are cross-sectional views showing step-by-step methods of manufacturing a conventional semiconductor memory device.

25 and 26 are cross-sectional views for explaining parasitic transistors generated in a conventional semiconductor memory device.

27A to 27C are cross-sectional views for explaining a method of forming a buzz big and a problem in a conventional semiconductor memory device.

FIG. 28 is a cross-sectional view for explaining a method of forming a buzz big and a problem in FIG. 27C. FIG.

<Explanation of symbols for main parts of drawing>

101: silicon substrate

102: tunnel oxide film

103: first polycrystalline silicon

104: shallow groove (STI area)

105: insulating film

106: second polycrystalline silicon

201: silicon substrate

204: STI

301: Silicon Substrate

302 tunnel oxide film

303: first polycrystalline silicon layer

304: silicon nitride film

308: oxidation resistant film

309: resist pattern

In order to achieve the above object, in the method of manufacturing a nonvolatile semiconductor memory device of one embodiment of the present invention, a nonvolatile semiconductor memory having a device region formed by groove-type isolation and having a memory cell portion having a floating gate and a peripheral circuit portion thereof In the method of manufacturing a device, a process of forming a polycrystalline silicon layer on an silicon substrate through an insulating film, and in order to form an element region, the polycrystalline silicon layer, the insulating film, and the silicon substrate are etched in a self-aligned manner to form a silicon substrate. Forming a plurality of grooves for device isolation having a bottom portion and surrounding the device region, rounding each end of the surface where the device region and the polycrystalline silicon layer face each other by oxidation; A step of coating with a film having a film and adding oxidation after the formation of the oxidation resistant film, A step of forming a buzzvik oxide film thicker than the memory cell portion is provided between the silicon substrate and the end portions of the surfaces of the polycrystalline silicon layer facing each other.

In the above manufacturing method, after the oxide resistant film is deposited, before the oxidation to the peripheral circuit portion, a step of selectively removing the oxidation resistant film so that the oxidation resistant film remains only in the floating gate side portion in the memory cell portion is added. It can be included as.

After the oxidation of the peripheral circuit portion, the oxidation resistant film covering the memory cell portion may be removed.

In order to achieve the above object, in the method of manufacturing a semiconductor memory device of another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device of a nonvolatile semiconductor memory device in which an element region is formed by groove-type element isolation, and further comprising a memory cell portion having a floating gate and a peripheral circuit portion thereof. A manufacturing method comprising the steps of laminating a polycrystalline silicon layer on an silicon substrate through an insulating film, self-aligning the polycrystalline silicon layer, the insulating film, and the silicon substrate only in the peripheral circuit portion to form a first device isolation groove; In the peripheral circuit portion, oxidizing each end of the surface where the element region and the polycrystalline silicon layer face each other to form a buzzvik oxide film, and self-aligning the polycrystalline silicon layer, the insulating film, and the silicon substrate in the memory cell portion. Etching to form the second device isolation groove, and after forming the second device isolation groove, Determined by oxidizing the respective ends of the surface silicon layer is opposed, it characterized in that it comprises a step of forming a thin oxide film than the buzz bikhyeong buzz bikhyeong oxide film formed on the peripheral circuit portion.

In order to achieve the above object, in the method of manufacturing a nonvolatile semiconductor memory device according to another aspect of the present invention, the nonvolatile semiconductor memory includes a memory cell portion having a floating gate, and a memory cell portion having a floating gate and a peripheral circuit portion thereof. A method of manufacturing a semiconductor device, the method comprising: forming an oxide resistant film on a silicon substrate through an insulating film, selectively removing the oxide resistant film and the insulating film from the memory cell portion, and forming a tunnel oxide film on the memory cell portion, which is nitrided. To oxynitride the tunnel film, to form a polycrystalline silicon layer on the tunnel oxynitride film of the memory cell portion and on the oxidation resistant film of the peripheral circuit portion, and to self-align the polycrystalline silicon and the silicon substrate by etching The device region and the polycrystalline seal by forming a groove for device isolation and oxidizing after formation of the device isolation groove. And between the ends of the opposing forming surfaces koncheung buzz bikhyeong oxide film, characterized by including a step of forming a thicker oxide film than the buzz bikhyeong memory cell in the peripheral circuit portion.

Moreover, in order to achieve the said subject, in the manufacturing method of the nonvolatile semiconductor memory device of another aspect of this invention, the nonvolatile region which has a memory cell part which has an element region formed by the isolation | separation type | mold element, and has a floating gate and its peripheral circuit part A method of manufacturing a semiconductor memory device, comprising: forming a polycrystalline silicon layer on an silicon substrate through an insulating film; and forming an element region by self-aligning the polycrystalline silicon layer and the silicon substrate to form an element region. A step of forming a groove, a step of rounding an end portion of each surface of the element region and the opposing face of polycrystalline silicon by oxidation, a step of covering only a memory cell portion with a silicon film, and post-oxidation of the silicon film, Buzz thicker than the memory cell portion between the silicon substrate of the peripheral circuit portion and the end of the opposite surface of the polycrystalline silicon layer And a step of forming a big oxide film and an oxide film of a silicon film covering the memory cell portion.

In order to achieve the above object, a nonvolatile semiconductor memory device according to another aspect of the present invention includes a semiconductor substrate, a memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed, and a circuit for controlling the memory cell. A peripheral circuit portion on the semiconductor substrate, a plurality of element regions formed in the memory cell portion and the peripheral circuit portion, respectively, separated by a plurality of grooves, an oxynitride film formed on the inner wall of the groove, an insulating film filling the groove, On the element region of the peripheral circuit portion, an end portion has a gate electrode formed through a gate insulating film defined by the oxynitride film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method including forming a polycrystalline silicon layer serving as an insulating film and a floating gate on a silicon substrate, and self-aligning the polycrystalline silicon layer and the silicon substrate to perform element isolation. And forming a silicon oxynitride film on the inner wall of the groove and the sidewall of the polycrystalline silicon layer.

In this manufacturing method, in the step of forming a silicon oxide film on the inner wall of the groove and the sidewall of the polycrystalline silicon layer, after the silicon oxide film is formed on the inner wall of the groove and the sidewall of the polycrystalline silicon layer, an oxynitride treatment is performed to form an oxynitride film. It is good also as a process to form.

A semiconductor memory device according to another aspect of the present invention includes a memory cell array region in which a plurality of memory cell transistors are formed, the element region of the memory cell transistor being insulated and separated by a buried element isolation region, and the peripheral circuit transistor of the memory cell array. A plurality of element regions of the peripheral circuit transistor are formed, the peripheral transistor regions being insulated and separated by buried element isolation regions, and the curvature of the end portions of the element regions of the peripheral circuit transistors It is characterized by being set substantially larger than curvature.

In this semiconductor memory device, the difference between the height of the flat portion of the element region and the height of the lowest portion of the gate electrode located above it may be 4 nm or more.

In this semiconductor memory device, the bias potential at which the subthreshold current flows may be given when the peripheral circuit transistor is in the standby state.

In this semiconductor memory device, at least part of the gate electrode of the memory cell transistor may be self-aligned with the buried element isolation region in the memory cell array region.

In this semiconductor memory device, the memory cell transistor may also be a memory cell of a nonvolatile semiconductor memory having a floating gate.

In the method of manufacturing a semiconductor device of another aspect of the present invention, in the manufacture of a semiconductor device, a part of the gate insulating film of the MOS transistor is formed before the element isolation forming step, and the remainder of the gate insulating film is formed after the element isolation forming step. MOS so that the curvature of the end of the element region of the MOS transistor having the gate insulating film formed after the element isolation forming process becomes substantially larger than the curvature of the end of the element region of the MOS transistor having the gate insulating film formed before the element isolation forming process. A transistor is formed.

A manufacturing method of a semiconductor device according to another aspect of the present invention is a manufacturing method of a nonvolatile semiconductor memory having a memory cell array region and a peripheral transistor region in which a peripheral circuit transistor is formed, the first method for a memory cell transistor on a front surface of a semiconductor substrate. Forming a gate insulating film, and forming a polysilicon film and an insulating film thereon; forming a trench for forming an isolation region in the insulating film, the polysilicon film, the first gate insulating film, and the semiconductor substrate; and the memory cell Removing the first gate insulating film on the end of the element region of the peripheral transistor region after covering the array region, and a portion between the surface of the trench and the end of the element region in the peripheral transistor region and the polysilicon film thereon Oxidizing the surface of the buried material, embedding a buried insulator in the trench, and A step of planarization, a step of removing the insulating film on the polysilicon film, a step of forming a second gate insulating film for the peripheral circuit transistor after removing the polysilicon film and the first gate insulating film in the peripheral transistor region, and Forming a stacked gate structure having the polysilicon film as a floating gate in a memory cell array region; forming a gate electrode on the second gate insulating film in a peripheral transistor region; and source / drain of a transistor in a substrate surface layer portion. And a step of selectively introducing impurities.

A manufacturing method of a semiconductor device according to another aspect of the present invention is a manufacturing method of a nonvolatile semiconductor memory having a memory cell array region and a peripheral transistor region in which a peripheral circuit transistor is formed, the first method for a memory cell transistor on a front surface of a semiconductor substrate. Forming a gate insulating film and forming a polysilicon film thereon; forming a trench for forming an isolation region in the polysilicon film, the first gate insulating film, and the semiconductor substrate; and embedding a buried insulator in the trench; A process of planarizing the entire surface, forming an inter-gate insulating film for floating gate-control gate insulation of the memory cell transistor on the entire substrate, and an inter-gate insulating film, a polysilicon film, and a first gate insulating film in the peripheral transistor region. Exposing the device region by removing the region; Etching an angle of an end portion of the element region exposed in the region to form a round shape, forming a second gate insulating film for the peripheral circuit transistor in the peripheral transistor region, and forming the poly gate in the memory cell array region. Forming a stacked gate structure having a silicon film as a floating gate, forming a gate electrode on the second gate insulating film in the peripheral transistor region, and selectively introducing impurities serving as a source / drain of the transistor in the substrate surface layer portion Characterized in that it comprises a.

Example

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)

1A-1D through 4D are sectional views showing the manufacturing method of the semiconductor memory device according to the first embodiment of the present invention in a step-by-step manner.

First, a tunnel oxide film 302 of a memory cell, for example, 10 nm is formed over the silicon substrate 301. Next, 70 nm of the first polycrystalline silicon layer 303 serving as the lower layer portion of the floating gate is formed on the upper portion thereof (Fig. 1A). In addition, a silicon nitride film 304 is usually deposited thereon, for example, 200 nm. Thereafter, a photolithography step forms a resist pattern in which portions of the STI grooves are opened, and the silicon nitride film 304 is processed based on the resist pattern (FIG. 1B).

Next, using the nitride film 302 as a mask, the first floating gate polycrystalline silicon 303, the tunnel oxide film 302, and the silicon substrate 301 are sequentially etched by the RIE method in this order. The shallow groove 305 formed in the silicon substrate 301 is a device isolation groove (STI).

Next, at the interface between the first polycrystalline silicon 303 serving as the floating gate and the silicon substrate 301, an oxidation, for example, a thermal oxidation process of 10 nm is suppressed with a small amount of oxidation so as not to introduce too much buzz. As a result, a thermal oxide film 306 is formed (FIG. 1C).

Next, an oxide film 307 is thinly deposited thereon by the CVD method. Further, an oxide resistant film, specifically a silicon nitride film 308, is deposited thereon, for example, 6 nm (FIG. 1D).

Next, a resist pattern 309 in which only the peripheral circuit portion is opened by the photolithography step is formed on the substrate (FIG. 2A). Using the resist pattern 309 as a mask, the oxidation resistant film 308 of the peripheral circuit portion is removed (FIG. 2B). For example, if the silicon nitride film, it can be removed by a method such as CDE (Chemical Dry Etching). In addition, the CVD oxide film 307 formed below the oxidation resistant film serves to reduce damage to the silicon substrate when the buried insulating film is later deposited inside the STI.

Subsequently, oxidation is carried out for inserting the bird's beak into the element region (silicon substrate 301) of the peripheral circuit portion and the opposing surface end portions of the first polycrystalline silicon layer 303 (FIG. 2C). The bird's beak 310 formed by this oxidation reduces the pitting of the gate electrode at the time of forming the peripheral circuit later. Therefore, this oxidation is carried out under a condition that a sufficient amount, for example, an oxide film of 30 nm is formed on the silicon substrate.

At this time, the memory cell part is covered with the oxidation resistant film 308 and is not oxidized. Therefore, no buzz bend is formed at the end portions of the element regions (silicon substrate 301) and the opposing surfaces of the first polycrystalline silicon layer 303 in the memory cell portion. Therefore, the curvature of the element region of the peripheral circuit portion can be substantially larger than the curvature of the element region of the memory cell portion. In addition, you may remove an oxidation resistant film afterwards as needed. If a silicon nitride film is present in the vicinity of the memory cell, the tunnel oxide film may be damaged by hydrogen diffused therefrom, and thus may be removed if necessary, but is not shown in this example. In addition, when removing a silicon nitride film, what is necessary is just to remove it by the etching by hot phosphoric acid or CDE (CHEMICAL DRY ETCHING) after the process of FIG. 1D.

Next, for example, a plasma oxide film 311 is deposited to fill the inside of the STI (FIG. 3A). When the aspect ratio is high, it may be deposited by using a high density plasma (HDP) CVD method. Next, the plasma oxide film 311 is planarized by, for example, a CMP (Chemica1 Mechanica1 po1ishing) method (FIG. 3B).

Next, the silicon nitride film 304 on the first floating gate polycrystalline silicon 303 is removed by wet etching. In some cases, in order to adjust the height of the insulating film 311 embedded in the STI, the insulating film 311 may be somewhat etched before removing the nitride film. Thereafter, a polycrystalline silicon layer 312 for the second floating gate is formed thereon. Further, a lithography process and etching of the floating gate separation region 313 are performed on the STI region. This produces a floating gate 312 separated for each cell (Fig. 3C).

Next, on the floating gate, a laminated insulating film 314 of, for example, an oxide film / nitride film / oxide film ONO, which is an insulating film between the floating gate and the control gate, is formed (FIG. 4A). Thereafter, the figure shows only the peripheral circuit portion.

Next, the memory cell area is covered with a resist by a photolithography process, and the dry etching of the ONO film 314 in the peripheral circuit area and the first and second polycrystalline silicon 303 and 312 for the floating gate is performed, and the tunnel oxide film 312 is provided. Is removed by wet etching (FIG. 4B). Since the gate burzvik is sufficiently formed, the upper end of the element region is protected during this wet etching, and it is possible to prevent the dent of the oxide film at the upper end.

Next, a gate oxide film 315 having an oxide thickness, for example, 15 nm, is formed on the substrate surface of the peripheral circuit (FIG. 4C), and then a polycrystalline silicon layer 316 is formed thereon (FIG. 4D). The polycrystalline silicon layer 316 is processed to become a gate electrode of the peripheral circuit portion and a control gate electrode of the memory cell portion.

Next, although not shown, the gate processing of the peripheral transistors and the memory cell transistors is performed, and then, as is usually performed, a diffusion layer is formed in the memory cell portion and the peripheral circuit portion, and a wiring process is performed. This completes the memory cell array.

By employing the above steps, a semiconductor memory device in which a large amount of invasion of Buzzvik is infiltrated only into the peripheral circuit portion without invading the memory cell portion. That is, the curvature of the element region of the peripheral circuit portion can be substantially larger than the curvature of the element region of the memory cell portion.

(2nd Example)

In the first embodiment, the entire surface of the memory cell region is covered with a silicon nitride film. However, when the entire surface is covered with a silicon nitride film and subjected to heat treatment, the tunnel oxide film 302 of the memory cell may deteriorate. In order to minimize this phenomenon, the oxidation resistant film may be formed in a sidewall shape on the side of the floating gate of the memory cell. The second embodiment provides such a method.

First, the process of FIGS. 1A-1D in the first embodiment is performed. After depositing the oxidation resistant film 308 in FIG. 1D, the entire surface is etched back by RIE, leaving the oxidation resistant film only on the sidewalls. Thereby, the structure shown in FIG. 6 can be obtained. Thereafter, by carrying out the same steps as in Fig. 2 and later in the first embodiment, the structure in which the oxidation resistant film remains only on the floating gate sidewall and the STI inner wall is completed.

(Third Embodiment)

7 and 8 are cross-sectional views showing step-by-step a method of manufacturing a semiconductor memory device according to the third embodiment of the present invention.

First, a tunnel oxide film 502 of a memory cell, for example, 10 nm is formed over the entire silicon substrate 501. Next, 70 nm of the first polycrystalline silicon layer 503 to be part of the floating gate is formed thereon (FIG. 7A). Further, a silicon nitride film 504 is deposited thereon, for example, 200 nm (FIG. 7B). Thereafter, by the photolithography process, a resist pattern (not shown) in which portions forming the grooves of the STI are opened only in the peripheral circuit portion is formed, and the silicon nitride film 504 is processed. Next, using the nitride film 304 as a mask, the first floating gate polycrystalline silicon layer 503, the tunnel oxide film 502, and the silicon substrate 501 are sequentially etched by the RIE method in order to thereby STI 505. To form.

Subsequently, a sufficient buzzvik oxide film 506 must be formed at the interface between the polycrystalline silicon layer 503 and the silicon substrate 501 of the peripheral circuit portion, and is oxidized at 30 nm, for example (Fig. 7C). At this time, since the memory cell portion is covered with the silicon nitride film 504, it is not oxidized.

Next, an STI groove 507 is formed in the memory cell portion (Fig. 8A). Subsequently, the minimum required oxidation, for example, 6 to 10 nm, is oxidized to the memory cell to form an oxide film 508 (Fig. 8B). Thereafter, a buried insulating film forming step into STI corresponding to FIG. 3 of the first embodiment is performed.

Also in the above steps, a semiconductor memory device in which a large amount of invasion of BuzzBic is allowed to enter the peripheral circuit section without invading BuzzBic into the memory cell section. That is, the curvature of the element region of the peripheral circuit portion can be substantially larger than the curvature of the element region of the memory cell portion.

(Example 4)

9A-9D and 10A-10C are cross-sectional views showing step-by-step methods of manufacturing a semiconductor memory device according to the fourth embodiment of the present invention.

First, a first thick oxide film, for example, an oxide film 602 of about 20 nm is formed on the silicon substrate 601 (Fig. 9A). Next, an oxide resistant film such as a silicon nitride film 603 is deposited by 8 nm on the top (FIG. 9B).

Next, the resist 604 is left in the peripheral circuit portion by the lithography process, the silicon nitride film 503 of the memory cell portion is removed (FIG. 9C), and after the resist is removed, the 20 nm silicon oxide film of the memory cell portion is etched away.

Next, a tunnel oxide film 605 is formed in the memory cell portion, for example, at a thickness of 9 nm. Since there is an oxidation resistant film (silicon nitride film) 603 in the peripheral circuit portion, there is no change. Next, nitrogen is introduced between the tunnel oxide film 605 and the silicon substrate 601 by nitriding treatment (FIG. 9D). This nitriding prevents the penetration of Buzzvik in a later step, and in general, the tunnel oxide film becomes oxynitride, thereby improving cell reliability. At this time, since the peripheral circuit portion is covered with the nitride film 603, the interface between the first oxide film 602 and the silicon substrate 601 is not nitrided. The nitriding process is, in general, can be carried out by heat treatment in an ammonia or N ₂ O, N0 gas.

Next, 70 nm of the first polycrystalline silicon layer 606 serving as the lower layer portion of the floating gate is formed on the upper portion thereof (Fig. 10A). Further, a silicon nitride film 607 is usually deposited thereon, for example, 200 nm. Thereafter, a lithography step forms a resist pattern in which a portion forming the grooves of the STI is opened to process the silicon nitride film 607.

Next, using the nitride film 607 as a mask, the peripheral circuit portion uses the first floating gate polycrystalline silicon layer 606, the silicon nitride film 603, the underlying first oxide film 602, and the silicon substrate 601. In the memory cell portion, the first floating gate polycrystalline silicon layer 606, the tunnel oxide film 605, and the silicon substrate 601 are etched vertically by the RIE method in this order. This shallow groove cut into the silicon substrate is an element isolation groove STI (Fig. 10B).

Subsequently, oxidation is carried out to insert buzz big at the interface end portion between the element region of the peripheral circuit portion and the silicon nitride film 603 (Fig. 10C). The oxide films 609 and 610 are formed by this oxidation, but the peripheral circuit portion Buzzvik 610 formed by this can reduce the dents of the gate electrode at the time of forming the peripheral circuit later. Therefore, this oxidation is performed in a sufficient amount, but at this time, the tunnel oxide film is nitrided in the memory cell portion, and it is difficult for Buzzvik to invade.

On the other hand, in the peripheral circuit portion, since there is a thick silicon oxide film 602 which is not nitrided on the element region, a thick buzz 610 can be inserted at the interface between the silicon substrate 601 and the silicon oxide film 602 compared with the memory cell portion. have. The thick silicon oxide film 602 and the silicon nitride films 603, 606, 607 on the upper portion of the peripheral circuit portion are all removed before forming the gate oxide film of the peripheral circuit portion (corresponding to the process of Fig. 4B in the first embodiment).

Also in the above process, a semiconductor memory device in which buzz big is invaded only in the peripheral circuit part without invading buzz big into the memory cell part is realized. That is, the curvature of the element region of the peripheral circuit portion can be substantially larger than the curvature of the element region of the memory cell portion.

(Example 5)

11A to 11D to 14A to 14C are cross-sectional views showing step by step methods for manufacturing a semiconductor memory device according to the fifth embodiment of the present invention.

First, a tunnel oxide film 702 of a memory cell, for example, 10 nm is formed over the silicon substrate 701. Next, 70 nm of the first polycrystalline silicon layer 703 serving as the lower layer portion of the floating gate is formed thereon (FIG. 11A).

In addition, the silicon nitride film 704 is usually deposited, for example, at 200 nm. Thereafter, a photolithography step forms a pattern in which the portions forming the grooves of the STI are opened to process the silicon nitride film. Next, using this nitride film as a mask, the polycrystalline silicon layer for tunneling, the tunnel oxide film, and the silicon substrate for the first floating gate are sequentially processed by the RIE method. The shallow groove cut into the silicon substrate is the device isolation groove STI (Fig. 11B).

Next, oxidation is suppressed with as little oxidation amount as possible so as not to put the buzz big at the interface between the first polycrystalline silicon serving as the floating gate and the silicon substrate too much. For example, a thermal oxidation process of 10 nm is performed. As a result, a thermal oxide film 706 is formed (FIG. 11C).

Next, an oxide film 707 is deposited thereon by the CVD method. In addition, a silicon film is formed thereon. Specifically, the amorphous silicon film 708 is deposited by 10 nm, for example, by reduced pressure CVD (LPCVD) (FIG. 11D).

Next, a resist pattern 709 is formed in which only the periphery is opened by a photolithography step (FIG. 12A). Using this resist material as a mask, the silicon film 708 of the peripheral circuit portion is removed (Fig. 12B). For example, an amorphous silicon film can be removed by a method such as CDE. In addition, the CVD oxide film 707 formed under the silicon film serves to reduce damage to the silicon substrate when the buried insulating film is later deposited inside the STI.

Next, oxidation is carried out to insert BuzzBig into the STI edge of the peripheral circuit portion (Fig. 12C). The bird's beak 710 formed by this oxidation can later reduce the dent of the gate electrode when the peripheral circuit portion is formed. Therefore, this oxidation is performed in a sufficient amount. For example, it is performed under the conditions of forming an oxide film of 30 nm on the silicon substrate.

On the other hand, the memory cell portion is covered with the amorphous silicon film 708, and is completely oxidized at the time of buzzing oxidation of the upper portion of the element region of the peripheral circuit portion, and the amorphous silicon film 708 becomes the silicon oxide film 711, and the film thickness is also weak. It is 20nm which is twice.

In the memory cell portion, after the amorphous silicon film 708 is completely formed of the silicon oxide film 711, the oxidant diffuses the silicon oxide film 711 so that the first polycrystalline silicon film 703 that is under the silicon substrate 701 and the floating gate is also formed. Is oxidized.

However, since the oxidant diffuses the silicon oxide film 711 and diffuses the silicon oxide film 706 formed by the CVD method to reach the silicon substrate 701 or the polycrystalline silicon film 703, the silicon substrate 701 And the oxidation rate of the first polycrystalline silicon film 703 which is the lower layer portion of the floating gate is greatly suppressed. Therefore, in this step, the buzz big hardly enters the upper end of the element region of the memory cell portion.

The amount of oxidation for inserting Buzzvik into the upper end of the element region of the peripheral circuit portion needs to be equal to the amount of oxidation so that the silicon film 708 deposited on the memory cell portion becomes the silicon oxide film 711 completely, and the element region in the memory cell portion. It is necessary for the upper end to have almost no burjbig, and in view of this, the deposited film thickness of the silicon oxide film 708 is set.

Next, for example, a plasma oxide film 712 is deposited to fill the inside of the STI (FIG. 13A). When the aspect ratio is high, it may be deposited using high density plasma (HDP) CVD. Next, the plasma oxide film is planarized by, for example, the CMP method (Fig. 13B).

Next, the silicon nitride film 704 on the first floating gate polycrystalline silicon 703 is removed by wet etching. In some cases, in order to adjust the height of the insulating film 712 embedded in the STI, the insulating film 712 may be somewhat etched before removing the nitride film 704.

Thereafter, the second polycrystalline silicon layer 713 for the floating gate is formed over the substrate.

In addition, a lithography process and etching of the floating gate isolation region 714 are performed on the STI region to perform a process for separating the floating gate for each cell (FIG. 13C).

Next, on the floating gate 713, a stacked insulating film 715 of, for example, an oxide film / nitride film / oxide film ONO, which is an insulating film between the floating gate and the control gate, is formed (FIG. 14A). After that, only the peripheral circuit portion is shown.

Next, the memory cell portion is covered with a resist by a photolithography process, dry etching of the 0NO film 715 of the peripheral circuit portion, the first and second polycrystalline silicon 703 and 713 for the floating gate, and wet etching of the tunnel oxide film are performed. (FIG. 14B). At the time of this wet etching, since the gate buzz big is formed sufficiently, the upper end of the element region is protected, and it is possible to prevent the dent of the oxide film at the upper end.

Next, a gate oxide film 716 having an oxide film thickness, for example, 15 nm, required in the peripheral circuit portion is formed (FIG. 14C), and then a polycrystalline silicon layer 717 is formed thereon (FIG. 14D). This polycrystalline silicon layer 717 becomes a gate electrode of the peripheral circuit portion and a control gate of the memory cell.

Next, although not shown in the drawings, the gate transistors of the peripheral transistors and the memory cell transistors are processed, and then a diffusion layer is formed in the memory cell portion and the peripheral circuit portion as usual, and the wiring process is performed to complete the memory cell array. do.

Also in the above process, a semiconductor memory device in which buzz big is invaded only in the peripheral circuit part without invading buzz big into the memory cell part is realized. That is, the curvature of the element region of the peripheral circuit portion can be substantially larger than the curvature of the element region of the memory cell portion.

(Example 6)

15A to 17D to 17A to 17D are cross-sectional views showing step by step manufacturing methods of the semiconductor memory device according to the fifth embodiment of the present invention. Unlike the first to fifth embodiments, the present embodiment does not form a large buzz big at the upper end of the element region of the peripheral circuit portion, but covers the sidewall of the STI of the peripheral circuit portion with an oxynitride film, By preventing the side surface of the element region from being exposed, it is possible to suppress the pits of the gate electrode of the peripheral circuit portion to the side of the element region.

Hereinafter, the manufacturing process will be described with reference to the drawings, but FIGS. 15 to 17A are views applied to both the memory cell portion and the peripheral circuit portion, and FIGS. 17B to 17D are views applied to the peripheral circuit portion.

First, a silicon oxide film 802 serving as a tunnel oxide film of a memory cell is formed over the silicon substrate 801, for example, 10 nm. Next, 70 nm of the first polycrystalline silicon layer 803 serving as the lower layer portion of the floating gate is formed thereon (FIG. 15A).

In addition, the silicon nitride film 804 is normally deposited, for example, at 200 nm. Thereafter, a photolithography step forms a resist pattern in which the portions forming the grooves of the STI are opened, and the silicon nitride film is processed. Next, using this nitride film as a mask, the polycrystalline silicon layer for tunneling, the tunnel oxide film, and the silicon substrate for the first floating gate are sequentially processed by the RIE method. The shallow groove formed in the silicon substrate is the device isolation groove STI (Fig. 15B).

Next, an oxidation, for example, a thermal oxidation process of 10 nm is suppressed with as little oxidation as possible so as not to put too much buzz big at the interface between the first polycrystalline silicon serving as the floating gate and the silicon substrate. As a result, a thermal oxide film 806 is formed (FIG. 15C).

Next, an oxide film 807 is deposited thereon, for example, by 20 nm. Thereafter, a process of changing the silicon oxide films 806 and 807 into a thermal nitride film is performed (FIG. 9D). Specifically, for example, the treatment is performed for 60 minutes in an NH ₃ atmosphere of 900 ° C, and for 60 minutes in an O ₂ atmosphere of 900 ° C. By this treatment, the interface region between the silicon oxide film 806 and silicon and the surface region of the silicon oxide film 807 become an oxynitride film containing several percent of nitrogen.

Next, for example, a plasma oxide film 812 is deposited to fill the inside of the STI (FIG. 16A). When the aspect ratio is high, it may be deposited using high density plasma (HDP) CVD. Next, the plasma oxide film is planarized by, for example, the CMP method (Fig. 16B).

Next, the silicon nitride film 804 on the first floating gate polycrystalline silicon 803 is removed by wet etching. In some cases, in order to adjust the height of the insulating film 812 embedded in the STI, the insulating film 812 may be somewhat etched before the nitride film 804 is removed. Thereafter, the polycrystalline silicon layer 813 for second floating gate is formed over the entire substrate. In addition, a lithography process and etching of the floating gate isolation region 814 are performed on the STI region to perform a process for separating the floating gate for each cell (FIG. 16C).

Next, on the floating gate 813, a laminated insulating film 715 of, for example, an oxide film / nitride film / oxide film ONO, which is an insulating film between the floating gate and the control gate, is formed (FIG. 17A). Hereinafter, only the peripheral circuit portion is shown.

Next, the memory cell portion is covered with a resist (not shown), and the ONO film, the first and second polycrystalline silicon layers 803 and 813 of the peripheral circuit portion are removed by dry etching, and the tunnel oxide film 802 is removed by wet etching ( 17B). During this wet etching, since the silicon sidewalls and the side surfaces of the first floating gate electrode 802 of the STI are covered with oxynitride oxynitride films 806 and 807, the etching rate of this portion is increased by the etching of the tunnel oxide film 802. It is slower than speed. For this reason, the side surface of the upper end of the element region is not exposed.

Next, a gate oxide film 816 having an oxide thickness necessary for the peripheral circuit portion, for example, 15 nm is formed (Fig. 17C), and then a polycrystalline silicon layer 817 is formed on the top (Fig. 17D). This polycrystalline silicon layer becomes a gate electrode of the peripheral circuit portion and a control gate of the memory cell.

In this embodiment, after the silicon oxide film 805 is formed on the inner wall of the STI by the oxidation treatment, the silicon oxide film 807 is deposited. However, the silicon oxide films 806 and 807 do not necessarily have to be two layers. It may be a single layer silicon oxide film by a film or an oxidation treatment.

Next, although not shown, the gate transistors of the peripheral transistors and the memory cell transistors are processed, and then, as is usually performed, a diffusion layer is formed in the memory cell and the peripheral circuit portion, and the wiring process is completed to complete the memory cell array. do.

In this embodiment, since the upper end side surface of the element region after the gate electrode formation of the peripheral circuit portion is covered with at least an oxynitride film formed on the inner wall of the STI, the kink characteristic of the peripheral transistor due to the thinning of the oxide film does not occur.

According to the invention disclosed in the first to fifth embodiments, since a large buzz is formed between the active region of the memory cell and the silicon substrate, and a large buzz is formed in the peripheral circuit portion, Characteristics fluctuation can be made small. On the other hand, by forming a buzz big in the peripheral circuit, it is possible to prevent the occurrence of the kink characteristic of the MOSFET, and to suppress the increase in the current consumption during standby.

In addition, according to the invention disclosed in the sixth embodiment, since the inner wall of the STI is covered with the silicon oxynitride film, the film shrinkage of the insulating film at the upper end of the element region can be suppressed when the tunnel oxide film is peeled off from the peripheral circuit portion. The occurrence of kink characteristics can be prevented, and an increase in standby current consumption can be suppressed.

(7th Embodiment)

18A-18D to 19A-19D are cross-sectional views showing step-by-step methods of manufacturing a semiconductor memory device according to the seventh embodiment of the present invention. The semiconductor memory device (NOR-type flash EEPR0M) according to this embodiment has an element region insulated by a buried element isolation region, and the film thickness of the gate oxide film of the MOS transistor is different from that of the memory cell array region and the peripheral transistor region. will be.

First, as shown in FIG. 18A, impurities are introduced into the memory cell array region of the semiconductor silicon substrate 901, that is, the memory cell portion and the peripheral transistor region, that is, the peripheral circuit portion, so that the threshold values of the respective transistors become desired values, respectively. A gate oxide film 902 serving as a tunnel oxide film of a memory cell transistor is formed over the entire surface, and a stacked film 904 of a polysilicon film 903, a CDV nitride film, and a CVD oxide film is deposited thereon.

Next, a resist pattern (not shown) is formed on the substrate and the resist pattern is removed after patterning the laminated film 904 using the pattern.

18B, the polysilicon film 903, the gate oxide film 902, and the silicon substrate 901 corresponding to the portion to be formed in the isolation region are formed using the patterned stacked film 904 as a mask. ) To form a shallow trench.

Next, after covering the memory cell array region with a resist (not shown), a wet etching process (or an isotropic dry etching process or both thereof) is performed on the peripheral transistor region, as shown in Fig. 18C, A portion of the gate oxide film 902 on the element region in the peripheral transistor region (part on the end of the element region) is removed to form a shape in which an oxidant is easily supplied to the end of the element region.

Thereafter, the resist is removed to oxidize such that the oxide film thickness on the surface of the trench is 20 nm or more, for example, in a temperature of 900 to 1000 degrees and an oxygen concentration of 10%. At this time, the portion between the element region end of the peripheral transistor region and the polysilicon film 903 thereon is supplied with an oxidizing agent and oxidation proceeds. Therefore, as shown in Fig. 18D, the so-called buzz big enters thickly, and the end portion of the element region is rounded. That is, the curvature of the end of the element region of the peripheral transistor region is increased.

Subsequently, as shown in FIG. 19A, for example, an LP-TE0S film 905 as a buried insulator is embedded in the trench. Thereafter, the entire surface is planarized by the CMP method or the etch back method, the buried insulator is retreated to the middle of the laminated film 904, and then wet etching is performed to remove the laminated film 904.

Next, as shown in Fig. 19B, a polysilicon film 906 into which phosphorus has been introduced as an impurity is deposited on the entire surface of the substrate, and a resist pattern (not shown) is formed thereon, and the polysilicon film is used using this. By patterning 906, a slit 907 for dividing the polysilicon film 906 in the memory cell array region on the device isolation region is formed, and the polysilicon films 906 and 903 in the peripheral transistor region are removed. Thereafter, the resist pattern is peeled off.

Next, a 0N0 insulating film 908 is formed over the entire surface of the substrate, and after covering the memory cell array region with a resist (not shown), the ONO insulating film 908 and the gate oxide film (tunnel oxide film) 902 in the peripheral transistor region. After removing the resist, the resist covering the memory cell array region is removed.

In addition, when the slits 907 are formed in the memory cell array region, the polysilicon films 906 and 903 of the peripheral transistor regions are left, and the 0NO insulating film 908 and the gate oxide film (tunnel oxide film) 902 are removed. The polysilicon films 906 and 903 may be removed.

As shown in Fig. 19C, the following forms the gate oxide film 909 of the transistor for the peripheral circuit as in the related art, and impurities are introduced as shown in Fig. 19D shown in a direction orthogonal to Fig. 19C. A polysilicon film is deposited on the entire surface on the substrate.

In the memory cell array region, the polysilicon film, the 0N0 insulating film 908, and the polysilicon films 906 and 903 are patterned to form a control gate 910 and a floating gate 911 (polysilicon films 906 and 903). )) Forms a stacked gate structure having two layers, and in the peripheral transistor region, the gate electrode 912 is formed by patterning the polysilicon film. Subsequently, although not shown in the drawing, impurities which become the source / drain of the transistor are selectively introduced into the substrate surface layer, and further, deposition of an interlayer insulating film, opening of a contact, wiring formation, and deposition of a surface protective insulating film are completed to complete the flash EEPROM. .

20A is an enlarged example of the shape of an end portion (that is, an end portion of the element region in the peripheral transistor region in which the gate oxide film is formed after forming the element isolation insulating film) corresponding to the portion indicated by the dotted line O in FIG. 19C. An example of the shape after device completion of this portion is shown in an enlarged scale. Here, 901 is a semiconductor substrate, 905 is a device isolation insulating film, 909 is a gate oxide film, and 912 is a gate electrode.

As can be seen from Figs. 20A and 20B, since the gate oxide film 909 on the end of the element region has a shape in which buzz is entered, film shrinkage at the end of the element region in the peeling process during the gate separation process is suppressed, Electric field concentration at the end of the element region becomes less likely to occur.

In addition, the dent of the gate electrode 112 formed on the gate oxide film 909 at the end of the element region in the peripheral transistor region shown in FIGS. 20A and 20B has a small dent amount, that is, measured As a result, the difference d between the height of the flat portion of the element region and the height of the lowest portion of the gate electrode above it was 4 nm or more.

(8th Embodiment)

21A-21C to 22A-22D are cross-sectional views showing step-by-step methods of manufacturing a semiconductor memory device according to the eighth embodiment of the present invention.

First, as shown in FIG. 21A, impurities are introduced into the memory cell array region and the peripheral transistor region of the semiconductor substrate 1001 so that the threshold values of the respective transistors become desired values, respectively. An oxide film 1002 serving as a tunnel oxide film is formed, and a laminated film 1004 of a polysilicon film 1003, a CVD (chemical vapor deposition) nitride film, and a CVD oxide film, into which phosphorus is introduced as impurities, is deposited thereon.

Next, a resist pattern (not shown) is formed on the substrate and the resist pattern is removed after patterning the laminated film 1004 using the pattern.

Thereafter, as shown in FIG. 21B, the polysilicon film 1003, the gate oxide film 1002, and the silicon substrate 1001 corresponding to the portion where the device isolation region is to be formed are formed using the patterned stacked film 1004 as a mask. By removing it, a shallow trench is formed.

Next, as shown in FIG. 21C, a low pressure tetra-eth-oxide-silicon (LP­TEOS) film 1005, which is a buried insulator, is embedded in the trench. Thereafter, the entire surface is planarized by the chemical mechanical polishing (CMP) method or the etch back method, and the buried insulator is retracted to the middle of the laminated film 1004. Thereafter, a wet etching process is performed to completely remove the laminated film 1004.

Next, as shown in Fig. 22A, a polysilicon film 1006 into which phosphorus is introduced as an impurity is deposited on the entire surface of the substrate, and a resist pattern (not shown) is formed thereon, and the polysilicon film is used using this. Pattern 1006. At this time, the slit 1007 which divides the polysilicon film 1006 in the memory cell array region on the element isolation region is formed, and the polysilicon films 1006 and 1003 in the peripheral transistor region are removed. Thereafter, the resist pattern is peeled off.

Next, an ONO insulating film (lamination film of oxide film / nitride film / oxide film) 1008 is formed on the entire surface of the substrate, and the memory cell array region is covered with a resist (not shown), followed by 0N0 insulating film 1008 of the peripheral transistor region. And after removing the gate oxide film (tunnel oxide film) 1002, the resist covering the memory cell array region is removed.

In addition, when forming the slit 1007 in the memory cell array region, the polysilicon films 1006 and 1003 of the peripheral transistor region are left, and the 0NO insulating film 1008 and the gate oxide film (tunnel oxide film) 1002 are removed. At this time, the polysilicon films 1006 and 1003 may be removed. In this step, the angle of the end of the element region in the peripheral transistor region is exposed.

Next, as shown in FIG. 22B while the memory cell array region is covered with a resist, a wet etching process (or an isotropic dry etching process or both thereof) is performed to determine the angle of the exposed device region end portion. It is etched into a round shape.

Next, after removing the resist covering the memory cell array region, as shown in Fig. 22C, the gate oxide film 1009 of the transistor for peripheral circuits is formed as in the prior art, and in a direction orthogonal to Fig. 22C. As shown in Fig. 22D, a polysilicon film into which impurities are introduced is deposited on the entire surface of the substrate. In the memory cell array region, the polysilicon film, the 0NO insulating film 1008 and the polysilicon films 1006 and 1003 are patterned to control the gate 1010 and the floating gate 1011 (polysilicon films 1006 and 1003). ) Is formed into a two-layer stacked gate structure, and the gate electrode 1012 is formed by patterning the polysilicon film in the peripheral transistor region. Subsequently, although not shown in the figure, impurities that become the source / drain of the transistor are selectively introduced into the substrate surface layer, and further, deposition of the interlayer insulating film, opening of contacts, wiring formation, and deposition of the surface protection insulating film are completed to complete the flash EEPR0M. .

FIG. 23 is an enlarged example of the shape of an end portion (that is, an end portion of the element region in the peripheral transistor region in which the gate oxide film is formed after forming the element isolation insulating film) corresponding to the portion indicated by the dotted line O in FIG. 22C. It is shown. Here, 1001 is a semiconductor substrate, 1005 is a device isolation insulating film, and 1009 is a gate oxide film.

As can be seen from FIG. 23, since the end portion of the element region has a rounded shape, electric field concentration at the end portion of the element region, which has been a problem in the past, is suppressed.

Summarizing the conventional manufacturing method according to 7th Embodiment and 8th Embodiment, in a conventional manufacturing method, in the removal process of an ONO film | membrane and a tunnel oxide film before forming the gate oxide film of a peripheral transistor area | region, it is an element region. The angle is exposed at the end.

As a result, in the conventional manufacturing method, when the peripheral circuit transistor is operated, electric field concentration occurs at an angle of the end portion of the element region, the leakage current of the peripheral circuit transistor increases, and the current consumption of the device increases or the peripheral circuit transistor increases. The sub-threshold characteristic of the discontinuity with respect to the gate voltage caused the peripheral circuit to malfunction, resulting in a drop in product yield.

On the other hand, in the manufacturing method of 7th Embodiment and 8th Embodiment, (1) by performing a wet etching process, an isotropic dry etching process, an oxidation process, or the composite process with respect to the edge part of the element region of a peripheral transistor area | region. In order to increase the curvature of the end of the element region, or (2) Buzz Big is placed in the end of the element region during the element isolation forming process of the peripheral transistor region.

As a result, the dent of the gate electrode at the end of the element region can be suppressed so that the gate electrode does not cause electric field concentration at the end of the element region, the leakage current of the peripheral circuit transistor is suppressed, and the subthreshold current of the peripheral circuit transistor is suppressed. Since the characteristics are improved, the power consumption of the product can be lowered and the yield can be increased.

Moreover, as a method of rounding the angle of the exposed element region end, it is generally known that when the oxidation is carried out in the state of the supply rate, the angle portion is more likely to be oxidized than the flat portion.

Therefore, in place of the processing in each of the above embodiments, before the gate formation of the peripheral circuit transistor, a step of oxidizing under conditions of high temperature and suppressing the supply of oxygen, such as 1000 ° C., 90% nitrogen and 10% oxygen, is added. Even if it is possible, the angle of the exposed end of the element region can be rounded, and the same effect can be obtained even if the gate oxide film forming process itself of the peripheral circuit transistor is used as the oxidation method at the feed rate. It is natural that the same effect can be obtained by combining these methods.

When separating the gate oxide film of the memory cell array region and the peripheral transistor region, rounding the angle of the end of the element region insulated and separated by the buried element isolation region in the peripheral transistor region means that the gate electrode is formed in the element region. It is very effective for suppressing the kink characteristics of the peripheral circuit transistors which are formed in the isolation region.

In the semiconductor device manufacturing method disclosed in the seventh and eighth embodiments, in the manufacture of a semiconductor device in which a part of the gate insulating film is formed before the element isolation forming step, and the remainder of the gate insulating film is formed after the element isolation forming step. Applicable.

By rounding the shape of the end portion of the element region, it is possible to suppress the leakage current and the consumption current in the region where the gate voltage of the transistor is low, and the subthreshold current characteristic is continuous with the gate voltage, The operation of the transistor can be stabilized and the yield of the product can be improved.

Therefore, the seventh and eighth embodiments are applied to, for example, the flash EEPR0M and its manufacture, so that the curvature of the end of the element region in the peripheral transistor region is set larger than the curvature of the end of the element region in the memory cell array region. As a result, the leakage current of the peripheral circuit transistor can be reduced to reduce the power consumption.

Although the present invention has been described based on the above embodiments, the present invention may, for example, include only the control circuit of the memory cell unit, and also the CPU and the like. In the above embodiment, the flash EEPROM has been described as an example. However, the present invention is not limited to this, and various modifications may be employed without departing from the spirit of the invention.

Claims (30)

A semiconductor substrate, A memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed; A peripheral circuit portion on the semiconductor substrate on which a circuit for controlling the memory cell having a floating gate is formed; A plurality of element regions respectively formed in the memory cell portion and the peripheral circuit portion and separated by a plurality of grooves; An insulating film filling the groove; A buzzvik oxide film formed between the element region of the memory cell portion and the floating gate electrode; Buzz big oxide film formed between the element region of the peripheral circuit portion and the gate electrode, and thicker than a buzz big oxide film formed between the element region of the memory cell portion and the floating gate electrode. Nonvolatile semiconductor memory device comprising a. A semiconductor substrate, A memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed; A peripheral circuit portion on the semiconductor substrate on which a circuit for controlling the memory cell is formed; A plurality of element regions respectively formed in the memory cell portion and the peripheral circuit portion and separated by a plurality of grooves; An oxidation resistant film formed on an inner wall of the groove and a side wall of the floating gate electrode in the memory cell portion; An insulating film filling the groove; A gate insulating film formed between the element region of the memory cell portion and the floating gate electrode; A gate insulating film formed between the element region of the peripheral circuit portion and the gate electrode Nonvolatile semiconductor memory device comprising a. The nonvolatile semiconductor memory device according to claim 2, wherein the oxidation resistant film is a silicon nitride film. A semiconductor substrate, A memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed; A peripheral circuit portion on the semiconductor substrate on which a circuit for controlling the memory cell is formed; A plurality of element regions respectively formed in the memory cell portion and the peripheral circuit portion and separated by a plurality of grooves; An oxidation resistant film formed only on the sidewall of the groove and the sidewall of the floating gate electrode in the memory cell portion; An insulating film filling the groove; A gate insulating film formed between the element region of the memory cell portion and the floating gate electrode; A gate insulating film formed between the element region of the peripheral circuit portion and the gate electrode Nonvolatile semiconductor memory device comprising a. The nonvolatile semiconductor memory device according to claim 4, wherein the oxidation resistant film is a silicon nitride film. A semiconductor substrate, A memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed; A peripheral circuit portion on the semiconductor substrate on which a circuit for controlling the memory cell is formed; A plurality of element regions respectively formed in the memory cell portion and the peripheral circuit portion and separated by a plurality of grooves; An insulating film filling the groove; An oxynitride film formed between the element region of the memory cell portion and the floating gate electrode; An oxide film formed between the element region of the peripheral circuit portion and the gate electrode Nonvolatile semiconductor memory device comprising a. A semiconductor substrate, A memory cell portion on the semiconductor substrate on which a plurality of memory cells are formed; A peripheral circuit portion on the semiconductor substrate on which a circuit for controlling the memory cell is formed; A plurality of element regions respectively formed in the memory cell portion and the peripheral circuit portion and separated by a plurality of grooves; An oxidation resistant film formed on at least an inner wall of the groove in the peripheral circuit; An insulating film filling the groove; A gate insulating film formed between the element region of the memory cell portion and the floating gate electrode; A gate insulating film formed between the element region of the peripheral circuit portion and the gate electrode Nonvolatile semiconductor memory device comprising a. 8. The nonvolatile semiconductor memory device according to claim 7, wherein the oxidation resistant film is an oxynitride film. 8. The nonvolatile semiconductor memory device according to claim 7, further comprising an oxidation resistant film formed on an inner wall of the groove in the memory cell portion and a side wall of the floating gate. 10. The nonvolatile semiconductor memory device according to claim 9, wherein the oxidation resistant film formed on the inner wall of the groove and the side wall of the floating gate in the memory cell portion is an oxynitride film. A semiconductor substrate, A memory cell array unit in which a plurality of memory cell transistors are formed in an element region of the semiconductor substrate, and the element region of the memory cell transistor is insulated and separated by a buried element isolation region while facing the gate electrode of the memory cell transistor; A plurality of peripheral circuit transistors are formed in the element region of the semiconductor substrate, and the peripheral transistor portion insulated and separated by the buried element isolation region while the element region of the peripheral circuit transistor faces the gate electrode of the peripheral circuit transistor, The curvature of the element isolation end of the element region of the peripheral circuit transistor is set substantially larger than the curvature of the element isolation end of the element region of the memory cell transistor. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the difference between the height of the flat portion of the element region and the height of the lowest portion of the gate electrode that is higher than that is 4 nm or more. 12. The nonvolatile semiconductor memory device according to claim 11, wherein a bias potential at which a subthreshold current flows is supplied to the peripheral circuit transistor when the operation of the peripheral circuit transistor is in the standby state. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the gate electrode portion of the memory cell transistor is self-aligned with the buried element isolation region in the memory cell array portion. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the memory cell transistor is a memory cell of a nonvolatile semiconductor memory having a floating gate. In the method for manufacturing a nonvolatile semiconductor memory device in which the element region is formed by the groove-type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a polycrystalline silicon layer on the silicon substrate through an insulating film, Forming a device region by self-aligning the polycrystalline silicon layer, the insulating film and the silicon substrate to form a plurality of grooves for device isolation having a bottom portion in the silicon substrate and surrounding the device region; Rounding each end of the device isolation side of the surface on which the device region and the polycrystalline silicon layer face each other by oxidation; Coating only the memory cell portion with an oxidation resistant film, After covering only the memory cell portion with the oxidation resistant film, further oxidation is performed, and in the element region of the peripheral circuit portion, a buzz-like oxide film thicker than the memory cell portion is formed between the end portions of the surfaces where the silicon substrate and the polycrystalline silicon layer face each other. Process A method of manufacturing a nonvolatile semiconductor memory device, comprising: 17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein the oxidation resistant film is a silicon nitride film. 17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein after the further oxidation treatment, an oxidation resistant film covering the memory cell portion is removed. In the method for manufacturing a nonvolatile semiconductor memory device in which the element region is formed by the groove-type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a polycrystalline silicon layer on the silicon substrate through an insulating film, Self-aligning the polycrystalline silicon layer, the insulating film, and the silicon substrate to form an element region, and forming a plurality of grooves for element isolation having a bottom portion surrounding the element region in the silicon substrate; Rounding each end of the face of the device region and the polycrystalline silicon layer opposite to each other by oxidation; Coating only the memory cell portion with an oxidation resistant film, Selectively removing the oxidation resistant film so that the oxidation resistant film is left only on the sidewall of the floating gate electrode and only on the sidewall of the device isolation groove; After the oxidation resistant film is selectively removed, further oxidation is carried out, and in the element region of the peripheral circuit portion, a step of forming a buzzvik-shaped oxide film thicker than the memory cell portion is formed between the end portions of the surfaces of the silicon substrate and the polycrystalline silicon layer facing each other. A method of manufacturing a nonvolatile semiconductor memory device, comprising: 20. The method of manufacturing a nonvolatile semiconductor memory device according to claim 19, wherein the oxidation resistant film is a silicon nitride film. 17. The method of manufacturing a nonvolatile semiconductor memory device according to claim 16, wherein after the further oxidation treatment, an oxidation resistant film covering the memory cell portion is removed. In the method for manufacturing a nonvolatile semiconductor memory device in which the element region is formed by the groove-type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a polycrystalline silicon layer on the silicon substrate through an insulating film, Self-aligning the polycrystalline silicon layer, the insulating film, and the silicon substrate only in the peripheral circuit portion, and forming a first device isolation groove; In the peripheral circuit portion, a step of oxidizing each end portion of the surface where the element region and the first polycrystalline silicon layer face each other, to form a buzzvik oxide film; Self-aligning the polycrystalline silicon layer, the insulating film, and the silicon substrate in the memory cell portion to form a second device isolation groove; After the formation of the second device isolation groove, a step of oxidizing each end of the surface where the device region of the memory cell portion and the surface of the polycrystalline silicon layer oppose each other to form a buzzvik oxide film thinner than the buzzvik oxide film formed in the peripheral circuit portion A method of manufacturing a nonvolatile semiconductor memory device, comprising: In the method for manufacturing a nonvolatile semiconductor memory device in which the element region is formed by the groove-type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming an oxidation resistant film through an insulating film on the silicon substrate; Selectively removing the oxidation resistant film and the insulating film from the memory cell portion; Forming a tunnel oxide film in the memory cell portion and nitriding it to oxynitride the tunnel film; Forming a polycrystalline silicon layer on top of the tunnel oxynitride film in the memory cell section and on the oxidation resistant film in the peripheral circuit section; Self-aligning the polycrystalline silicon and the silicon substrate and forming grooves for device isolation in the memory cell portion and the peripheral circuit portion; A process of forming a buzzvik oxide film at the end of each surface where the device region and the polycrystalline silicon face each other by oxidation after forming the device isolation groove, and forming a buzzvik oxide film thicker than the memory cell portion in the peripheral circuit portion. A method of manufacturing a nonvolatile semiconductor memory device, comprising: In the method for manufacturing a nonvolatile semiconductor memory device in which an element region is formed by groove type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a polycrystalline silicon layer on the silicon substrate through an insulating film, Forming a device isolation groove to self-align the polycrystalline silicon and the silicon substrate to form an element region; A step of rounding an end portion of each surface of the device region and the polycrystalline silicon facing each other by oxidation; Coating only the memory cell portion with a silicon film; Adding a post-coating oxidation of the silicon film and forming a buzzvik oxide film thicker than the memory cell portion between the silicon substrate of the peripheral circuit portion and the end of the opposite surface of the polycrystalline silicon layer; Oxidizing the silicon film covering the memory cell portion A method of manufacturing a nonvolatile semiconductor memory device, comprising: 25. The method of manufacturing a nonvolatile semiconductor memory device according to claim 24, wherein the silicon film covering only the memory cell portion is an amorphous silicon film. In the method for manufacturing a nonvolatile semiconductor memory device in which an element region is formed by groove type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a polycrystalline silicon layer serving as an insulating film and a floating gate on the silicon substrate; Self-aligning the polycrystalline silicon layer and the silicon substrate to form a groove for device isolation; Forming a silicon oxynitride film on the inner wall of the groove and the sidewall of the polycrystalline silicon A method of manufacturing a nonvolatile semiconductor memory device, comprising: 27. The silicon oxynitride film according to claim 26, wherein the step of forming a silicon oxynitride film on the inner wall of the groove and the sidewall of the polycrystalline silicon is performed after the silicon oxide film is formed on the inner wall of the groove and the sidewall of the polycrystalline silicon layer. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that the step of forming a film. A method of manufacturing a nonvolatile semiconductor memory device in which a part of a gate insulating film of a MOS transistor is formed before an element isolation process and the remainder of the gate insulating film is formed after an element isolation formation process. The curvature of the end of the element region of the MOS transistor having the gate insulating film formed after the element isolation forming process is substantially as compared to the curvature of the end of the element region of the MOS transistor having the gate insulating film formed before the element isolation forming process. A method of manufacturing a nonvolatile semiconductor memory device, characterized by forming a MOS transistor so as to be large. In the method for manufacturing a nonvolatile semiconductor memory device in which an element region is formed by groove type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a first gate insulating film for a memory cell transistor on the entire surface of the semiconductor substrate, and forming a polysilicon film and an insulating film thereon; Forming a trench for forming an isolation region in the insulating film, the polysilicon film, the first gate insulating film, and the semiconductor substrate; Removing the first gate insulating film on the end of the element region of the peripheral transistor region after covering the memory cell array region; Oxidizing the surface of the trench and the surface of the portion between the end of the element region in the peripheral transistor region and the polysilicon film thereon; Embedding a buried insulator in the trench and planarizing the entire surface thereof; Removing the insulating film on the polysilicon film; Removing the polysilicon film and the first gate insulating film in the peripheral transistor region, and then forming a second gate insulating film for the peripheral circuit transistor; Forming a stacked gate structure including the polysilicon film as a floating gate in the memory cell array region, and forming a gate electrode on the second gate insulating film in a peripheral transistor region; A process of selectively introducing impurities serving as a source / drain of a transistor in the substrate surface layer portion A method of manufacturing a nonvolatile semiconductor memory device, comprising: In the method for manufacturing a nonvolatile semiconductor memory device in which an element region is formed by groove type isolation and has a memory cell portion having a floating gate and a peripheral circuit portion thereof, Forming a first gate insulating film for a memory cell transistor on the entire surface of the semiconductor substrate, and forming a polysilicon film thereon; Forming a trench for forming an isolation region in the polysilicon film, the first gate insulating film and the semiconductor substrate; Embedding a buried insulator in the trench and planarizing the entire surface thereof; Forming an inter-gate insulating film for insulating the floating gate control gate of the memory cell transistor on the entire substrate; Removing the inter-gate insulating film, the polysilicon film and the first gate insulating film of the side transistor region to expose the device region; Etching the corners of the end portions of the device regions exposed in the peripheral transistor region to form a round shape; Forming a second gate insulating film for the peripheral circuit transistor in the peripheral transistor region; Forming a stacked gate structure including the polysilicon film as a floating gate in the memory cell array region, and forming a gate electrode on the second gate insulating film in a peripheral transistor region; A process of selectively introducing impurities serving as a source / drain of a transistor in the substrate surface layer portion A method of manufacturing a nonvolatile semiconductor memory device, comprising: