KR100881847B1 - Method For Manufacturing Semiconductor Memory Device - Google Patents

Abstract

The present invention provides a method of manufacturing a semiconductor memory device. According to this, after the multilayer insulating film is laminated on the cell portion and the peripheral semiconductor substrate for the flash memory, the multilayer insulating film is etched by a part thickness. A trench is then formed in the cell portion and the peripheral portion using the same photolithography process. Thus, the trench in the cell portion is formed shallower than the trench in the peripheral portion.

Accordingly, the present invention can simplify the trench formation process since the trenches of the cell portion and the peripheral portion are simultaneously formed at different depths.

Description

Method for manufacturing semiconductor memory device {Method For Manufacturing Semiconductor Memory Device}             

1 and 2 are plan and main cross-sectional views showing cells of a typical flash memory.

3 to 7 are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device in which trenches are formed at different depths in the cell and peripheral portions of a flash memory.

In general, semiconductor memory devices are classified into random access memory (RAM) and read only memory (ROM). The RAM is a volatile data that is already erased as time passes, such as dynamic random access memory (DRAM) and static random access memory (SRAM). Once the ROM has stored the data, it remains in that state, but the input and output of the data is slow. The ROM is subdivided into a ROM, a programmable ROM (PROM), an erasable PROM (EPROM), and an electrically erasable PROM (EEPROM). Recently, the demand for EEPROM that can electrically program or erase data is increasing rapidly. The cell of the flash memory having the EEPROM or the batch erase function has a stack-type gate structure in which a floating gate and a control gate are stacked.

The flash memory has a NAND type in which 16 cells are connected in series to form a unit string, and the unit string is connected in parallel between a bit line and a ground line, and each cell is a bit line. It is divided into NOR type which is connected in parallel between and ground line. The NAND flash memory is advantageous for high integration and the NOR flash memory is advantageous for high speed operation. The Noah-type flash memory uses a common source method. That is, one contact is formed every 16 cells, and the source lines of the 16 cells are generally connected to an n + diffusion layer.

In recent years, shallow trench isolation (STI) technology has been used as an isolation process for high integration of semiconductor devices. In addition, the cell size of the flash memory is being reduced by the self aligned source (SAS) technology. The STI technology and the SAS technology are essential processes for shrinking the cells of the flash memory in the X and Y axis directions.                         

In a general flash memory using the STI technique and the SAS technique, as shown in FIG. 1, the drain D and the source S of each cell are disposed with a common word line WL interposed therebetween. The drain D and the source S of the cell are electrically isolated from each other by an insulating film in a trench (not shown) formed in the isolation region ISO. In addition, as each source S is shown in FIG. 2, the insulating film in the trench 20 of the isolation region ISO for the common source is removed and ion implantation is performed on the surface of the substrate 10 in the trench 20. The ion implantation layer 30 is electrically connected to each other.

However, when the STI technology and the SAS technology are applied together in the manufacture of the flash memory, the source resistance per cell is increased as compared with the case of applying a local oxidation of silicon (LOCOS) process and the SAS technology. As the source resistance per cell increases in this way, since one source contact is formed every 16 cells, the back bias is changed by the voltage drop between the first and eighth cells. As a result, errors are likely to occur during read operations.

Further, since the peripheral portion of the flash memory uses a high voltage of 12V and the cell portion uses a low voltage of 5 to 9V, the depth of the trench becomes deeper as the flash memory becomes finer. This further increases the source resistance.

However, in the related art, although the voltage of the cell portion is lower than that of the peripheral portion, the trench of the cell portion is formed as deep as the trench of the peripheral portion, so that there is a limit to reducing the source resistance.

Recently, in order to solve this problem, a method of forming the trench of the cell portion shallower than the trench of the peripheral portion has begun to be used. However, in this method, since the photolithography process of forming the trench of the cell portion and the photolithography process of forming the trench of the periphery are performed separately, the photolithography process is not only complicated, but also an overlay problem is likely to occur. .

Accordingly, it is an object of the present invention to simplify the process of forming trenches of different depths in the cell and peripheral portions of the flash memory.

The semiconductor memory device manufacturing method according to the present invention for achieving the above object is

Forming a multilayer insulating film in the first region and the second region of the semiconductor substrate; Forming a total thickness of the multilayer insulating film of the second region to be smaller than the total thickness of the multilayer insulating film of the first region using a photolithography process; And simultaneously forming first and second trenches of different depths in the isolation regions of the first region and the second region using a photolithography process.

Preferably, the multilayer insulating film can be formed in a stacked structure of a first oxide film, a nitride film, and a second oxide film while going from top to bottom.

Preferably, the first oxide film may be laminated to a thickness of 30 to 150 GPa, the nitride film may be laminated to a thickness of 500 to 3000 GPa, and the second oxide film may be laminated to a thickness of 300 to 3000 GPa. In this case, by etching the second oxide film of the second region, the total thickness of the multilayer insulating film of the second region may be made thinner than the total thickness of the multilayer insulating film of the first region.

Preferably, the multilayer insulating film may be formed in a stacked structure of a first oxide film and a nitride film while going from top to bottom. In this case, the nitride film of the second region may be etched by a partial thickness to make the total thickness of the multilayer insulating film of the second region thinner than the total thickness of the multilayer insulating film of the first region.

Preferably, the first region may be divided into a cell portion of the flash memory, and the second region may be divided into a peripheral portion of the flash memory.

Hereinafter, a method of manufacturing a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

3 to 7 are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor memory device according to the present invention.

3 and 4, first, on the semiconductor substrate 10, for example, the cell portion 11 of the flash memory, which is the first region of the P-type single crystal silicon substrate, and the peripheral portion 12 of the flash memory, which is the second region. A first oxide film 13 as a sacrificial film is laminated to a thickness of 30 to 150 kPa, and a nitride film 15 is stacked to a thickness of 500 to 3000 kPa on the first oxide film 13, and on the nitride film 15. The second oxide film 17 is laminated to a thickness of 300 to 3000 GPa. Here, the second oxide film 17 is a TEOS oxide film laminated by a plasma enhanced chemical vapor deposition process.

Subsequently, the photoresist pattern PR1 is formed only on the cell portion 11 of the semiconductor substrate 10 by using a photolithography process, and the pattern of the photoresist film PR1 is used as an etch mask to form the pattern of the peripheral portion 12. The nitride film 15 is exposed by dry etching the oxide film 17. Accordingly, the insulating film of the cell portion 11 is composed of the first oxide film 13, the nitride film 15, and the second oxide film 17, and the insulating film of the peripheral portion 12 includes the first oxide film 13 and the nitride film 15. Since the total thickness of the insulating film of the cell portion 11 is greater than the total thickness of the insulating film of the peripheral portion 12.

Referring to FIG. 5, the isolation region is then removed to form a trench in the isolation region of the cell portion 11 and the peripheral portion 12 of the semiconductor substrate 10 after removing the pattern of the photoresist film PR1 of FIG. 4. A pattern of the photosensitive film PR2 having a window exposing the light is formed in the cell portion 11 and the peripheral portion 12 together.

Referring to FIG. 6, the second oxide film 17 and the nitride film of the cell portion 11 are then subjected to dry etching, for example, reactive ion etching, using the photoresist film PR2 as an etching mask and having anisotropic etching characteristics. 15 and the first oxide film 13 are sequentially etched. In this case, the reactive ion etching process is performed based on etching conditions of an insulating film such as an oxide film or a nitride film.

In addition, in the peripheral portion 12, the nitride film 15 and the first oxide film 13 are etched, and the semiconductor substrate 10 is etched by a partial depth. This is because the total thickness of the insulating film of the cell part 11 is larger than the total thickness of the insulating film of the peripheral part 12.

Subsequently, as shown in FIG. 7, the reactive ion etching process is performed based on the etching conditions of silicon. The first trench 19a of the cell part 11 may have a desired depth D1, for example, a depth of 1500˜2500 μs. Etch with. At this time, the second trench 19b of the peripheral portion 12 is etched to a depth D2 of about 3500 kPa.

Therefore, in the present invention, the first and second trenches 19a and 19b can be formed at different depths at the same time.

Then, the insulating insulating film is buried and planarized in the first and second trenches by using a conventional publicly known technique, and then word lines and sources / drains are formed in the cell portion and the peripheral portion, and the first region of the region for the common source is formed. The insulating film in the trench is selectively etched and ion implanted with impurities for a common source on the exposed surface of the first trench. For the convenience of description, since it is less relevant to the gist of the present invention, a detailed description thereof will be omitted.

Therefore, the present invention simultaneously forms different trenches in the cell portion and the peripheral portion for the flash memory, thereby simplifying the trench formation process. In addition, since the trench of the cell portion is formed to be shallower than the trench of the peripheral portion, the source resistance can be reduced. As a result, the operation of the program and read of the flash memory can be maintained stably.

Meanwhile, the present invention may comprise the multilayer insulating film as a first oxide film and a nitride film, and by etching the nitride film of the peripheral part by a part thickness, the total thickness of the insulating film of the peripheral part may be made thinner than the total thickness of the insulating film of the cell part. Do. For convenience of description, description thereof will be omitted in order to avoid duplication of description.

As described in detail above, in the method of manufacturing a semiconductor memory device according to the present invention, a multilayer insulating film is laminated on a cell portion and a peripheral semiconductor substrate for a flash memory, and the multilayer insulating film is etched by a partial thickness. A trench is then formed in the cell portion and the peripheral portion using the same photolithography process. Thus, the trench in the cell portion is formed shallower than the trench in the peripheral portion.

Accordingly, the present invention can simplify the trench formation process since the trenches of the cell portion and the peripheral portion are simultaneously formed at different depths.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (7)

Forming a multilayer insulating film by laminating a first oxide film, a nitride film, and a second oxide film on the first region and the second region of the semiconductor substrate; Removing the second oxide film of the second region by using a first photolithography process to form a total thickness of the multilayer insulating film of the second region to be smaller than the total thickness of the multilayer insulating film of the first region; By simultaneously applying a second photolithography process, the second oxide film, the nitride film, and the first oxide film of the isolation region in the first region are etched, and the nitride film, the first oxide film, and the removed second portion of the isolation region in the second region are etched. Etching the semiconductor substrate corresponding to an oxide thickness; By simultaneously applying a third photolithography process to etch the exposed substrate of the first region and the partially etched substrate of the second region, first and second having different depths in the isolation region of the first region and the second region. A method of manufacturing a semiconductor memory device comprising forming a trench. delete The semiconductor according to claim 1, wherein the first oxide film is laminated to a thickness of 30 to 150 GPa, the nitride film is laminated to a thickness of 500 to 3000 GPa, and the second oxide film is laminated to a thickness of 300 to 3000 GPa. Method of manufacturing a memory device. delete Stacking a first oxide film and a nitride film on the first region and the second region of the semiconductor substrate to form a multilayer insulating film; Forming a total thickness of the multilayer insulating film of the second region to be smaller than the total thickness of the multilayer insulating film of the first region by removing a portion of the nitride film of the second region using a first photolithography process; By simultaneously applying a second photolithography process, the nitride film and the first oxide film of the isolation region of the first region are etched, and the thickness of the nitride film, the first oxide film and the partially removed nitride film of the isolation region of the second region is etched. Etching the semiconductor substrate; By simultaneously applying a third photolithography process to etch the exposed substrate of the first region and the partially etched substrate of the second region, first and second having different depths in the isolation region of the first region and the second region. A method of manufacturing a semiconductor memory device comprising forming a trench. delete The method of claim 1, wherein the first region is divided into a cell portion of a flash memory, and the second region is divided into a peripheral portion of a flash memory.

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