KR100521378B1 - Gate Insulator Of Semiconductor Device And Method Of Forming The Same - Google Patents

Abstract

A gate insulating film of a semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate insulating film pattern and a first conductive film pattern sequentially stacked on a high voltage region of a semiconductor substrate, and a second gate insulating film pattern and a first conductive film pattern sequentially stacked on a low voltage region. And a third gate insulating film pattern and a second conductive film pattern sequentially stacked on the cell region. In this case, the third gate insulating film pattern is thicker than the second gate insulating film pattern, and the first gate insulating film pattern is thicker than the third gate insulating film pattern.

Description

Gate Insulator Of Semiconductor Device And Method Of Forming The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a gate insulating film of a flash memory and a method of forming the same.

The memory semiconductor device may be classified into a volatile memory device and a nonvolatile memory device according to whether or not the stored information may be maintained when power is not supplied. Recently, a widely used flash memory device is a semiconductor device representing the nonvolatile memory device. The flash memory uses physical phenomena caused by high potential differences, such as FN tunneling, to change the stored information. In order to generate such a high potential difference, the flash memory device includes high voltage transistors having a thick gate insulating layer in a peripheral circuit region.

Meanwhile, the memory semiconductor device includes a plurality of cell transistors disposed in a cell array region and functional circuits disposed in a peripheral circuit region for operating the cell transistors. The functional circuit includes not only the high voltage transistors but also low voltage transistors having a gate insulating film thinner than the high voltage transistors. As a result, the flash memory device may include a high voltage transistor, a low voltage transistor, and a cell transistor, and the transistors may include gate insulating layers having different thicknesses. However, according to the related art, the low voltage transistor and the cell transistor are formed together to simplify the process.

1 to 5 are process cross-sectional views illustrating a method of manufacturing a flash memory according to the prior art.

Referring to FIG. 1, a semiconductor substrate 10 having a high voltage region HV, a low voltage region LV, and a cell region CELL is prepared. The first gate insulating layer 20 is formed on the entire surface of the semiconductor substrate 10. The first gate insulating film 20 may be a silicon oxide film formed through a thermal oxidation process. Thereafter, the first gate insulating layer 20 is patterned to expose the semiconductor substrate 10 of the low voltage region LV and the cell region CELL.

Referring to FIG. 2, a second gate insulating layer 30 is formed on the semiconductor substrate 10 exposed in the low voltage region LV and the cell region CELL. The second gate insulating film 30 is also preferably a silicon oxide film formed through a thermal oxidation process. Thus, the silicon oxide film may be further formed on the first gate insulating film 20. Thereafter, the polycrystalline silicon film 40, the buffer oxide film 50, and the silicon nitride film 60 are sequentially formed on the entire surface of the semiconductor substrate including the second gate insulating film 30.

Referring to FIG. 3, the silicon nitride film 60, the buffer oxide film 50, and the polycrystalline silicon film 40 are sequentially patterned, and the polycrystalline silicon pattern 45 sequentially stacked on the semiconductor substrate 10. The buffer oxide film pattern 55 and the silicon nitride film pattern 65 are formed. The polycrystalline silicon pattern 45, the buffer oxide film pattern 55, and the silicon nitride film pattern 65 form a trench mask pattern according to the present invention.

Thereafter, an anisotropic etching process using the silicon nitride film pattern 65 as an etching mask is performed to etch the first gate insulating film 20, the second gate insulating film 30, and the semiconductor substrate 10. Accordingly, the trench 15 defining the active region is formed around the trench mask pattern. A first gate insulating layer pattern 25 and a second gate insulating layer pattern 35 are formed between the active region and the polycrystalline silicon pattern 45. The first gate insulating layer pattern 25 is disposed in the high voltage region HV, and the second gate insulating layer pattern 35 is disposed in the low voltage region LV and the cell region CELL.

Referring to FIG. 4, after forming the trench 15, an isolation layer 70 is formed on the entire surface of the resultant trench. The device isolation film 70 is formed of at least one of a silicon oxide film and a silicon nitride film. The device isolation layer 70 is formed on the entire surface of the semiconductor substrate including the trench mask pattern while filling the trench 15. In addition, before the device isolation layer 70 is formed, a thermal oxidation process may be further performed to form another silicon oxide layer on the inner wall of the trench 15.

Referring to FIG. 5, the device isolation layer 70 is etched to expose the top surface of the polycrystalline silicon pattern 45. The etching of the device isolation layer 70 may further include planar etching using a chemical mechanical polishing technique.

According to the conventional method described above, the polycrystalline silicon pattern 45 and the gate insulating layers 25 and 35 constituting the trench mask pattern are used as gate electrodes and gate insulating layers of transistors, respectively. The prior art method described above is commonly referred to as a self-aligned shallow trench isolation (SA-STI) process.

According to the SA-STI process, the process may be simplified, but the gate insulating layers 25 and 35 formed in the low voltage region LV and the cell region CELL have the same thickness. However, as the operation speed of the semiconductor device is further increased, the low voltage transistors disposed in the peripheral circuit region must also be increased. To this end, it is necessary to form the gate insulating film of the low voltage transistor, that is, the second gate insulating film pattern 35 of the low voltage region LV as thin as possible. Such thin formation of the gate insulating film of the low voltage transistor is further required in a NOR type flash memory device having a high operating speed as a main advantage. However, the flash memory uses a gate insulating film of the cell region as an insulating layer for retaining information stored in the floating gate electrode. Accordingly, when the second gate insulating layer pattern 35 formed in the low voltage region LV is thin, the information retention characteristic is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of implementing fast operating speeds and stable information retention characteristics.

Another object of the present invention is to provide a method of forming a semiconductor device having a gate insulating film having a different thickness.

Another object of the present invention is to provide a method of forming gate insulating films having different thicknesses using SA-STI technology.

In order to achieve the above technical problem, the present invention provides a semiconductor device having gate insulating films of different thicknesses. The semiconductor device includes a first gate insulating film pattern and a first conductive film pattern sequentially stacked on the high voltage region of the semiconductor substrate, and the second gate insulating film pattern and the first conductive film sequentially stacked on the low voltage region of the semiconductor substrate. And a third gate insulating film pattern and a second conductive film pattern sequentially stacked on the cell region of the semiconductor substrate. In this case, the third gate insulating film pattern is thicker than the second gate insulating film pattern, and the first gate insulating film pattern is thicker than the third gate insulating film pattern.

According to a preferred embodiment of the present invention, the first, second and third gate insulating film patterns are silicon oxide films. In addition, the first conductive layer pattern and the second conductive layer pattern are both polycrystalline silicon, and have different thicknesses or different impurity concentrations.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a semiconductor device performing a SA-STI process to have a gate insulating film having a different thickness. The method includes preparing a semiconductor substrate having a high voltage region, a low voltage region, and a cell region, and then sequentially forming a lower trench mask film and an upper trench mask film. The lower trench mask layer may include a first gate insulating film, a first conductive film, and a first insulating film sequentially stacked in a high voltage region of the semiconductor substrate, and a second gate insulating film, a first conductive film, and a first insulating film sequentially stacked in the low voltage region. And a third gate insulating film, a second conductive film, and a second insulating film that are sequentially stacked on the cell region. In this case, the third gate insulating film is thicker than the second gate insulating film, and the first gate insulating film is thicker than the third gate insulating film.

In an embodiment, the first gate insulating film, the second gate insulating film, and the third gate insulating film are silicon oxide films formed by thermally oxidizing the semiconductor substrate. In addition, the first conductive film and the second conductive film are polycrystalline silicon, which may have different characteristics from at least one of thickness and impurity concentration. In addition, the first insulating film and the second insulating film may be formed of at least one material selected from a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The upper trench mask layer may be formed of at least one material selected from a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

In example embodiments, the forming of the lower trench mask layer may include forming a first gate insulating layer covering the semiconductor substrate of the high voltage region and the cell region while exposing the semiconductor substrate of the low voltage region. It is preferable to include forming a second gate insulating film on the semiconductor substrate in the low voltage region. Thereafter, a first conductive film and a first insulating film are sequentially formed on the entire surface of the semiconductor substrate including the first and second gate insulating films, and the first insulating film, the first conductive film, and the first gate insulating film are patterned to form the first insulating film. After exposing the semiconductor substrate of the cell region, a third gate insulating film is formed on the exposed semiconductor substrate of the cell region. Subsequently, a second conductive film and a second insulating film are sequentially formed on the front surface of the semiconductor substrate including the third gate insulating film, and patterned to expose the upper surface of the first insulating film in the high voltage region and the low voltage region.

According to an exemplary embodiment of the present invention, after the upper trench mask layer is formed, a step of forming a trench mask pattern exposing predetermined regions of the semiconductor substrate by patterning the upper and lower trench mask layers in order may be further performed. Can be. Subsequently, an anisotropic etching of the exposed semiconductor substrate using the trench mask pattern as an etching mask forms a trench defining an active region, and then an isolation layer is formed on the entire surface of the semiconductor substrate on which the trench is formed. Subsequently, the device isolation layer is etched until the top surfaces of the first and second conductive layers are exposed, thereby forming a device isolation layer pattern filling the trench.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. If it is also mentioned that the layer is on another layer or substrate it may be formed directly on the other layer or substrate or a third layer may be interposed therebetween.

6 to 14 are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 6, a semiconductor substrate 100 including a high voltage region HV, a low voltage region LV, and a cell region CELL is prepared. The first gate insulating layer 110 is formed on the upper surface of the semiconductor substrate 100. The first gate insulating layer 110 may be a silicon oxide layer formed by thermally oxidizing exposed silicon atoms of the semiconductor substrate 100.

The first photoresist pattern 120 exposing the low voltage region LV is formed on the first gate insulating layer 110. The first gate insulating layer 110 is etched using the first photoresist pattern 120 as an etch mask to expose the semiconductor substrate 100 in the low voltage region LV. The etching of the first gate insulating layer 110 may be performed by an isotropic etching method in order to minimize etching damage.

Meanwhile, before forming the first gate insulating layer 110, a plurality of ion implantation processes for forming predetermined well regions may be further performed.

Referring to FIG. 7, the top surface of the first gate insulating layer 110 is exposed by removing the first photoresist pattern 120. Thereafter, a second gate insulating layer 112 is formed in the exposed semiconductor substrate 100 in the low voltage region LV. The second gate insulating layer 112 may be thinner than the first gate insulating layer 110.

On the other hand, the second gate insulating film 112 is preferably a silicon oxide film formed through a thermal oxidation process. As a result, the silicon oxide layer formed may increase the thickness of the first gate insulating layer 110. In consideration of this increase in thickness, the first gate insulating layer 110 is formed.

The first conductive layer 130 and the first insulating layer 140 are sequentially formed on the entire surface of the semiconductor substrate on which the second gate insulating layer 112 is formed. The first conductive film 130 and the first insulating film 140 are preferably polycrystalline silicon and silicon oxide film, respectively.

Referring to FIG. 8, a second photoresist pattern 122 is formed on the first insulating layer 140 to expose the cell region CELL and cover the high voltage region HV and the low voltage region LV. . Thereafter, the first insulating layer 140 and the first conductive layer 130 using the second photoresist pattern 122 as an etching mask until the semiconductor substrate 100 of the cell region CELL is exposed. And the first gate insulating layer 110 are sequentially etched. In this case, in order to minimize etching damage, the first gate insulating layer 110 may be etched using an isotropic etching method. In the etching of the first insulating layer 140 and the first conductive layer 130, an isotropic etching method or anisotropic etching method may be used.

Referring to FIG. 9, the second photoresist pattern 122 is removed to expose the top surface of the first insulating layer 140 in the high voltage and low voltage regions. Thereafter, a third gate insulating layer 114 is formed on the exposed semiconductor substrate 100 of the cell region CELL.

According to an exemplary embodiment of the present invention, the third gate insulating layer 114 is thinner than the first gate insulating layer 110 and thicker than the second gate insulating layer 112. For example, the thicknesses of the first gate insulating film 110, the second gate insulating film 112, and the third gate insulating film 114 are preferably 150 ns, 50 ns, and 100 ns, respectively.

After the third gate insulating layer 114 is formed, the second conductive layer 150 and the second insulating layer 160 are sequentially formed on the entire surface of the resultant. The second conductive layer 150 and the second insulating layer 160 may be formed of the same material as the first conductive layer 130 and the first insulating layer 140, respectively. That is, the second conductive film 150 and the second insulating film 160 are preferably a polycrystalline silicon film and a silicon oxide film, respectively. In addition, the first conductive layer 130 and the second conductive layer 150 may be formed to have the same thickness and the same impurity concentration as each other, and the first insulating layer 140 and the second insulating layer 160 It may be of the same thickness and of the same composition. The first insulating layer 140 and the second insulating layer 160 may be formed of a silicon oxynitride layer or a silicon nitride layer.

Referring to FIG. 10, a third photoresist pattern 124 is formed on the second insulating layer 160 to cover the cell region CELL and expose the high voltage region HV and the low voltage region LV. . The second insulating layer 160 and the second conductive layer 150 are etched using the third photoresist pattern 124 as an etching mask until the first insulating layer 140 is exposed.

Accordingly, referring to the result formed on the semiconductor substrate 100, the first gate insulating layer 110, the first conductive layer 130, and the first insulating layer 140 are sequentially stacked in the high voltage region HV. In the low voltage region LV, the second gate insulating layer 112, the first conductive layer 130, and the first insulating layer 140 are sequentially stacked. In addition, a third gate insulating layer 114, a second conductive layer 150, a second insulating layer 160, and a third photoresist pattern 124 are sequentially stacked on the cell region CELL.

Referring to FIG. 11, after the third photoresist pattern 124 is removed to expose the first insulating layer 140 and the second insulating layer 160, the upper trench mask layer 170 is formed on the entire surface of the resultant. ). The upper trench mask layer 170 is a material layer used as an etching mask during a subsequent front anisotropic etching process for trench formation.

Since the trench is typically formed deep to a depth of 1000 to 4000 microns, the upper trench mask layer 170 is recessed by a predetermined thickness during etching thereof. Accordingly, when the thickness of the upper trench mask layer 170 is thin, etching damage may occur to the gate electrode. In order to minimize such etching damage, the upper trench mask layer 170 is formed of a material having high density and etching selectivity with respect to the semiconductor substrate 100. For example, the upper trench mask layer 170 may be formed of a silicon nitride layer, and a silicon oxide layer and / or a silicon oxynitride layer may be further used.

Referring to FIG. 12, a fourth photoresist pattern 126 defining an active region is formed on the upper trench mask layer 170. The material layers under the upper trench mask layer 170 are anisotropically etched using the fourth photoresist pattern 126 as an etching mask until the upper surface of the semiconductor substrate 100 is exposed.

Accordingly, the first gate insulating layer pattern 111, the first conductive layer pattern 135, the first insulating layer pattern 145, and the upper trench mask pattern are sequentially stacked on the semiconductor substrate 100 in the high voltage region HV. 175 is disposed. In addition, the second gate insulating layer pattern 113, the first conductive layer pattern 135, the first insulating layer pattern 145, and the upper trench mask pattern 175 are disposed in the low voltage region LV. In addition, the third gate insulating layer pattern 115, the second conductive layer pattern 155, the second insulating layer pattern 165, and the upper trench mask pattern 175 are disposed in the cell region CELL. The fourth photoresist pattern 126 is disposed on the upper trench mask pattern 175.

Referring to FIG. 13, the fourth photoresist pattern 126 is removed to expose the top surface of the upper trench mask pattern 175. Thereafter, the semiconductor substrate 100 is anisotropically etched using the upper trench mask pattern 175 as an etching mask, thereby forming a trench 105 defining an active region around the upper trench mask pattern 175. . Subsequently, an isolation layer 180 filling the trench 105 is formed on the entire surface of the semiconductor substrate including the trench 105. The device isolation layer 180 may be formed of a silicon oxide layer, and at least one of a silicon nitride layer and a silicon oxynitride layer may be further used.

Before the device isolation layer 180 is formed, a thermal process for healing an etch damage occurring in the etching process for forming the trench may be further performed. The thermal oxidation process may be further performed to form a silicon oxide film on the inner wall of the trench 105. It may be. In addition, as is commonly known, before forming the device isolation layer 180, a liner layer covering the inner wall of the trench 105 may be further formed. The liner film is preferably formed of a silicon nitride film.

Referring to FIG. 14, the device isolation layer 180 is etched on the entire surface until the upper surfaces of the first and second conductive layer patterns 135 and 155 are exposed. The etching the entire surface of the device isolation layer 180 may include a planarization etching process using a chemical mechanical polishing technique. The planarization etching process may be performed until the upper surface of the upper trench mask pattern 175 is exposed. Accordingly, the device isolation layer 180 is etched to form the device isolation layer pattern 185 filling the trench 105.

Subsequently, the upper trench mask pattern 175 and the lower portions of the first and second insulating layer patterns 165 are sequentially removed to thereby remove the first conductive layer pattern 135 and the second conductive layer pattern 155. Expose the top surface. As described above, the first conductive layer pattern 135 is disposed in the high voltage region HV and the low voltage region LV, and the second conductive layer pattern 155 is disposed in the cell region CELL.

Referring to FIG. 14, a semiconductor device according to an exemplary embodiment of the present invention will be described. The semiconductor device according to the present invention includes gate insulating films having three different thicknesses. The first gate insulating layer pattern 111 disposed in the high voltage region HV of the semiconductor substrate 100 is the thickest, and the second gate insulating layer pattern 113 disposed in the low voltage region LV is the thinnest. In addition, the third gate insulating layer pattern 115 disposed in the cell region Cell of the semiconductor substrate 100 is thinner than the first gate insulating layer pattern 111 and thicker than the second gate insulating layer pattern 113. According to one preferred embodiment of the present invention, the thicknesses of the first, second and third gate insulating film patterns 111, 113, and 115 are, in turn, approximately 150, 50, and 100 μs.

The first conductive layer pattern 135 and the second conductive layer pattern 155 are disposed on the gate insulating layer patterns 111, 113, and 115. Preferably, the first and second conductive film patterns 135 and 155 are all polycrystalline silicon. In this case, the first conductive layer pattern 135 is disposed in the high voltage region HV and the low voltage region LV, and the second conductive layer pattern 155 is disposed in the cell region CELL. That is, the first conductive layer pattern 135 is formed on the first and second gate insulating layer patterns 111 and 113, and the second conductive layer pattern 155 is the third gate insulating layer pattern ( 115) is formed on top.

A trench 105 is disposed in the semiconductor substrate 100 around the gate insulating layer patterns 111, 113 and 115 and the conductive layer patterns 135 and 155 formed thereon. The trench 105 is filled by the device isolation layer pattern 185. The device isolation layer pattern 185 may be at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

According to the present invention, there is provided a method of manufacturing a semiconductor device such that the gate insulating films have three different thicknesses. That is, the gate insulating film of the cell transistor may be formed thinner than the gate insulating film of the high voltage transistor and thicker than the gate insulating film of the low voltage transistor. Accordingly, the high voltage transistor has a gate insulating film of sufficient thickness to withstand the high voltage, the cell transistor has a gate insulating film of sufficient thickness to have stable information retention characteristics, and the low voltage transistor has a gate insulating film having a thickness suitable for fast operation speed. . As a result, it is possible to manufacture a semiconductor device having a high operating speed and capable of stably maintaining the stored information.

1 through 5 are process cross-sectional views illustrating a prior art method for forming a gate insulating film of a flash memory.

6 through 14 are cross-sectional views illustrating a method of forming a gate insulating film of a flash memory and a structure thereof according to an exemplary embodiment of the present invention.

Claims (14)

Preparing a semiconductor substrate having a high voltage region, a low voltage region, and a cell region; A first gate insulating film, a first conductive film and a first insulating film sequentially stacked on the semiconductor substrate in the high voltage region; A second gate insulating film, a first conductive film and a first insulating film sequentially stacked on the semiconductor substrate in the low voltage region; Forming a lower trench mask film including a third gate insulating film, a second conductive film, and a second insulating film sequentially stacked on the semiconductor substrate in the cell region; Forming an upper trench mask layer covering the lower trench mask layer; Patterning the upper and lower trench mask layers in order to form a trench mask pattern exposing predetermined regions of the semiconductor substrate; Anisotropically etching the exposed semiconductor substrate using the trench mask pattern as an etch mask to form a trench defining an active region; Forming an isolation layer on the entire surface of the semiconductor substrate on which the trench is formed; And Etching the device isolation layer until the upper surfaces of the first and second conductive layers are exposed, thereby forming a device isolation layer pattern filling the trench; And the third gate insulating film is thicker than the second gate insulating film, and the first gate insulating film is thicker than the third gate insulating film. The method of claim 1, And the first gate insulating film, the second gate insulating film and the third gate insulating film are silicon oxide films formed by thermally oxidizing the semiconductor substrate. The method of claim 1, And the first conductive film and the second conductive film are formed of polycrystalline silicon. The method of claim 1, And the first conductive film and the second conductive film are different from each other in at least one of thickness and impurity concentration. The method of claim 1, And the first insulating film and the second insulating film are formed of at least one material selected from a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The method of claim 1, And the upper trench mask layer is formed of at least one material selected from a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. The method of claim 1, Forming the lower trench mask layer Forming a first gate insulating film covering the semiconductor substrate in the high voltage region and the cell region while exposing the semiconductor substrate in the low voltage region; Forming a second gate insulating film on the exposed low voltage semiconductor substrate; Sequentially forming a first conductive film and a first insulating film on an entire surface of the semiconductor substrate including the first and second gate insulating films; Patterning the first insulating film, the first conductive film, and the first gate insulating film to expose the semiconductor substrate in the cell region; Forming a third gate insulating film on the semiconductor substrate in the exposed cell region; Sequentially forming a second conductive film and a second insulating film on an entire surface of the semiconductor substrate including the third gate insulating film; And Patterning the second insulating film and the second conductive film to expose an upper surface of the first insulating film in the high voltage region and the low voltage region. delete Forming a first gate insulating film on an entire surface of the semiconductor substrate having a high voltage region, a low voltage region, and a cell region; Patterning the first gate insulating layer to expose the semiconductor substrate in the low voltage region; Forming a second gate insulating film thinner than the first gate insulating film on the exposed low voltage semiconductor substrate; Sequentially forming a first conductive film and a first insulating film on an entire surface of the semiconductor substrate including the second gate insulating film; Patterning the first insulating film, the first conductive film, and the first gate insulating film to expose the semiconductor substrate in the cell region; Forming a third gate insulating film on the semiconductor substrate in the exposed cell region that is thinner than the first gate insulating film and thicker than the second gate insulating film; Sequentially forming a second conductive film and a second insulating film on an entire surface of the semiconductor substrate including the third gate insulating film; Patterning the second insulating film and the second conductive film to expose an upper surface of the first insulating film in the high voltage region and the low voltage region; Forming an upper trench mask layer covering the first insulating layer exposed in the high voltage region and the low voltage region and the second insulating layer exposed in the cell region; Etching the upper trench mask layer to form an upper trench mask pattern; By using the upper trench mask pattern as an etching mask, the first insulating layer, the first conductive layer, and the first gate insulating layer are sequentially patterned in the high voltage region to expose the semiconductor substrate, and the first layer is exposed in the low voltage region. Patterning the first insulating film, the first conductive film, and the second gate insulating film in order to expose the semiconductor substrate, and sequentially patterning the second insulating film, the second conductive film, and the third gate insulating film in the cell region. Exposing the semiconductor substrate; Anisotropically etching the exposed semiconductor substrate using the upper trench mask pattern as an etch mask to form a trench defining an active region; Forming an isolation layer on the entire surface of the semiconductor substrate on which the trench is formed; And And etching the device isolation layer until the upper surfaces of the first and second conductive layers are exposed to form a device isolation layer pattern filling the trench. The method of claim 9, And the first conductive film and the second conductive film are formed of polycrystalline silicon. The method of claim 9, And the first conductive film and the second conductive film are different from each other in at least one of thickness and impurity concentration. delete delete delete