JP2009252820A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an oxidant from oxidizing a part below a polysilicon film constituting a floating gate electrode as much as possible in oxidation processing after gate processing. <P>SOLUTION: A method of manufacturing a semiconductor device includes the stages of: laminating and forming a gate insulating film 5, a polysilicon film 6 and a silicon nitride film 10 on a semiconductor substrate 1; forming a groove 4 for element isolation by dry etching; depositing a first oxide film 9 of high density by HDP-CVD to be buried in the groove 4 for element isolation, namely, depositing the first oxide film 9 to be buried in the groove 4 for element isolation of a memory cell portion such that an upper surface thereof is above an active region 2 of the semiconductor substrate 1 and a part over a trench 4 is not covered; burying a second oxide film 12 having lower density than the first oxide film in the groove 4 for element isolation; flattening the first and second oxide films using the silicon nitride film 10 as a stopper; and removing the second oxide film 12 buried in the groove 4 for element isolation of the memory cell portion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device configured to embed a high density oxide film and a low density oxide film in an element isolation trench.

  In a semiconductor device forming an integrated circuit, miniaturization has been advanced to increase the degree of integration. One element of the miniaturization is the reduction of the element isolation region. In recent years, STI (Shallow Trench Isolation) technology has been introduced, and element isolation with a narrow width has become possible. However, if the insulating film is poorly embedded in a trench formed in a semiconductor substrate, the insulation characteristics are affected. Will be affected.

  As a method for embedding an insulating film in the element isolation trench with the above-mentioned miniaturization, a device for element isolation is obtained by applying a perhydrogenated silazane polymer solution (polysilazane solution) to the surface of a semiconductor substrate and then performing an oxidation treatment in a water vapor atmosphere. A method of forming a silicon oxide film that is an insulating film for use is known (see, for example, Patent Document 1). However, in the case of this method, when a silicon oxide film is formed by performing an oxidation process in a water vapor atmosphere, impurities such as carbon may remain in the silicon oxide film, which may act as a positive fixed charge. There was a problem of deteriorating the electrical characteristics and reliability.

  As another method for embedding an insulating film in the element isolation trench, a silicon oxide film (hereinafter referred to as a high-density oxide film (or HDP oxide film)) is formed in the element isolation trench by using an HDP (high density plasma) -CVD method. There is known a method of embedding. In this method, when the aspect ratio of the trench where the STI structure is formed increases with the miniaturization of the pattern, before the trench is completely filled when the high-density oxide film is buried in the element isolation trench. The opening is closed before the trench is filled with the high-density oxide film deposited excessively in the opening between the gate electrodes. As a result, there is a problem that voids are formed in the high-density oxide film having the STI structure, that is, in the element isolation insulating film.

  As a method for solving such a problem of embedding failure, a method is conceived in which a high-density oxide film is deposited as a thin film in the element isolation trench and then a low-density oxide film with good embedding property is embedded. In this case, as the low density oxide film, for example, a silicon oxide film formed by applying a polysilazane solution and performing an oxidation process in a water vapor atmosphere is used.

However, in the above-described method of embedding the high-density oxide film and the low-density oxide film in the element isolation trench, the low-density oxide film exists close to the floating gate electrode. The agent diffuses in the low density oxide film and oxidizes the lower part of the polysilicon film constituting the floating gate electrode. As a result, there is a problem that the thickness of the edge portion of the silicon oxide film that becomes the tunnel oxide film is increased, that is, the so-called bird's beak amount is increased.
JP 2004-179614 A

  The present invention can reduce the amount of bird's beaks in a tunnel insulating film by preventing the oxidizing agent from oxidizing the lower part of the polysilicon film constituting the floating gate electrode as much as possible in an oxidation step after gate processing. An object is to provide a method for manufacturing a device.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a memory cell portion and a peripheral circuit portion are provided on a semiconductor substrate, wherein the gate insulating film, the polysilicon film, and the silicon nitride are formed on the semiconductor substrate. A step of laminating a film; and etching the semiconductor substrate, the gate insulating film, the polysilicon film, and the silicon nitride film by dry etching, and forming an element isolation groove in the memory cell portion with the peripheral circuit Forming an element isolation groove having a width wider than that of the element isolation groove of the memory cell portion in the portion, and HDP-CVD to have a predetermined density in the element isolation grooves of the memory cell portion and the peripheral circuit portion. A step of depositing and embedding a first oxide film, wherein the high-density oxide film embedded in the element isolation trench of the memory cell portion has a height of the semiconductor surface; Depositing up to a position above the upper surface of the active region of the substrate, and depositing the first oxide film so as not to block the upper part of the isolation trench; and applying a perhydrogenated silazane polymer solution And filling the element isolation trench with a second oxide film having a lower density than the first oxide film, and flattening the first and second oxide films using the silicon nitride film as a stopper by CMP. And a step of removing the second oxide film embedded in the element isolation trench of the memory cell portion by wet etching after removing the silicon nitride film by wet etching. Has characteristics.

  According to the present invention, although the high-density oxide film and the low-density oxide film are embedded in the element isolation trench, the low-density oxide film can be prevented from approaching the floating gate electrode, and the amount of bird's beak is reduced. can do.

  Hereinafter, an embodiment in which the present invention is applied to a NOR flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

First, the configuration of the NOR type flash memory device of this embodiment will be described.
FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a floating gate type NOR flash memory device. FIG. 2 shows an example of a layout obtained by extracting a part of the cell array of the NOR flash memory device of FIG.

  In the cell array of the NOR type flash memory device shown in FIGS. 1 and 2, memory cell transistors Trm are arranged in a matrix (row direction: X direction, column direction) on a well region formed in a surface layer portion of a silicon substrate 1 as a semiconductor substrate. : Y direction). Each memory cell transistor Trm has an active region (a source / drain diffusion layer and a channel region) 2 formed in a well region, and has a two-layer gate structure (of a floating gate) via a gate insulating film on the well region. And a gate electrode GM having a structure in which a control gate is formed via an inter-gate insulating film.

  In the cell array of the NOR type flash memory device, two adjacent memory cell transistors Trm share a drain region D, and two adjacent memory cell transistors Trm share a source region S. In addition, the columns of the memory cell transistors Trm arranged in the Y direction are separated by an STI (shallow trench isolation) region 3 which is a trench type element isolation region.

  A plurality of word lines WL are arranged in the X direction (row direction) so as to be connected in common to the control electrodes of the memory cell transistors Trm in the same row on the cell array, and are common to the source regions S of the memory cells in the same row. A plurality of local source lines LS are arranged in the X direction (row direction) as common source lines made of metal wirings connected to.

  Further, a plurality of bit lines BL made of metal wiring are arranged in the Y direction (column direction) so as to be in common contact with the drain regions D of the memory cell transistors Trm in the same column on the cell array, and a plurality of local source lines LS. A plurality of source lines (main source lines) MS made of metal wirings in common contact with each other are intermittently arranged in the Y direction (column direction) in the bit line BL array.

  As described above, the drain D shared by two adjacent memory cell transistors Trm is connected to the low-resistance bit line BL via the drain contact DC. The source S shared by two adjacent memory cell transistors Trm is connected to a local source line LS that exists in parallel with the word line WL between the word lines WL, and the local source line LS is connected to the source line contact LS. Is connected to the low-resistance main source line MS, and a potential is applied from outside the cell array.

  In the NOR flash memory device having the above structure, when channel hot electron injection is used to inject electrons into the floating gate electrode in order to write data to the memory cell transistor, the ground potential is applied to the source S and well region of the memory cell transistor Trm. give. A desired potential that maximizes the generation efficiency of hot electrons is applied to the control gate and the drain D from an external circuit via the word line WL and the bit line BL, respectively.

  FIG. 3 shows a schematic cross-sectional structure in the middle stage of the manufacturing process of the NOR type flash memory device, and shows a portion indicated by a cutting line AA in FIG. 2, that is, a portion cut along the word line WL. A cross section is shown.

  In FIG. 3, a trench (groove) 4 for forming STI 3 is formed in a portion sandwiched between active regions 2 in the silicon substrate 1. The trench 4 is set such that the depth dimension d1 from the upper surface of the silicon substrate 1 is secured to a dimension (for example, 150 nm or more) sufficient to ensure a dielectric strength between adjacent gate electrodes GM.

  On the upper surface of the active region 2, a silicon oxide film (tunnel oxide film) 5 as a gate insulating film, a polysilicon film 6 as a floating gate electrode, an interpoly insulating film 7 made of an ONO film, etc., a control gate electrode (word line WL) The polysilicon film 8 is stacked and constitutes the gate electrode GM. A high-density first oxide film 9 made of an HDP oxide film is embedded in the trench 4 and between the gate electrode GM (floating gate electrode). In this case, the height of the upper surface of the first oxide film 9 is lower than the height of the upper surface of the polysilicon film 6 and higher than the upper surface of the active region 2 by a height dimension h (for example, about 50 to 60 nm). Embedded.

After that, a NOR flash memory device is formed from the state of the above configuration through a general manufacturing process such as contact hole and electrode formation.
Since it is configured as described above, even if the aspect ratio between the gate electrodes GM is increased, only the first oxide film 9 is embedded inside the trench 4 and between the gate electrodes GM, and the oxidation after gate processing is performed. In the process or the like, it is possible to prevent the oxidizing agent from oxidizing the lower portion of the polysilicon film 6 constituting the floating gate electrode as much as possible, and the film thickness of the edge portion of the silicon oxide film 5 serving as a tunnel oxide film is increased. The so-called bird's beak amount can be reduced.

  Next, the manufacturing process of the said structure is demonstrated with reference to FIGS. 4A to 9A are cross-sectional views taken along the section line AA in FIG. 2 (that is, the CELL portion), and FIG. 4B is a sectional view of the peripheral circuit portion (that is, the PERI portion). It is sectional drawing.

  First, as shown in FIG. 4, after a silicon oxide film 5 as a gate insulating film is formed on a silicon substrate 1 by thermal oxidation, a polysilicon film 6 to be a floating gate electrode is deposited. Thereafter, a silicon nitride film 10 serving as a hard mask material is deposited. Subsequently, a resist 11 is formed on the silicon nitride film 10, and the resist 11 is patterned by an exposure method to form a mask.

  Next, as shown in FIG. 5, the trench 4 is formed by etching (processing) the silicon nitride film 10, the polysilicon film 6, the silicon oxide film 5, and the silicon substrate 1 using a dry etching technique. In this case, the trench 4 is processed such that the depth dimension d1 of the CELL part is shallow, for example, about 150 nm, and the depth dimension d2 of the PERI part is deep, for example, about 300 nm. In addition, as a method of making the depth of the trench 4 separately, there is a method in which the resist is covered with the area PEP and processed to have a desired depth separately. Thereafter, the resist 11 is removed by wet etching.

  Subsequently, as shown in FIG. 6, a silicon oxide film (HDP oxide film), that is, a high-density first oxide film 9 is deposited using HDP (high density plasma) -CVD. In this case, the first oxide film 9 in the CELL portion protrudes in the trench 4 so that the height of the upper surface of the first oxide film 9 is higher than the upper surface of the active region (AA region) 2 (specifically Specifically, the first oxide film 9 is excessively deposited on the silicon nitride film 10 up to a height dimension h (for example, about 50 to 60 nm) higher than the upper surface of the active region 2 and the trench. 4 is deposited so as not to close (see FIG. 6A). In the present embodiment, since the depth dimension d1 of the trench 4 in the CELL portion is as shallow as about 150 nm, it is possible to sufficiently deposit the first oxide film 9 as described above. The width dimension (the dimension in the left-right direction in FIG. 6A) a of the trench 4 is set to about 70 nm, for example.

  Thereafter, for example, after applying a perhydrogenated silazane polymer solution (polysilazane solution) to the surface of the silicon substrate 1, an oxidation treatment is performed in a water vapor atmosphere, so that a silicon oxide film having a lower density than the first oxide film 9 is obtained. A certain second oxide film 12 is formed.

  Next, as shown in FIG. 7, the first oxide film 9 and the second oxide film 12 are planarized by CMP using the silicon nitride film 10 as a stopper. After that, as shown in FIG. 8A, the first oxide film 9 and the second oxide film 12 in the trench 4 of the CELL part are made lower than the height of the upper surface of the polysilicon film 6 and the active region 2 by dry etching. It is dropped (etched back) to a position of a height dimension h from the upper surface of.

  Subsequently, as shown in FIG. 9, the silicon nitride film 10 on the polysilicon film 6 is removed by wet etching with hot phosphoric acid. Further, in the wet etching (variable etching) for absorbing the etching variation between lots generated by the dry etching after the silicon nitride film 10 is removed, the selection ratio between the first oxide film 9 and the second oxide film 12 is selected. Only the second oxide film 12 is removed by wet etching using a certain chemical solution (for example, HF-Vapor). In this case, etching is performed such that the second oxide film 12 in the CELL portion is completely removed while the second oxide film 12 in the trench (element isolation trench) 4 in the PERI portion remains. As a result, an oxide film, specifically, the first oxide film 9 and the second oxide film 12 are embedded in the trench (element isolation groove) 4 of the PERI portion (see FIG. 9B). A structure in which only the first oxide film 9 is embedded in the trench 4 of the CELL portion can be realized. Thereafter, as shown in FIG. 3, an interpoly insulating film 7 made of, for example, an ONO film is deposited, and a polysilicon film 8 is formed on the interpoly insulating film 7 to complete a laminated gate electrode.

  According to the present embodiment having such a configuration, only the first oxide film 9 is embedded in the trench 4 of the CELL portion, and the height of the upper surface of the first oxide film 9 is the upper surface of the active region 2. Unlike the conventional configuration, the polysilicon film 6 in which the oxidizing agent forms the floating gate electrode in the oxidation step after the gate processing is different from the conventional configuration because the height h is higher than the height dimension h (for example, about 50 to 60 nm). It is possible to prevent as much as possible from oxidizing the lower part of the substrate. As a result, the so-called bird's beak amount in which the film thickness of the edge portion of the silicon oxide film 5 serving as the tunnel oxide film is increased can be reduced. Specifically, as shown in FIG. 11, the bird's beak amount b can be about 10 nm (see FIG. 10).

  Incidentally, in the conventional configuration, that is, both the first oxide film and the second oxide film are embedded in the trench of the CELL portion, and the height of the upper surface of the first oxide film is the upper surface of the active region 2 of the silicon substrate 1. In the case of a lower configuration, the bird's beak amount b is about 20 nm (see FIG. 10), which is a considerably large value. This is because the second oxide film is present in the vicinity of the floating gate electrode, so that in the oxidation process after gate processing, the oxidant diffuses in the second oxide film and forms the floating gate electrode. This is because the lower part of the film is oxidized.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.

  As a method of creating the depth of the trench 4 separately between the CELL part and the PERI part, instead of using a resist cover at the area PEP and separately processing to have a desired depth, the micro loading effect is used and the PERI is used. Alternatively, a method of making the depth (STI depth) of the trench 4 in the CELL part shallower than the part may be used.

  Moreover, in the said embodiment, although the depth of the trench 4 was comprised so that it might differ in a CELL part and a PERI part, you may comprise the same depth in the CELL part and a PERI part. That is, only the first oxide film 9 is embedded inside the trench 4 in the CELL portion and between the polysilicon film 6 (gate electrode GM) (specifically, the upper surface of the first oxide film 9 in the trench 4 is (Deposition up to a position where the height is higher than the active region 2 of the silicon substrate 1 and protrudes and the first oxide film 9 does not close above the trench 4) The depth of the trench 4 may be the same in the CELL part and the PERI part.

  Further, the present invention may be applied not only to a NOR flash memory device but also to a NAND flash memory device.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NOR type flash memory device showing an embodiment of the present invention; Schematic plan view showing a partial layout pattern of the memory cell region 2 shows a schematic cross-sectional structure in the middle of the manufacturing process of the NOR type flash memory device, and is a cross-sectional view of a portion indicated by a cutting line AA in FIG. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic sectional view at one stage of the manufacturing process (5) Schematic cross-sectional view at one stage of the manufacturing process (No. 6) The figure which shows the relationship between the bird's beak amount of the edge part of a tunnel oxide film, this embodiment, and a conventional structure Schematic cross-sectional view explaining the amount of bird's beak in tunnel oxide film

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is an active region, 3 is STI, 4 is a trench (element isolation trench), 5 is a silicon oxide film (gate oxide film), 6 is a polysilicon film, and 9 is The first oxide film, 10 is a silicon nitride film, and 12 is a second oxide film.

Claims (3)

In a method for manufacturing a semiconductor device configured to provide a memory cell portion and a peripheral circuit portion on a semiconductor substrate,
Stacking a gate insulating film, a polysilicon film and a silicon nitride film on a semiconductor substrate;
The semiconductor substrate, the gate insulating film, the polysilicon film, and the silicon nitride film are etched by dry etching, an element isolation groove having a predetermined width is formed in the memory cell portion, and an element of the memory cell portion is formed in the peripheral circuit portion. Forming an element isolation groove having a width wider than the width of the isolation groove;
A step of depositing and embedding a first oxide film having a predetermined density in the element isolation trenches of the memory cell portion and the peripheral circuit portion by HDP-CVD, which is embedded in the element isolation trenches of the memory cell portion; The high-density oxide film is deposited so that the height of the upper surface thereof is higher than the upper surface of the active region of the semiconductor substrate, and the first oxide film is deposited so as not to block the upper portion of the element isolation trench. A process to be performed;
Applying a perhydrogenated silazane polymer solution and embedding a second oxide film having a lower density than the first oxide film in the element isolation trench;
Planarizing the first and second oxide films using the silicon nitride film as a stopper by CMP;
And a step of removing the second oxide film embedded in the element isolation trench of the memory cell portion by wet etching after removing the silicon nitride film by wet etching. Manufacturing method.   In the step of forming the element isolation groove, the depth dimension of the element isolation groove of the memory cell portion is configured to be smaller than the depth dimension of the element isolation groove of the peripheral circuit portion. A method for manufacturing a semiconductor device according to claim 1.   In the step of removing the second oxide film, all of the second oxide film of the memory cell portion is removed and part of the second oxide film of the peripheral circuit portion is removed. The method of manufacturing a semiconductor device according to claim 1 or 2.

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