KR19990018367A - Nonvolatile Memory Device and Manufacturing Method Thereof - Google Patents

Abstract

Disclosed are a nonvolatile memory device having a self-aligned shallow trench isolation (SA-STI) structure and a method of manufacturing the same. The nonvolatile memory device may include a trench isolation region formed to a predetermined depth in a semiconductor substrate to define an active region; A first conductive layer formed over the active region via a tunnel oxide layer and formed as the same photo-mask as the trench isolation region; and in a memory cell region, the first conductive layer is formed in a spacer form on a sidewall of the first conductive layer and is selected. A floating gate including a second conductive layer formed to connect an upper side of the first conductive layer and a sidewall of the first conductive layer; And a control gate formed on the floating gate through an interlayer insulating layer. The floating gate and the trench isolation region are formed to be self-aligned with the same mask, and the floating gates of the select transistor regions are all electrically connected to the control gate. In addition, the control gate can be easily etched without reducing the coupling ratio.

Description

Nonvolatile Memory Device and Manufacturing Method Thereof

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a self-aligned shallow trench isolation structure and a method of manufacturing the same.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. If you do this, you can maintain the status, but it can be divided into ROM (read only memory) products with slow data input and output. Among these ROM products, there is an increasing demand for electrically erasable and programmable ROM (EEPROM) or flash memory that can electrically input and output data. Flash memory devices are an advanced form of EEPROM that can be electrically erased at high speed without removing them from the circuit board.The memory cell structure is simple, so the manufacturing cost per unit memory is low and the data is refreshed to preserve data. The advantage is that functions are unnecessary, but the input / output speed of data is hundreds of kilowatts to several kilowatts, which is significantly slower than tens of RAM products.

Looking at the flash memory device from a circuit point of view, each memory cell can be controlled independently, so that the operation speed is high, but one contact is required per two cells, so that the cell area becomes large and several memory cells are combined into one bundle. It can be controlled and classified into NAND type, which is advantageous for high integration.

In particular, highly integrated flash memory devices are expected to replace magnetic disk memory devices, which have several advantages such as small cell area, fast access time, and low power consumption. Because. However, in order to replace the magnetic disk memory, the flash memory needs to further reduce the cost per bit, and to this end, it is required to reduce the number of processes and further reduce the cell size. In order to satisfy these requirements, a NAND type flash memory cell with a self-aligned shallow trench isolation (hereinafter referred to as SA-STI) structure has been proposed (IEDM'94, S.Aritome et al., A 0.64μm ^2). SELF-ALIGNED SHALLOW TRENCH ISOLATION (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs), pp. 61-64).

First, a description will be made by comparing a NAND type flash memory cell having the SA-STI structure with a general NAND type flash memory cell.

FIG. 1 is a layout diagram of a conventional NAND flash memory cell, and FIG. 2 is a layout diagram of a NAND flash memory cell having the SA-STI structure. In Fig. 1, reference numeral 12 denotes a floating gate. In Fig. 2, reference numeral 54 denotes a floating gate and 66 denotes a gate of a selection transistor.

In the NAND type flash memory cell having the SA-STI structure shown in FIG. 2, the floating gate 54 used for storing charges does not overlap the active pattern unlike in FIG. 1. That is, the active pattern for forming the active region and the field region and the pattern of the floating gate 54 are the same. In addition, the floating gate 54 pattern and the active region may be simultaneously formed by only one photo process. Therefore, the size of the memory cell can be reduced by reducing the separation distance between the bit lines.

3A to 6B are cross-sectional views illustrating a method of manufacturing a flash memory cell having a SA-STI structure shown in FIG. 2. Here, each a is a cross-sectional view in which the memory cell is cut in the word line direction, that is, in the Y1-Y1 'or Y2-Y2' direction, and each b is a cross-sectional view in which the memory cell transistor is cut in the bit line direction, that is, in the X-X 'direction.

Referring to FIGS. 3A and 3B, after forming a P well in a predetermined region of the semiconductor substrate 50 through a photograph and an ion implantation process, the tunnel oxide layer 52 is grown to a thickness of about 85 kHz thereon. Subsequently, a first polysilicon layer 54 to be used as a floating gate is deposited on the tunnel oxide layer 52 to a thickness of about 2000 to 4000 microns, and the first oxide layer 56 is deposited thereon. The first oxide layer 56 is used as an etch mask when etching the semiconductor substrate 50 and the first polysilicon layer 54 for trench isolation.

Subsequently, after forming an active pattern as shown in FIG. 2 by a photolithography process, the first oxide layer 56 is etched using the active pattern. Subsequently, the first polysilicon layer 54, the tunnel oxide film 52, and the substrate 50 are continuously etched using the first oxide film 56 as an etching mask to form a trench 58. Subsequently, P-type impurities such as boron (B) are ion-implanted into the substrate 50 under the trench 58 to form a channel stop layer (not shown) to enhance device isolation characteristics. .

4A and 4B, the second oxide layer 60 is deposited on the entire surface of the resultant product in which the trench 58 is formed by chemical vapor deposition (CVD).

Referring to FIGS. 5A and 5B, the second oxide layer 60 is dry-etched until a portion of the sidewall of the floating gate 54 is exposed, so that the second oxide layer 60 is formed only in the trench 58. Landfill. Subsequently, ONO (oxide / nitride / oxide) 62 is deposited as an interlayer insulating film on the entire surface of the resultant product.

6A and 6B, a second polysilicon layer 64 to be used as a control gate is deposited on the ONO layer 62. Subsequently, the control gate 64, the ONO film 62, and the floating gate 54 are patterned by photolithography to form the gate 66 of the selection transistor and the gate 68 of the cell transistor. At this time, as shown in the layout diagram of FIG. 2, the gate vertical structures of the memory cell transistor regions Y1-Y1 ′ and the selection transistor regions Y2-Y2 ′ are simultaneously patterned to the floating gate 54 by an active pattern. As a result, they are formed in the same manner. In addition, in the gate 66 region of the selection transistor, the floating gate 54 is separated from each other in units of strings like the gate 68 region of the memory cell transistor.

According to the above-described conventional NAND-type flash memory cell having a SA-STI structure, by using the trench device isolation process, the separation distance between devices is smaller than that of the device isolation process by the local oxidation of silicon (LOCOS). The active pattern may be the same as that of the floating gate 54, thereby reducing the size of the memory cell and reducing the number of processes.

However, the NAND type flash memory cell having the above-described conventional SA-STI structure has the following problems.

As shown in FIG. 2, in the NAND type flash memory device, a plurality of memory cells are connected in series between one bit line contact 70 and a common source line 72 to form one string. A plurality of strings are connected in parallel to form a block, and blocks are symmetrically arranged around the bit line contact 70. Therefore, when a feature cell is to be selected, if a word line and a bit line are selected, a select line 66 is used to designate a specific block. Unlike the memory cell, the select line 66 electrically connects the floating gate and the control gate to operate as a MOS transistor. For this purpose, butting contacts are generally used. That is, the floating gate and the control gate of the selection line are connected to the metal using a butting contact.

However, in the SA-STI process described above, since the trench isolation pattern and the floating gate pattern are self-aligned using the same active mask, the floating gate of the select transistor (or select line) 66 is formed in the memory cell region. Similarly, each unit string is formed in a structure separated from each other. Therefore, since the gate of the selection transistor has the same structure as that of the memory cell transistor, and the floating gate is insulated from the control gate by the ONO film, it becomes difficult to operate as a normal MOS transistor.

In addition, according to the aforementioned NAND type flash memory cell having the SA-STI structure, the length of the floating gate 54 is limited to the length corresponding to the width of the active pattern as shown in FIG. Therefore, the area is smaller than the floating gate area in the general NAND type flash memory cell as shown in FIG. 1, so that the coupling ratio is relatively small. To solve this problem, a method of enlarging the area of the ONO film by increasing the thickness of the floating gate by increasing the thickness of the floating gate has been proposed. However, according to the above method, when the control gate, the ONO film, and the floating gate are continuously etched, the likelihood of generating a stringer of the control gate or the floating gate increases.

Accordingly, the present invention has been devised to solve the above-described problems of the conventional method, and an object of the present invention is to allow the floating gates of the select transistors to be electrically connected to the control gates, and control gate and memory without reducing the coupling ratio. The present invention provides a nonvolatile memory device that is easy to gate-pattern a cell transistor.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which is particularly suitable for manufacturing the nonvolatile memory device.

1 is a layout diagram of a general NAND flash memory cell.

2 is a layout diagram of a NAND type flash memory cell having a conventional SA-STI structure.

3A to 6B are cross-sectional views illustrating a method of manufacturing the flash memory cell shown in FIG. 2.

7 is a layout diagram of a NAND type flash memory cell having a SA-STI structure according to the present invention.

8A and 8B are cross-sectional views illustrating a selection transistor region and a memory cell region, respectively, in the flash memory cell shown in FIG. 7.

9A to 13B are cross-sectional views illustrating a method of manufacturing the flash memory cell shown in FIG. 7.

Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 102 tunnel oxide film

104: first conductive layer 106: second insulating film

108: trench 110: third insulating film

112: second conductive layer 114: selection line pattern

118: interlayer insulating film 120: third conductive layer

122: selection transistor 124: cell transistor

In order to achieve the above object, the present invention provides a plurality of stacked memory cells comprising a series of transistors connected in series, and at least one selection transistor is common to the bit line contact to select one predetermined cell among the memory cells. A nonvolatile memory device in which a unit string is connected to one another in series between source lines,

A trench isolation region formed to a predetermined depth in the semiconductor substrate to define an active region; A first conductive layer formed over the active region via a tunnel oxide layer, the first conductive layer formed as the same photo-mask as the trench isolation region, and in the memory cell region in the form of a spacer on sidewalls of the first conductive layer; A floating gate including a second conductive layer formed to connect a sidewall of an upper portion of the first conductive layer to the selection transistor region; And a control gate formed on the floating gate with an interlayer insulating layer interposed therebetween.

Preferably, the pattern of the second conductive layer in the selection transistor region is wider than the pattern of the trench isolation region.

Preferably, the first conductive layer is separated by the string unit.

In order to achieve the above object, the present invention provides a plurality of stacked memory cells composed of transistors connected in series, and at least one selection transistor is selected from a bit line contact to select a predetermined one of the memory cells. A method of manufacturing a nonvolatile memory device in which unit strings are connected in series between a common source line to form a unit string.

Sequentially forming a first insulating film, a first conductive layer to be used as a floating gate, and a second insulating film on the semiconductor substrate; Forming a trench by etching the semiconductor substrate to a predetermined depth by a photolithography process; Forming a trench isolation region by forming a third insulating film on the entire surface of the resultant and etching the same until the top and sidewalls of the first conductive layer are exposed; Forming a second conductive layer on the entire surface of the resultant product; Forming a photoresist film only on an upper portion of the selection transistor region by a photolithography process, and then etching the second conductive layer of the memory cell region using the photoresist to leave a second conductive layer in the form of a spacer on the sidewall of the first conductive layer; Sequentially forming a third conductive layer to be used as an interlayer insulating film and a control gate on the entire surface of the resultant product; And etching the third conductive layer, the interlayer insulating layer, the second conductive layer, and the first conductive layer to form gates of a selection transistor and a memory cell. .

Preferably, the second insulating film is formed of either a CVD oxide film or a CVD nitride film, and the third insulating film is formed of any one of a CVD oxide film or a laminated film of a thermal oxide film and a CVD-oxide film.

The forming of the trench may include forming a photoresist layer on the second insulating layer to define an active region, and etching the second insulating layer using the photoresist; Removing the photosensitive film; And forming a trench by etching the first conductive layer, the first insulating layer, and the semiconductor substrate using the second insulating layer as an etching mask.

The third insulating film is etched by a chemical mechanical polishing (CMP) process, wherein the second insulating film is etched together.

Preferably, the photoresist layer for etching the second conductive layer is formed to include a part or the whole of the selection transistor region.

In the present invention, the trench isolation region and the floating gate for defining the active region are formed in a self-alignment using the same mask. In addition, a floating gate is formed of a first conductive layer and a second conductive layer formed in a spacer form on sidewalls of the first conductive layer in a memory cell region by using a separate photo-mask, and in a string unit in a selection transistor region, respectively. The top and sidewalls of the first conductive layer formed separately are connected to each other by the second conductive layer. Therefore, in the selection transistor region, all the floating gates are electrically connected to the control gate.

In addition, since the floating gate is formed of the first conductive layer and the second conductive layer, the area of the interlayer insulating layer is enlarged without increasing the thickness of the floating gate, thereby making it easier to etch the control gate without reducing the coupling ratio.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

7 is a layout diagram of a NAND type flash memory cell having a SA-STI structure according to the present invention.

Referring to FIG. 7, in the NAND type flash memory device according to the present invention, in a plurality of memory cells, a plurality of memory cells share one active region and one bit line contact 130 and a common source line 132. Are connected in series, and select transistors for selecting a block during data read and write operations include a memory cell and a bit line contact 130, and a memory cell and a common source line 132. It is located in between to form a unit string. Such a unit string is repeatedly arranged with an active region and a trench isolation region to form a block. The blocks are symmetrically disposed about the bitline contacts 130.

In addition, the NAND type flash memory device according to the present invention has a self-aligned structure in which the trench isolation pattern and the floating gate pattern are formed using the same active mask, and in many memory cells, the floating gate of the select transistor is separated for each unit string. In order to be electrically connected to the word line, the gate pattern 114 of the selection transistor is formed to overlap the SA-STI pattern using a separate photo-mask. Preferably, the gate pattern 114 of the selection transistor is formed somewhat wider than the SA-STI pattern.

FIG. 8A is a cross-sectional view of the selection transistor taken along the Y2-Y2 'direction in FIG. 7, and FIG. 8B is a cross-sectional view taken along the X-X ′ direction of the memory cell of FIG. Here, reference numeral 100 is a semiconductor substrate, 102 is a tunnel oxide film, 104 is a first conductive layer, 110 is a third insulating film, 112 is a second conductive layer, 118 is an interlayer insulating film, 120 is a control gate, and 122 is a gate of a selection transistor. And 124 denote gates of the cell transistors, respectively.

8A and 8B, in the flash memory cell having the SA-STI structure according to the present invention, a floating gate is formed by the first conductive layer 104 and the second conductive layer 112 in the memory cell region. do. In contrast, in the selection transistor (or selection line) region, the top and sidewalls of the first conductive layer 104 formed separately from each other by strings are connected to each other by the second conductive layer 112. Accordingly, in the selection line 122, the floating gates 104 and 112 and the control gate 120, to which the first and second conductive layers are connected, are separated from each other by the interlayer insulating layer 118. Electrically connected to each other through a butting contact to operate as a MOS transistor.

In addition, in the NAND type flash memory cell having the SA-STI structure according to the present invention, since the floating gate is formed of the first conductive layer and the second conductive layer, the area of the interlayer insulating film is enlarged without increasing the thickness of the floating gate. Etching of the control gate is facilitated without reducing the coupling ratio.

9A to 13B are cross-sectional views illustrating a method of manufacturing a NAND type flash memory cell having a SA-STI structure according to the present invention shown in FIG. Here, each b is a cross-sectional view in which the memory cell is cut in the bit line direction, that is, the XX 'direction, and each a is a cut in the memory cell transistor in the word line direction, that is, in the Y1-Y1' direction, or the selection transistor is Y2-Y2 '. It is sectional drawing cut in the direction.

9A and 9B illustrate forming trench 108. N wells and P wells are formed in predetermined regions of the semiconductor substrate 100 through a photo and ion implantation process. Typically, a well in which a PMOS transistor of a peripheral circuit portion is to be formed is called an N well, and a P well in which a memory cell in the N well is to be formed is called a pocket p-well.

Subsequently, the first insulating film 102 to be provided as a tunnel oxide film is grown on the entire surface of the substrate 100 to a thickness of about 90 kV, and then the first conductive layer 104 to be used as a floating gate on the tunnel oxide film 102. For example, a polysilicon layer doped with impurities is deposited to a thickness of about 3000 to 4000 microns. Next, for example, a CVD oxide film or a CVD nitride film is deposited on the first conductive layer 104 with the second insulating film 106. The second insulating layer 106 is used as an etch mask when etching the semiconductor substrate 100 and the first conductive layer 104 for trench isolation in a subsequent process.

Subsequently, after forming an active pattern as shown in FIG. 7 by a photolithography process, the second insulating layer 106 is etched using the active pattern. Subsequently, the trench 108 is formed by continuously etching the first conductive layer 104, the tunnel oxide film 102, and the semiconductor substrate 100 using the second insulating film 106 as an etching mask. Subsequently, P-type impurities such as boron (B) are ion-implanted in the substrate 100 under the trench 108 to form a channel stop layer (not shown) to enhance device isolation characteristics.

10A and 10B illustrate a step of depositing, for example, a CVD oxide film or a stacked layer of a thermal oxide film and a CVD oxide film with a third insulating film 110 on the entire surface of the trench 108. The third insulating layer 110 is deposited to fill both sidewalls of the trench 108 and the first conductive layer 104.

11A and 11B illustrate forming the second conductive layer 112. The third insulating layer 110 is etched until the upper portion of the first conductive layer 104 and a portion of the sidewalls are exposed, thereby filling the third insulating layer 110 only in the trench 108. In this case, the second insulating layer 106, which used as a mask during the etching process for forming the trench 108, is etched together with the third insulating layer 110, thereby exposing a portion of the upper portion and the sidewall of the first conductive layer 104. do. The etching process of the third insulating layer 110 may be performed by a chemical mechanical polishing (CMP) method, in which the first conductive layer 104 acts as an etch stopper, thereby providing a first etching process. The second and third insulating layers 106 and 110 on the conductive layer 104 may be removed. In addition, after performing the CMP process, anisotropic or isotropic etching may be performed to expose sidewalls of the first conductive layer 104.

Subsequently, a polysilicon layer doped with impurities, for example, is deposited on the entire surface of the resultant material as the second conductive layer 112.

12A and 12B illustrate etching the second conductive layer 112. After forming the second conductive layer 112 as described above, after performing a photolithography process using the same photo-mask as the selection line pattern 114 shown in FIG. 7, the second conductive layer 112 is anisotropically dry-etched. . As a result, the first conductive layer 104 and the second conductive layer 112 remaining in the form of a spacer on the sidewalls of the first conductive layer 104 are used as the final floating gate. In this case, as shown in FIG. 12B, in the selection transistor region 114, the second conductive layer 112 is not etched and remains as it is. Therefore, the floating gate constituting the gate of the selection transistor is formed in a structure in which the upper side and the sidewall of the first conductive layer 104 are connected to each other by the second conductive layer 112. In FIG. 7, the regions indicated by the select line patterns 114 are intended to be connected to the first conductive layer 104 by the second conductive layer 112, and thus overlap with each other without having to form the same as the SA-STI pattern. All you need is Preferably, it is convenient to form the select line pattern 114 slightly wider than the SA-STI pattern. In Fig. 12B, reference numeral 116 denotes a cell transistor region.

13A and 13B illustrate forming an interlayer insulating film 118 and a third conductive layer 120. After etching the second conductive layer 112 as described above, the ONO film is deposited on the entire surface of the resultant with the interlayer insulating film 118. Subsequently, an impurity doped polysilicon layer or a dopant-doped polysilicon layer and a tungsten silicide (WSix) layer are deposited as a third conductive layer 120 to be used as a control gate on the interlayer insulating layer 118. do. Subsequently, after performing a photolithography process using the same photo-mask as the SA-STI pattern illustrated in FIG. 7, the control gate 120, the ONO film 118, and the floating gates 104 and 112 are successively anisotropically dried. Etch it. As a result, the floating gate is formed by the first conductive layer 104 and the second conductive layer 112 in the memory cell region, whereas the first conductive layer is formed separately in string units in the selection transistor (or selection line) region. Layers 104 are connected to each other by second conductive layer 112 to form a floating gate.

After the above processes, a source / drain ion implantation process for forming a MOS transistor, a planarization process, a contact and a metal process for forming a bit line, and the like are completed to complete a NAND type flash memory device.

As described above, in the nonvolatile memory device according to the present invention, the trench isolation region and the floating gate for defining the active region are self-aligned using the same mask. In addition, a floating gate is formed of a first conductive layer and a second conductive layer formed in a spacer form on sidewalls of the first conductive layer in a memory cell region by using a separate photo-mask, and in a string unit in a selection transistor region, respectively. The top and sidewalls of the first conductive layer formed separately are connected to each other by the second conductive layer. Therefore, in the selection transistor region, all the floating gates are electrically connected to the control gate.

In addition, since the floating gate is formed of the first conductive layer and the second conductive layer, the area of the interlayer insulating layer is enlarged without increasing the thickness of the floating gate, thereby making it easier to etch the control gate without reducing the coupling ratio.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (10)

A plurality of stacked memory cells composed of series-connected transistors and at least one selection transistor connected to each other in series between a bit line contact and a common source line to select a predetermined one of the memory cells A nonvolatile memory device constituting a string, comprising: a trench isolation region formed to a predetermined depth in a semiconductor substrate to define an active region; A first conductive layer formed over the active region via a tunnel oxide layer, the first conductive layer formed as the same photo-mask as the trench isolation region, and in the memory cell region in the form of a spacer on sidewalls of the first conductive layer; A floating gate including a second conductive layer formed to connect a sidewall of an upper portion of the first conductive layer to the selection transistor region; And a control gate formed on the floating gate through an interlayer insulating layer. The nonvolatile memory device of claim 1, wherein the pattern of the second conductive layer in the selection transistor region overlaps the pattern of the trench isolation region by a predetermined width. The nonvolatile memory device of claim 1, wherein the first conductive layer is separated by the string. A plurality of stacked memory cells composed of series-connected transistors and at least one selection transistor connected to each other in series between a bit line contact and a common source line to select a predetermined one of the memory cells A method of manufacturing a nonvolatile memory device constituting a string, the method comprising: sequentially forming a first insulating film, a first conductive layer to be used as a floating gate, and a second insulating film on an upper surface of a semiconductor substrate; Forming a trench by etching the semiconductor substrate to a predetermined depth by a photolithography process; Forming a trench isolation region by forming a third insulating film on the entire surface of the resultant and etching the same until the top and sidewalls of the first conductive layer are exposed; Forming a second conductive layer on the entire surface of the resultant product; Forming a photoresist film only on an upper portion of the selection transistor region by a photolithography process, and then etching the second conductive layer of the memory cell region using the photoresist to leave a second conductive layer in the form of a spacer on the sidewall of the first conductive layer; Sequentially forming a third conductive layer to be used as an interlayer insulating film and a control gate on the entire surface of the resultant product; And etching the third conductive layer, the interlayer insulating film, the second conductive layer, and the first conductive layer to form gates of a selection transistor and a memory cell. The method of claim 4, wherein the second insulating layer is formed of any one of a CVD oxide film and a CVD nitride film. The method of claim 4, wherein the forming of the trench comprises: forming a photoresist layer defining an active region on the second insulating layer, and etching the second insulating layer using the photoresist; Removing the photosensitive film; And forming a trench by etching the first conductive layer, the first insulating layer, and the semiconductor substrate using the second insulating layer as an etching mask. The method of manufacturing a nonvolatile memory device according to claim 4, wherein the third insulating film is formed of any one of a CVD oxide film or a laminated film of a thermal oxide film and a CVD-oxide film. The method of claim 4, wherein the second insulating film is etched together in the etching of the third insulating film. The method of claim 4, wherein the third insulating layer is etched by chemical mechanical polishing (CMP). The method of claim 4, wherein the photosensitive film for etching the second conductive layer is formed to include a part or the whole of the selection transistor region.