JP2008270260A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent electrical short circuit between the gate electrode of a circuit element having a one-layer gate structure and a substrate in a semiconductor memory having a two-layer gate structure and a one-layer gate structure. <P>SOLUTION: The underlying gate electrode layers 23b and 23c of a selection gate transistor and an MOS transistor having a one-layer gate structure are made thicker than the floating gate electrode layer 23a of a memory cell transistor so that the upper surface of the gate insulating layers 22b and 22c is prevented from being exposed by penetrating the underlying gate electrode layers 23b and 23c when openings 28b and 28c are formed in second interelectrode insulating films 24b and 24c by etching. Since the gate insulating layers 22b and 22c are not removed simultaneously when a native oxide layer formed on the exposed surface of the underlying gate electrode layers 23b and 23c is removed, electrical short-circuit can be prevented between the gate electrodes SG and TG of a selection gate transistor and an MOS transistor and a semiconductor substrate 21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, to a NAND type nonvolatile memory in which a select gate transistor having a one-layer gate structure and a memory cell transistor having a two-layer gate structure are mounted on the same semiconductor substrate. It relates to the gate structure.

  The NAND type nonvolatile memory has a structure in which a plurality of memory cell transistors formed on an element region of a semiconductor substrate are connected in series, and select gate transistors are arranged on both sides thereof. In the manufacture of the NAND type nonvolatile memory, the memory cell transistor and the select gate transistor are simultaneously processed in order to simplify the manufacturing process.

  That is, the first gate electrode layer is formed on the semiconductor substrate in the memory cell transistor region and the select gate transistor region via the gate insulating film. After forming the interelectrode insulating layer on the first gate electrode layer, an opening for exposing a part of the surface of the first gate electrode layer is formed in the interelectrode insulating layer in the select gate transistor region by etching. Next, a second gate electrode layer is formed on the exposed surface of the first gate electrode layer and the interelectrode insulating layer, and then gate electrode processing is performed. In the memory cell transistor region, a floating gate electrode layer (first gate electrode layer) is formed. And a control gate electrode layer (second gate electrode layer) and a memory cell gate electrode having a two-layer gate structure, and in the selection gate transistor region, a lower gate electrode layer (first gate electrode layer) through an opening. A selection gate electrode having a one-layer gate structure in which the upper gate electrode layer (second gate electrode layer) is electrically connected is formed (see, for example, Patent Document 1).

  In this manufacturing method, in the select gate transistor region, the upper part of the lower gate electrode layer is also etched by etching when the opening is formed in the interelectrode insulating layer. In addition, the natural oxide film formed on the exposed surface of the lower gate electrode layer after the opening is formed may cause a conduction failure between the upper gate electrode layer and the lower gate electrode layer. The surface of the semiconductor substrate is exposed through the upper gate electrode layer and the gate insulating layer by this etching, and the upper gate electrode layer may come into contact with the semiconductor substrate. Must be formed thick.

  On the other hand, in the NAND type nonvolatile memory, inter-cell interference has become a problem due to miniaturization. In order to reduce the inter-cell interference, it is necessary to reduce the thickness of the floating gate electrode layer of the memory cell transistor. It is known that it is effective (for example, refer nonpatent literature 1).

However, since the floating gate electrode layer of the memory cell transistor and the lower gate electrode layer of the selection gate transistor are integrally formed, if the thickness of the floating gate electrode layer is reduced, the thickness of the lower gate electrode layer is also reduced. Conversely, if the lower gate electrode layer is made thicker, the floating gate electrode layer becomes thicker, so that the electrical short circuit between the gate electrode of the select gate transistor and the semiconductor substrate and the inter-cell interference of the memory cell transistor can be improved at the same time. It is difficult.
JP 2002-176114 A IEEE Non-Volatile Semiconductor Memory Workshop 2006, pages 9-11

  In view of the above, the present invention provides a semiconductor memory device and a method for manufacturing the same, which can simultaneously improve the electrical short circuit between the gate electrode of the select gate transistor and the semiconductor substrate and the inter-cell interference of the memory cell transistor.

  In a method for manufacturing a semiconductor memory device according to one embodiment of the present invention, a top surface of a semiconductor substrate is processed to form a first top surface region and a second top surface region in which the top surface is located on a plane below the first top surface region. Forming a gate insulating layer on the first upper surface region and the second upper surface region so that the thicknesses of the insulating layers in the first and second upper surface regions are the same, and the gate insulation A first gate electrode layer is formed on the layer so that the electrode layers in the first and second upper surface regions have the same thickness, and the upper surface of the first gate electrode layer in the first upper surface region is A step of being positioned on a plane above the upper surface of the first gate electrode layer in the upper surface region, and an upper surface of the first gate electrode layer in the first upper surface region and the first gate electrode in the second upper surface region. Flush with the top of the layer An opening for exposing a part of the surface of the first gate electrode layer to the inter-electrode insulating layer in the second upper surface region; and a step of forming an inter-electrode insulating layer on the first gate electrode layer. A step of removing a natural oxide film formed on the exposed surface of the first gate electrode layer; and a second gate on the exposed surface of the first gate electrode layer and the inter-electrode insulating layer. Forming an electrode layer and selectively removing the second gate electrode layer, the inter-electrode insulating layer, the first gate electrode layer, and the gate insulating layer on the first and second upper surface regions; And a step of forming a gate electrode.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising: forming a gate insulating layer on the first upper surface region of the semiconductor substrate to have a thickness greater than that of the second upper surface region; The first gate electrode layer is formed so that the film thickness of the electrode layer in the first and second upper surface regions is the same, and the upper surface of the first gate electrode layer in the first upper surface region is the same as that in the second upper surface region. A step of positioning on a plane above the upper surface of the first gate electrode layer; and an upper surface of the first gate electrode layer in the first upper surface region and an upper surface of the first gate electrode layer in the second upper surface region. A step of positioning on the same plane; a step of forming an interelectrode insulating layer on the first gate electrode layer; and a part of the surface of the first gate electrode layer on the interelectrode insulating layer in the second upper surface region. Form an exposed opening A step of removing a natural oxide film formed on the exposed surface of the first gate electrode layer; and a second gate electrode layer on the exposed surface of the first gate electrode layer and the inter-electrode insulating layer. Forming a gate electrode by selectively removing the second gate electrode layer, the interelectrode insulating layer, the first gate electrode layer, and the gate insulating layer on the first and second upper surface regions; And a step of forming.

  According to still another aspect of the present invention, there is provided a semiconductor memory device including a semiconductor substrate including a first upper surface region and a second upper surface region having an upper surface located on a plane below the first upper surface region, and the first and first semiconductor devices. 2 between the gate insulating layer provided on the upper surface region, the floating gate electrode layer provided on the first upper surface region via the gate insulating layer, and the first electrode provided on the floating gate electrode layer An insulating layer; a control gate electrode layer provided on the first inter-electrode insulating layer; and an upper surface provided in the second upper surface region via the gate insulating layer and having the same upper surface as the upper surface of the floating gate electrode layer A lower gate electrode layer located on a plane; a second inter-electrode insulating layer provided on the lower gate electrode layer and having an opening for exposing a part of the lower gate electrode layer; and the lower gate The exposed surface of the electrode layer and the second electrode; Comprising an upper layer gate electrode layer provided between the insulating layer, the thickness of the floating gate electrode layer, it is characterized in thinner than the thickness of the lower gate electrode layer.

  A semiconductor memory device according to yet another aspect of the present invention is provided on a semiconductor substrate having a first upper surface region and a second upper surface region on the same plane, on the first upper surface region, and on the second upper surface region. A first gate insulating layer thicker than the second gate insulating layer, a floating gate electrode layer provided on the first upper surface region via the first gate insulating layer, and the floating gate electrode layer A first inter-electrode insulating layer provided on the first inter-electrode insulating layer, a control gate electrode layer provided on the first inter-electrode insulating layer, and an upper surface provided in the second upper surface region via the second gate insulating layer. Has a lower gate electrode layer positioned on the same plane as the upper surface of the floating gate electrode layer, an opening provided on the lower gate electrode layer and exposing a part of the upper surface of the lower gate electrode layer Second inter-electrode insulating layer and the lower gate electrode An upper gate electrode layer provided on the exposed surface of the layer and the second inter-electrode insulating layer, and the thickness of the floating gate electrode layer is smaller than the thickness of the lower gate electrode layer It is a feature.

  According to the present invention, it is possible to simultaneously improve the electrical short circuit between the gate electrode of the select gate transistor and the semiconductor substrate and the inter-cell interference of the memory cell transistor.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[First Embodiment]
FIG. 1 is a plan view schematically showing a NAND nonvolatile memory which is a semiconductor memory device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA of FIG. In the NAND type nonvolatile memory of this embodiment, a first upper surface region and a second upper surface region whose upper surface is located on a plane below the first upper surface region are provided on a semiconductor substrate, and the memory is provided on the first upper surface region. By providing the floating gate electrode layer of the cell transistor and providing the lower gate electrode layer of the selection gate transistor on the second upper surface region, the upper surfaces of the floating gate electrode layer and the lower gate electrode layer are flush with each other, and the floating gate The electrode layer is thin and the lower gate electrode layer is thicker than the floating gate electrode layer.

  As shown in FIG. 1, in the memory cell region 11, a plurality of active areas 13 that are element formation regions are formed in parallel in a strip shape via an element isolation insulating film 14 in the Y direction in the figure, A plurality of word lines WL1, WL2,..., WL8 are formed in parallel in a strip shape in the X direction in the drawing orthogonal to the figure. Memory cell transistors MT are formed at the intersections of the active area 13 and the word lines WL1, WL2,. A selection gate line SGL is formed outside the word line WL1 and outside the word line WL8, and a selection gate transistor ST for designating a memory cell block to be accessed is provided at each intersection of the active area 13 and the selection gate line SGL. Has been placed. Here, the “memory cell block” is a region including the memory cell transistor MT sandwiched between arbitrary selection gate lines SGL. The selection gate line SGL is provided with an inter-electrode insulating layer having a width narrower than that of the selection gate line SGL and having an opening 28b described later over the entire length of the selection gate line SGL. Here, in the memory cell region 11, a region where the memory cell transistor MT is disposed is referred to as a memory cell transistor region 11a, and a region where the selection gate transistor ST is disposed is referred to as a selection gate transistor region 11b. In addition, a contact electrode 17 for connecting data of the memory cell transistor MT to a bit line (not shown) is disposed on the active area 13 in a region sandwiched between the selection gate lines SGL in the selection gate transistor region 11b. . In the present embodiment, the number of word lines for each memory block is eight. However, the number of lines may be 16 or 32. Similarly, the number of active areas 13 is six, but a larger number of structures may be used.

  Further, outside the memory cell region 11, there is one active area 13 surrounded by the element isolation insulating film 14, and the active area 13 provided on the active area 13 extends in the X direction so as to cross the active area 13. One gate electrode TG extending to the element isolation insulating film 14 is formed. A plurality of upper-layer metal wirings (not shown) are electrically connected to the upper and lower active areas 13 in the Y direction in the figure so as to sandwich the gate electrode TG, and are arranged in parallel with the extending direction of the gate electrode TG. The contact electrode 17 is formed. A gate contact electrode 18 connected to an upper wiring (not shown) is formed on the element isolation insulating film 14 in the gate electrode TG. An interelectrode insulating layer having an opening 28c described later is provided on the active area 13 in the gate electrode TG. At the intersection of the active area 13 and the gate electrode TG, a MOS transistor TR which is a peripheral circuit transistor for driving the memory cell transistor MT and the selection gate transistor ST is formed. A region where the MOS transistor TR is formed is referred to as a peripheral circuit region 12. Although only one gate electrode TG is arranged, a plurality of gate electrodes TG may be provided, and the number of contact electrodes 17 and the number of gate contact electrodes 18 may be different from those in the present embodiment. Further, a plurality of interelectrode insulating layers may be formed in the gate electrode TG.

  As shown in FIG. 2, the semiconductor substrate 21 has a first upper surface region and a second upper surface region whose upper surfaces are located on different planes. Here, the first upper surface region having the upper surface at the upper position is the memory cell transistor region 11a, and the second upper surface region having the upper surface at the lower position is the selection gate transistor region 11b and the peripheral circuit region 12. On the top surfaces of the memory cell transistor region 11a, the select gate transistor region 11b, and the peripheral circuit region 12 of the semiconductor substrate 21, gate insulating layers 22a, 22b, and 22c having the same film thickness are formed.

  The gate electrodes MG1, MG2, and MG3 of the memory cell transistors MT1, MT2, and MT3 are formed on the gate insulating layer 22a with a predetermined interval. Each of the gate electrodes MG1, MG2, and MG3 includes a floating gate electrode layer 23a provided via the gate insulating layer 22a, a first inter-electrode insulating layer 24a formed on the floating gate electrode layer 23a, and the first A control gate electrode layer 27a composed of a control gate electrode layer lower portion 25a formed on the inter-electrode insulating layer 24a and a control gate electrode layer upper portion 26a formed on the control gate electrode layer lower portion 25a; The metal layer 29a is formed on the control gate electrode layer 27a. With this configuration, the gate electrodes MG1, MG2, and MG3 of the memory cell transistors MT1, MT2, and MT3 are two layers in which the floating gate electrode layer 23a and the control gate electrode layer 27a are electrically separated by the first inter-electrode insulating layer 24a. It has a gate structure. An impurity diffusion layer 20 as a source / drain region is formed near the surface of the semiconductor substrate 21 so as to sandwich the gate electrodes MG1, MG2, and MG3 of the memory cell transistors MT1, MT2, and MT3.

  The gate electrode SG of the select gate transistor ST is formed on the gate insulating layer 22b. The gate electrode SG is provided via the gate insulating layer 22b, and a lower gate electrode layer 23b located on the same plane as the upper surface of the floating gate electrode layer 23a, and a second electrode formed on the lower gate electrode layer 23b. An inter-layer insulating layer 24b, an opening 28b penetrating the second inter-electrode insulating layer 24b on the upper surface of the second inter-electrode insulating layer 24b and having a bottom in the lower gate electrode layer 23b, and a second inter-electrode insulating layer 24b An upper gate electrode layer lower portion 25b formed on the upper surface of the upper gate electrode layer and an upper gate electrode layer upper portion 26b formed on the upper gate electrode layer lower portion 25b and in the opening 28b and electrically connected to the lower gate electrode layer 23b. The upper gate electrode layer 27b and the metal layer 29b formed on the upper gate electrode layer 27b. With this configuration, the gate electrode SG of the select gate transistor ST has a one-layer gate structure in which the lower gate electrode layer 23b and the upper gate electrode layer 27b are electrically connected. An impurity diffusion layer 20 as a source / drain region is formed near the surface of the semiconductor substrate 21 so as to sandwich the gate electrode SG.

  The gate electrode TG of the MOS transistor TR is formed on the gate insulating layer 22c. The gate electrode TG is provided via the gate insulating layer 22c, and a lower gate electrode layer 23c located on the same plane as the upper surface of the floating gate electrode layer 23a, and a second electrode formed on the lower gate electrode layer 23c. An inter-layer insulating layer 24c, an opening 28c penetrating through the second inter-electrode insulating layer 24c on the upper surface of the second inter-electrode insulating layer 24c and having a bottom in the lower gate electrode layer 23c, and the second inter-electrode insulating layer 24c The upper gate electrode layer lower portion 25c formed on the upper surface of the upper gate electrode layer and the upper gate electrode layer upper portion 26c formed in the upper gate electrode layer lower portion 25c and the opening 28c and electrically connected to the lower gate electrode layer 23c. The upper gate electrode layer 27c and the metal layer 29c formed on the upper gate electrode layer 27c. With this configuration, the gate electrode TG of the MOS transistor TR has a one-layer gate structure in which the lower gate electrode layer 23c and the upper gate electrode layer 27c are electrically connected. Further, an impurity diffusion layer 20 as a source / drain region is formed near the surface of the semiconductor substrate 21 so as to sandwich the gate electrode TG.

Note that “on the same plane” as used herein is not limited to being completely on the same plane, and within a range of manufacturing variations, different planes are on the same plane. .

  Next, a method for manufacturing the NAND nonvolatile memory according to the first embodiment will be described with reference to FIGS.

  3 to 13 are diagrams schematically showing a manufacturing process of the NAND-type nonvolatile memory according to the first embodiment, and each drawing is a cross-sectional view taken along line AA in FIG.

  First, as shown in FIG. 3, the upper surface of the semiconductor substrate 21 in the memory cell transistor region 11a is covered with a first mask material 30a made of, for example, a photoresist, and the semiconductors in the select gate transistor region 11b and the peripheral circuit region 12 are etched. The upper surface of the substrate 21 is removed. By this removal step, the upper surfaces of the select gate transistor region 11b and the peripheral circuit region 12 as the second upper surface region are positioned on a plane below the upper surface of the memory cell transistor region 11a as the first upper surface region. Here, the height difference (hereinafter referred to as a step) H1 between the upper surface of the memory cell transistor region 11a and the upper surface of the select gate transistor region 11b and the peripheral circuit region 12 is formed to be 20 nm or more. The upper limit value of the step H1 will be described later. Here, “height” means a height from the upper surface of the semiconductor substrate 21.

Next, as shown in FIG. 4, the first mask material 30 a is removed, and for example, a silicon oxide film (SiO ₂₎ is commonly formed on the semiconductor substrate 21 in the memory cell transistor region 11 a, the select gate transistor region 11 b, and the peripheral circuit region 12. ) Or a silicon nitride film (SiN) is formed to the same film thickness, for example, about 50 to 100 mm. Here, the film thickness of the gate insulating layer 22 is the same in the memory cell transistor region 11a, the select gate transistor region 11b, and the peripheral circuit region 12.

  Next, as shown in FIG. 5, on the gate insulating layer 22 in the memory cell transistor region 11a, the selection gate transistor region 11b, and the peripheral circuit region 12, a floating gate electrode layer or lower layer made of, for example, polycrystalline silicon is used. The first gate electrode layer 23 serving as the gate electrode layer is formed to have the same film thickness, for example, about 70 nm to 100 nm. Here, the upper surface of the first gate electrode layer 23 in the memory cell transistor region 11a is located above the upper surfaces of the first gate electrode layer 23 in the selection gate transistor region 11b and the peripheral circuit region 12 by a step H1. Note that the polycrystalline silicon of the first gate electrode layer 23 can be doped with an impurity such as phosphorus, arsenic, or boron.

  The “same film thickness” as used herein is not limited to the same film thickness, and different film thicknesses are within the range of manufacturing variation (in this embodiment, about 10% variation). And within the category of the same film thickness.

  Next, as shown in FIG. 6, the upper part of the first gate electrode layer 23 in the memory cell transistor region 11a is removed, and the first gate electrode layer in the memory cell transistor region 11a, the selection gate transistor region 11b, and the peripheral circuit region 12 is removed. The upper surface of 23 is positioned on the same plane. For this removal step, for example, planarization by CMP (Chemical Mechanical Polishing) is used. In this CMP process, not only the upper portion of the first gate electrode layer 23 in the memory cell transistor region 11a but also the upper portion of the first gate electrode layer 23 in the selection gate transistor region 11b and the peripheral circuit region 12 is removed to some extent. The film thickness of the first gate electrode layer 23 in the cell transistor region 11a is about 30 nm, and the film thickness of the first gate electrode layer 23 in the select gate transistor region 11b and the peripheral circuit region 12 is 50 nm or more. Further, without performing planarization by CMP, polycrystalline silicon is formed by CVD on the selection gate transistor region 11b and the first gate electrode layer 23 in the peripheral circuit region 12, and the memory cell transistor region 11a and the selection gate transistor region 11b. In addition, the upper surface of the first gate electrode layer 23 in the peripheral circuit region 12 can be located on the same plane.

  Here, “located on the same plane” is not limited to being completely on the same plane, but is different planes within the range of manufacturing variations (in this embodiment, about 15 nm). In some cases, they are included in the category of the same plane.

  Next, a second mask material (not shown) made of, for example, a silicon nitride film is formed on the first gate electrode layer 23, and the first gate electrode layer 23 and the gate insulating layer 22 are formed using the second mask material as a mask. Then, the semiconductor substrate 21 is etched to form an element isolation groove (not shown) reaching the semiconductor substrate 21, and, for example, a silicon oxide film (SiO 2) is buried in the element isolation groove to form an element isolation insulating film (FIG. (Not shown). Next, after making the upper surface of the element isolation insulating film substantially coincide with the upper surface of the first gate electrode layer 23, the second mask material is removed. By this process, the element isolation insulating film 14 is formed. Note that the height of the element isolation insulating film 14 from the surface of the semiconductor substrate 21 in the memory cell region 11 can be made lower than the height in the peripheral circuit region 12. In addition, a so-called post-gate forming process in which the gate insulating layer 22 is formed after the element isolation insulating film 14 is formed is also possible.

  Next, as shown in FIG. 7, an interelectrode insulating layer 24 made of, for example, an ONO (Oxide-Nitride-Oxide) film is formed on the first gate electrode layer 23 to a film thickness of about 12 nm to 17 nm. On the inter-layer insulating layer 24, a second gate electrode layer lower portion 25 made of, for example, polycrystalline silicon and later serving as a lower portion of the control gate electrode layer or a lower portion of the upper gate electrode layer is formed to a thickness of about 30 nm to 60 nm. The lower portion 25 of the second gate electrode layer is used as a protective film for preventing fluctuations in electrical characteristics of the interelectrode insulating layer 24. If the fluctuations in electrical characteristics can be allowed in operation, the second gate electrode layer 25 can be used. The electrode layer lower portion 25 may not be formed.

  Next, as shown in FIG. 8, a third mask material 30 b made of, for example, a photoresist is formed on the second gate electrode layer lower portion 25. The third mask material 30b has openings 31 for forming the openings 28b and 28c of the second inter-electrode insulating layers 24b and 24c shown in FIG. Note that the third mask material 30b can be a hard mask made of, for example, a silicon nitride film, BSG (Boron Silicate Glass), or TEOS (Tetra Ethyl Ortho Silicate).

  Next, as shown in FIG. 9, the second gate electrode layer lower portion 25 and the interelectrode insulating layer 24 in the opening 31 of the third mask material 30b are removed by etching using the third mask material 30b as a mask, and the first Openings 28b and 28c exposing the surface of the gate electrode layer 23 are formed. Here, in forming the openings 28b and 28c, overetching is performed in order to reliably expose the surface of the first gate electrode layer 23. Therefore, the upper part of the first gate electrode layer 23 in the interelectrode insulating layer 24 is shaved by about 40 nm. However, since the film thickness of the first gate electrode layer 23 in the selection gate transistor region 11b and the peripheral circuit region 12 is 50 nm or more, it reaches the surface of the gate insulating layer 22 through the first gate electrode layer 23. The bottoms of the openings 28b and 28c are located in the first gate electrode layer 23. After that, in order to remove a natural oxide film (not shown) made of SiO 2 formed on the exposed surface of the first gate electrode layer 23 in the openings 28b and 28c, for example, hydrofluoric acid such as hydrogen fluoride or diluted hydrofluoric acid. Wash with a chemical solution. In this cleaning, any chemical solution other than hydrofluoric acid may be used as long as the natural oxide film formed on the surface of the first gate electrode layer 23 and the gate insulating layer 22 can be removed.

  Next, as shown in FIG. 10, on the second gate electrode layer lower portion 25 so as to fill in the openings 28b and 28c, the control gate electrode layer upper portion or the upper gate electrode layer upper portion is made of, for example, polycrystalline silicon. The second gate electrode layer upper portion 26 is formed to a thickness of about 60 nm to 150 nm. Next, as shown in FIG. 11, a metal layer 29 made of, for example, tungsten is formed on the second gate electrode layer upper portion 26 so as to have a film thickness of about 20 nm to 60 nm. Further, instead of the metal layer 29, for example, a silicide layer may be formed by a salicide process in which titanium, cobalt, or nickel is deposited on the second gate electrode layer upper portion 26 and reacted at a high temperature.

  Next, as shown in FIG. 12, a fourth mask material 30 c made of, for example, a photoresist is formed on the metal layer 29. The fourth mask material 30c covers portions that will later become the gate electrodes MT, SG, and TG. Further, the fourth mask material 30c can be processed by using, for example, a silicon nitride film or a hard mask made of BSG or TEOS instead of the photoresist.

  Next, as shown in FIG. 13, the metal layer 29, the second gate electrode layer upper portion 26, the second gate electrode layer lower portion 25, and the interelectrode insulating layer 24 are formed by anisotropic etching using the fourth mask material 30c as a mask. Remove. Next, etching is advanced by the thickness (H2 in the drawing) of the first gate electrode layer 23 in the memory cell transistor region 11a. At this time, since the gate insulating layer 22 has the same film thickness in the memory cell transistor region 11a, the selection gate transistor region 11b, and the peripheral circuit region 12, it is masked by the fourth mask material 30c in the selection gate transistor region 11b and the peripheral circuit region 12. The first gate electrode layer 23 having a film thickness H1 equal to the step H1 between the upper surface of the memory cell transistor region 11a and the upper surfaces of the selection gate transistor region 11b and the peripheral circuit region 12 remains in the unexposed portion.

  Next, as shown in FIG. 14, the etching is further advanced, and the first gate electrode layer 23 remaining in the select gate transistor region 11b and the peripheral circuit region 12 is removed until the gate insulating layer 22 is exposed. At this time, the portion of the gate insulating layer 22d that is not masked by the fourth mask material 30c in the memory cell transistor region 11a is also etched, and the film thickness is reduced from H3 in the drawing to H4 in the drawing. Here, if the gate insulating layer 22d is completely removed before the first gate electrode layer 23 in the select gate transistor region 11b and the peripheral circuit region 12 is completely removed, the semiconductor substrate 21 under the gate insulating layer 22 is removed and the memory is removed. The electrical characteristics of the cell transistor MT will fluctuate. Therefore, the upper limit value of the step H1 in the figure is determined by the selection ratio of the first gate electrode layer 23 to the gate insulating layer 22. Specifically, the step H 1 needs to be lower than the product of H 3, which is the thickness of the gate insulating layer 22, and the etching selectivity of the first gate electrode layer 23 with respect to the gate insulating layer 22. By this etching process, the first gate electrode layer 23 becomes the floating gate electrode layer 23a and the lower gate electrode layers 23b and 23c, and the inter-electrode insulating layer 24 becomes the first inter-electrode insulating layer 24a and the second inter-electrode insulating layers 24b and 24c. The second gate electrode layer 27 comprising the second gate electrode layer lower portion 25 and the second gate electrode layer upper portion 26 is the control gate electrode layer 27a and the upper gate electrode layers 27b and 27c, and the metal layer 29 is the metal layer 29a, Divided into 29b and 29c, respectively.

  Next, as shown in FIG. 15, the gate insulating layer 22 is removed using the fourth mask material 30c as a mask, and then the fourth mask material 30c is removed, whereby the gate electrodes MG1, MG2, MG3, SG, TG are removed. Is formed. Thereafter, the impurity diffusion layer 20 is formed by the ion implantation method using the gate electrodes MG1, MG2, MG3, SG, and TG as a mask. Further, in order to prevent the impurity diffusion layer 20 from being divided due to a step on the surface of the semiconductor substrate 21 between the select gate transistor ST and the memory cell transistor MT1, the incident direction of impurity ions can be inclined obliquely from the direction perpendicular to the semiconductor substrate 21. is there. Further, the fourth mask material 30c may be completely removed by anisotropic etching when forming the gate electrodes MG1, MG2, MG3, SG, and TG. In addition, the gate insulating layer 22 can be etched using the gate electrodes MG1, MG2, MG3, SG, and TG as a mask.

  Thereafter, an inter-gate electrode insulating film (not shown) is buried so as to cover the gate electrodes MG1, MG2, MG3, SG, and TG, and an interlayer insulating layer is formed on the inter-gate electrode insulating film. Thereafter, a contact electrode 17 reaching the impurity diffusion layer 20 and a gate contact electrode 18 reaching the contour metal layer 29 are formed through the inter-gate electrode insulating layer and the interlayer insulating layer, respectively. Further, the contact electrode 17 and the gate contact electrode 18 are formed. And upper metal wiring (not shown) electrically connected to each other are formed on the interlayer insulating layer.

  Further, without performing the step of removing the gate insulating layer 22 in the memory cell region 11a using the fourth mask material 30c shown in FIG. 15 as a mask, the above-described interlayer insulating layer, contact electrode 17, gate contact electrode 18 and upper metal wiring It is also possible to form

  Through the above steps, the NAND nonvolatile memory shown in FIGS. 1 and 2 is obtained.

  According to the NAND type nonvolatile memory of the present embodiment, the upper surface of the select gate transistor region 11b and the upper surface of the peripheral circuit region 12 of the semiconductor substrate 21 are provided on a plane located below the upper surface of the memory cell transistor region 11a. The floating gate electrode layer 23a of the memory cell transistor MT, the select gate transistor region 11b and the peripheral circuit region 12 which are the second upper surface regions, and the lower gate electrode layers 23b and 23c of the select gate transistor ST and MOS transistor TR are respectively provided. The upper surface is provided on the same plane. Therefore, the floating gate electrode layer 23a of the memory cell transistor MT is formed with a thin film thickness, while the lower gate electrode layers 23b and 23c of the selection gate transistor ST and the MOS transistor TR are more than the floating gate electrode layer 23a of the memory cell transistor MT. The lower portions of the openings 28b and 28c of the interelectrode insulating layer 24 of the select gate transistor ST and the MOS transistor TR are located in the lower gate electrode layers 23b and 23c. Accordingly, it is possible to reduce the inter-cell interference of the memory cell transistor and to prevent an electrical short circuit between the gate electrode SG of the selection gate transistor and the semiconductor substrate 21.

  Further, according to the method for manufacturing the NAND type nonvolatile memory of the present embodiment, the memory cell transistor region 11a on the upper surface of the semiconductor substrate 21 and the select gate transistor whose upper surface is located on a plane below the memory cell transistor region 11a. The region 11b and the peripheral circuit region 12 are formed, the floating gate electrode layer 23a is formed on the memory cell transistor region 11a via the gate insulating layers 22a, 22b, and 22c, and the select gate transistor region 11b and the peripheral circuit region 12 are formed. By forming the lower gate electrode layers 23b and 23c so that their upper surfaces are located on the same plane, the thickness of the floating gate electrode layer 23a is reduced, while the thickness of the lower gate electrode layers 23b and 23c is reduced. It can be made thicker than the film thickness of the floating gate electrode layer 23a. That is, even if the floating gate electrode layer 23a is thinned by adjusting the step H1 between the upper surface of the memory cell transistor region 11a and the upper surfaces of the select gate transistor region 11b and the peripheral circuit region 12, the lower gate electrode layers 23b, 23c The upper surface of the gate insulating layers 22b and 22c is not exposed through the lower gate electrode layers 23b and 23c by etching when the openings 28b and 28c are formed in the second inter-electrode insulating layers 24b and 24c. It can be thick enough. Therefore, when the natural oxide film formed on the exposed surfaces of the subsequent lower gate electrode layers 23b and 23c is removed, the gate insulating layers 22b and 22c are not simultaneously removed, and the selection gate transistor ST and the MOS transistor TR are removed. It is possible to easily obtain a NAND-type nonvolatile memory capable of preventing an electrical short circuit between the gate electrodes SG and TG of the semiconductor substrate 21 and the semiconductor substrate 21 and reducing the inter-cell interference of the memory cell transistors. it can.

  The top surfaces of the gate electrodes MG1, MG2, MG3, SG, and TG of the memory cell transistor MT, select gate transistor ST, and MOS transistor TR are located on the same plane. Accordingly, the flatness of CMP using the gate electrodes MG1, MG2, MG3, SG, and TG as stoppers is improved.

  In the present embodiment, a plurality of active areas 13 can be arranged in the peripheral circuit region 12 to form a plurality of MOS transistors TR. A plurality of MOS transistors TR are formed on one active area 13. It is also possible to obtain the same effect as in this embodiment regardless of whether the MOS transistor TR is an N-type MOS transistor or a P-type MOS transistor.

[Modification of Manufacturing Method of First Embodiment]
16 to 18 are process cross-sectional views schematically showing the manufacturing process of the NAND-type nonvolatile memory according to the modification of the manufacturing method of the first embodiment of the present invention, and each figure is A in FIG. It is sectional drawing which follows the -A line. Hereinafter, for convenience of explanation, the same or similar parts as those in the first embodiment are denoted by the same reference numerals, and different parts from the above-described embodiment will be mainly described.

  First, the first gate electrode layer 23 is formed on the upper surface of the semiconductor substrate 21 through the same process as in the first embodiment. Next, as shown in FIG. 16, a fifth mask material 30 d made of, for example, a photoresist is formed on the first gate electrode layer 23 in the select gate transistor region 11 b and the peripheral circuit region 12. Next, as shown in FIG. 17, the upper portion of the first gate electrode layer 23 on the memory cell transistor region 11a protruding upward from the upper surface of the first gate electrode layer 23 on the select gate transistor region 11b and the peripheral circuit region 12. That is, the film thickness corresponding to the difference in height of the first gate electrode layer 23 in the memory cell transistor region 11a, the select gate transistor region 11b, and the peripheral circuit region 12 is replaced with the silicon oxide film 23d by thermal oxidation.

Next, as shown in FIG. 18, the silicon oxide film 23d is removed by etching using, for example, hydrogen fluoride. Thereafter, by removing the fifth mask material 30d, the upper surfaces of the first gate electrode layers 23 in the select gate transistor region 11b, the peripheral circuit region 12, and the memory cell transistor region 11a are positioned on the same plane. For etching the silicon oxide film 23d, for example, dry etching with difluorocarbon (CF ₂ ) can be used. It is also possible to increase the oxidation rate of the first gate electrode layer 23 in the memory cell transistor region 11a by doping impurities into the first gate electrode layer 23 in the memory cell transistor region 11a. Since the subsequent steps are the same as those in the first embodiment described above, description thereof is omitted.

  Also in the modified example, the floating gate electrode layer 23a on the memory cell transistor region 11a has a small film thickness, and the lower gate electrode layers 23b and 23c on the selection gate transistor region 11b and the peripheral circuit region 12 have a large film thickness. Can be formed. Therefore, a NAND nonvolatile memory having the same effect as that of the first embodiment can be manufactured.

  Further, the first gate electrode in the selection gate transistor region 11b, the peripheral circuit region 12, and the memory cell transistor region 11a can be obtained without removing the top surfaces of the selection gate transistor region 11b and the first gate electrode layer 23 in the peripheral circuit region 12 by CMP or the like. Since the height of the upper surface of the layer 23 is made equal, there is little variation in the height of the gate electrodes MG and TG from the upper surface of the semiconductor substrate 21.

[Variation of Nonvolatile Memory of First Embodiment]
19 and 20 are schematic cross-sectional views of a modification of the NAND nonvolatile memory according to the first embodiment of the present invention. FIG. 19 is a modification of the NAND nonvolatile memory according to the first embodiment. FIG. 20 is a cross-sectional view taken along line AA of FIG. This modification differs from the first embodiment described above in that the opening of the second inter-electrode insulating layer in the select gate transistor has a structure in which one half in the width direction of the upper surface of the lower gate electrode layer is exposed, the MOS The gate electrode of the transistor has a structure without the second inter-electrode insulating layer and the lower gate electrode layer. Hereinafter, for convenience of explanation, the same or similar parts as those in the above-described first embodiment are denoted by the same reference numerals, and different parts from those in the above-described first embodiment will be mainly described.

  As shown in FIG. 19, in the select gate transistor region 11b, the opening 28b of the second interelectrode insulating layer 24b has a width extending from the center of the line width of the select gate lines SGL1, SGL2, and SGL3 to the edge in the width direction. And extends in the X direction in the figure. In the peripheral circuit region 12, the opening 28c in the interelectrode insulating layer is provided so as to include the MOS transistor TR formed at the intersection of the active area 13 and the gate electrode TG.

  As shown in FIG. 20, in the gate electrode SG of the select gate transistor ST, the opening 28b of the second inter-electrode insulating layer 24b is provided in a region extending from the center of the upper surface of the lower gate electrode layer 23b to the edge in the width direction. Thus, one half of the upper surface of the lower gate electrode layer 23b is exposed. Further, in the gate electrode TG of the MOS transistor TR, the second inter-electrode insulating layer and the lower gate electrode layer are not provided, and the gate electrode TG is connected to the upper gate electrode layer lower portion 25c provided on the gate insulating layer 22c. The upper gate electrode layer lower portion 25c is formed in a single layer structure of a second gate electrode layer 27 including an upper gate electrode layer upper portion 26c provided on the upper gate electrode layer lower portion 25c. Since the structure other than the above is the same as that of the first embodiment, the description thereof is omitted.

  21 to 23 are drawings schematically showing a manufacturing process of a modification of the NAND nonvolatile memory according to the first embodiment. Each drawing is a cross-sectional view taken along line AA in FIG.

  First, the process up to the step of forming the second gate electrode layer lower portion 25 on the interelectrode insulating layer 24 is the same as that in the first embodiment described above, and thus the description thereof is omitted. Next, as shown in FIG. 21, a third mask material 30 b made of, for example, a photoresist is formed on the second gate electrode layer lower portion 25. This third mask material 30b has an opening 31 for forming the openings 28b and 28c of the interelectrode insulating film shown in FIG.

  Next, as shown in FIG. 22, the second gate electrode layer lower portion 25 and the interelectrode insulating layer 24 are removed by etching using the third mask material 30b as a mask, and the opening exposing the surface of the first gate electrode layer 23 28b and 28c are formed. Here, since the film thickness of the first gate electrode layer 23 in the selection gate transistor region 11b and the peripheral circuit region 12 is 50 nm or more, the surface of the gate insulating layer 22 penetrates the first gate electrode layer 23. The bottoms of the openings 28b and 28c are formed in the first gate electrode layer 23 without being exposed. Since the subsequent steps up to the step of forming the metal layer 29 on the second gate electrode layer upper portion 26 are the same as those in the first embodiment, description thereof will be omitted.

  Next, as shown in FIG. 23, a fourth mask material 30c made of, for example, photoresist is formed on the metal layer 29 so as to cover portions other than portions that will later become the gate electrodes MG1, MG2, MG3, SG, and TG. Thereafter, the metal layer 29, the second gate electrode layer upper portion 26, the second gate electrode layer lower portion 25, the interelectrode insulating layer 24, and the first gate electrode layer 23 are removed by anisotropic etching using the fourth mask material 30c as a mask. To do. At this time, in the gate electrode SG of the select gate transistor ST, the opening 28b of the second interelectrode insulating layer 24b has a structure in which one half of the upper surface of the lower gate electrode layer 23b is exposed, and in the gate electrode TG of the MOS transistor TR In this structure, the second inter-electrode insulating layer and the first gate electrode layer are not provided. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  Even if the opening 28b of the second interelectrode insulating layer 24b of the select gate transistor ST has a structure in which one half of the upper surface of the lower gate electrode layer 23b is exposed as in the present embodiment, the floating gate of the memory cell transistor MT The electrode layer 23a can be made thin, while the lower gate electrode layer 23b of the select transistor ST and the MOS transistor TR can be made thicker than the floating gate electrode layer 23a. Therefore, the same effect as the first embodiment can be obtained.

  In the gate electrode SG of the select gate transistor ST, the opening 28b of the second inter-electrode insulating layer 24b exposes one half of the upper surface in the width direction of the lower gate electrode layer 23b, and the lower gate electrode layer 23b and the second gate Since the electrode layer 27 is electrically connected, the electric resistance of the gate electrode SG can be lowered. Further, since the gate electrode TG of the MOS transistor TR has a structure in which the second inter-electrode insulating layer does not exist, the electric resistance can be further reduced.

  Further, since the distance between the gate electrode MG of the memory cell transistor MT1 and the end of the opening 28b of the gate electrode SG of the selection gate transistor ST can be increased in the memory cell region 11, an opening is formed in the third mask material 30b. Lithographic alignment margin when forming 31 is improved.

  In the present embodiment, the gate electrode SG of the selection gate transistor ST in the selection gate transistor region 11b has a structure that does not include the second inter-electrode insulating layer and the first gate electrode layer like the gate electrode TG of the MOS transistor TR. The second inter-electrode insulating layer 24c having the opening 28c having the same structure as the gate electrode SG of the selection gate transistor ST is provided in the gate electrode TG of the MOS transistor TR in the peripheral circuit region 12. Is also possible.

  Further, the opening 28c of the interelectrode insulating layer in the peripheral circuit region 12 may have a structure that spans part of the MOS transistor TR and the active area 13, for example, a region in the X direction in the drawing is included in the active area 13. Of course, it may be provided so as to include the gate electrode TG.

[Second Embodiment]
FIG. 24 is a schematic diagram of a NAND nonvolatile memory according to the second embodiment, and is a cross-sectional view taken along the line AA of FIG. This embodiment differs from the first embodiment described above in that the film thickness of the second gate insulating layer of the MOS transistor TR in the peripheral circuit region is the same as that of the first gate insulating layer of the memory cell transistor MT and select gate transistor ST. The film thickness of the lower gate electrode layer is smaller than the film thickness of the lower gate electrode layer of the select gate transistor ST because the film thickness is larger than the film thickness and the film thickness of the second gate insulating layer is increased. It is in. Hereinafter, for convenience of explanation, the same or similar parts as those in the first embodiment described above are denoted by the same reference numerals, and description will be made focusing on the characteristic parts of the present embodiment.

  As shown in FIG. 24, in this embodiment, the first gate insulating layer 22a of the memory cell transistor MT and the first gate insulating layer 22b of the select gate transistor ST are formed to have the same film thickness. The thickness of the second gate insulating layer 32c is formed to be thicker than the thickness of the first gate insulating layers 22a and 22b of the memory cell transistor MT and select gate transistor ST. Further, the film thickness of the lower gate electrode layer 23c of the MOS transistor TR is smaller than the film thickness of the lower gate electrode layer 23b of the select gate transistor ST because the film thickness of the second gate insulating layer 32c is increased. Yes. Since the structure other than the above is the same as that of the first embodiment, the description thereof is omitted.

  Next, a method for manufacturing the NAND nonvolatile memory according to the second embodiment will be described with reference to FIGS.

  25 to 29 are diagrams schematically showing a manufacturing process of the NAND nonvolatile memory according to the second embodiment, and each drawing is a cross-sectional view taken along the line AA in FIG.

  First, on the upper surface of the semiconductor substrate 21, a memory cell transistor region 11a that is a first upper surface region, a selection gate transistor region 11b that is a second upper surface region whose upper surface is located on a plane below the first upper surface region, and peripheral circuits The process up to the formation of the region 12 is the same as that in the first embodiment described above, and a description thereof will be omitted.

Next, as shown in FIG. 25, a _second layer made of, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) commonly used for the memory cell transistor region 11a, the select gate transistor region 11b, and the peripheral circuit region 12 is used. The gate insulating layer 32 is formed to a thickness of about 300 to 400 mm. Here, the film thickness of the second gate insulating layer 32 is the same in the memory cell transistor region 11a, the select gate transistor region 11b, and the peripheral circuit region 12. Here, the difference in height between the upper surface of the memory cell transistor region 11a of the semiconductor substrate 21 and the upper surfaces of the select gate transistor region 11b and the peripheral circuit region 12, that is, the step H5 is formed to be 60 nm or more. The upper limit value of the step H5 will be described later.

Next, as shown in FIG. 26, a first mask material 33 made of, for example, a photoresist is formed on the second gate insulating layer 32 in the peripheral circuit region 12. Next, as shown in FIG. 27, using the first mask material 33 as a mask, the second gate insulating layer 32 in the region other than the peripheral circuit region 12 is removed by wet etching using, for example, hydrogen fluoride or hydrofluoric acid. For the etching of the second gate insulating layer 32, for example, dry etching using difluorocarbon (CF ₂ ) can be used.

  Next, as shown in FIG. 28, on the upper surface of the semiconductor substrate 21 in the select gate transistor region 11b and the memory cell transistor region 11a, a first gate insulating layer 22 made of a silicon oxide film, for example, by thermal oxidation is formed with a thickness of 50 to 100 mm. Form to the extent. At this time, since the peripheral circuit region 12 is also thermally oxidized at the same time, the thickness of the second gate insulating layer 32 in the peripheral circuit region 12 is about 350 to 500 mm.

  By using these steps, the second gate insulating layer 32 having a thickness larger than that of the memory cell region 11 can be formed in the peripheral circuit region 12. The first and second gate insulating layers 22 and 32 can also be formed by a CVD method. The first and second gate insulating layers 22 and 32 are silicon nitride by heating in a nitrogen atmosphere. It is also possible to form a film.

  Since the subsequent steps up to the step of forming the gate electrodes MG1, MG2, MG3, SG, and TG are the same as those in the first embodiment, description thereof is omitted. Next, as shown in FIG. 29, a second gate electrode layer 27 comprising a metal layer 29, a second gate electrode layer upper portion 26, and a second gate electrode layer lower portion 25 by anisotropic etching using the fourth mask material 30c as a mask. And the interelectrode insulating layer 24 are removed. Next, etching is advanced by the thickness (H2 in the drawing) of the first gate electrode layer 23 in the memory cell transistor region 11a. At this time, the film thickness of the portion of the first gate electrode layer 23 not masked by the fourth mask material 30c is H5 in the drawing in the selection gate transistor region 11b, and the second gate insulating layer from H5 in the peripheral circuit region 12 H6 in the figure, which is small by the difference in film thickness between 32 and the first gate insulating layer 22. Therefore, the upper limit value of H5 in the figure is determined by the selection ratio of the first gate electrode layer 23 to the first gate insulating layer 22. Specifically, H5 needs to be lower than the product of H3, which is the thickness of the first gate insulating layer 22, and the etching selectivity of the first gate electrode layer 23 with respect to the first gate electrode layer 23. Since the subsequent steps are the same as those in the first embodiment described above, description thereof is omitted.

  Also in this embodiment, the same effect as the first embodiment can be obtained. Further, since the thickness of the gate insulating layer 22c of the MOS transistor TR is larger than the thickness of the gate insulating layer 22b of the selection gate transistor ST, the MOS transistor TR is changed to a high breakdown voltage transistor, and the selection gate transistor ST is changed. It can be made into a transistor with a high operating speed.

[Third Embodiment]
FIG. 30 is a schematic diagram of a NAND nonvolatile memory according to the third embodiment, and is a cross-sectional view taken along the line AA of FIG. In the NAND nonvolatile memory according to the third embodiment, a thick first gate insulating layer is provided on a first upper surface region of a semiconductor substrate having the same plane, and the second upper surface region is provided with a first gate insulating layer. The upper surface of the second gate insulation is positioned on a plane below the upper surface of the first gate insulating layer by providing the second gate insulating layer having a smaller thickness, and the memory cell transistor is floated on the first gate insulating layer. By providing the gate electrode layer and providing the lower gate electrode layer of the selection gate transistor on the second gate insulating layer, the upper surfaces of the floating gate electrode layer and the lower gate electrode layer are in the same plane, and the floating gate electrode layer It is thin and has a structure in which the lower gate electrode layer is thicker than the floating gate electrode layer. For convenience of explanation, the same or similar parts as those in the first embodiment described above are denoted by the same reference numerals, and description will be made focusing on the characteristic parts of the present embodiment.

  As shown in FIG. 30, in the NAND-type nonvolatile memory according to the present embodiment, the upper surface of the memory cell transistor region 11a that is the first upper surface region of the semiconductor substrate 21, the select gate transistor region 11b that is the second upper surface region, and the periphery The upper surface of the circuit region 12 is located on the same plane. Further, the film thickness of the first gate insulating layer 41 of the memory cell transistor MT is thicker than the film thickness of the second gate insulating layers 42b and 42c of the select gate transistor ST and the MOS transistor TR. Furthermore, the upper surface of the floating gate electrode layer 23a of the memory cell transistor MT and the upper surfaces of the lower gate electrode layers 23b and 23c of the select gate transistor ST and the peripheral circuit MOS transistor TR are provided on the same plane. With this configuration, the film thickness of the floating gate electrode layer 23a of the memory cell transistor MT is thin, and the film thickness of the lower gate electrode layers 23b and 23c of the select gate transistor ST and the MOS transistor TR of the peripheral circuit is the same as that of the floating gate electrode layer 23a. It is thicker than the film thickness. Since the structure other than the above is the same as that of the first embodiment, the description thereof is omitted.

  Next, a method for manufacturing the NAND nonvolatile memory according to the third embodiment will be described with reference to FIGS.

  FIG. 31 to FIG. 34 are drawings schematically showing the manufacturing process of the NAND-type nonvolatile memory according to the third embodiment, and each drawing is a cross-sectional view taken along the line AA in FIG.

First, as shown in FIG. 31, a first gate insulating layer 41 made of, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is formed on a semiconductor substrate 21 to a film thickness of about 400 to 800 mm. Next, a first mask material 49 made of, for example, a photoresist is formed on the first gate insulating layer 41 in the memory cell transistor region 11a. Thereafter, as shown in FIG. 32, the first gate insulating layer 41 in the region other than the memory cell transistor region 11a is removed by wet etching with, for example, hydrogen fluoride or hydrofluoric acid using the mask material 49 as a mask. Further, for this etching, for example, dry etching with difluorocarbon (CF ₂ ) can be used.

  Next, as shown in FIG. 33, after removing the first mask material 49, the second gate insulating layer 42 is formed on the upper surface of the semiconductor substrate 21 in the select gate transistor region 11 b and the peripheral circuit region 12 by, for example, thermal oxidation. The film thickness is smaller than that of one gate insulating layer 41 and is about 30 to 50 mm. At this time, since the memory cell transistor region 11a is also thermally oxidized at the same time, the thickness of the first gate insulating layer 41 in the memory cell transistor region 11a is about 50 to 100 mm. By using these steps, a thick first gate insulating layer 41 is formed in the memory cell transistor region 11a of the semiconductor substrate 21, and a first gate insulating layer is formed in the select gate transistor region 11b and the peripheral circuit region 12. The second gate insulating layer 42 having a thickness smaller than that of the first gate insulating layer 42 is formed, and the upper surface of the second gate insulating layer 42 can be positioned on a plane below the upper surface of the first gate insulating layer 41.

  Here, when forming the openings 28b and 28c, the thickness of the first gate insulating layer 41 indicated by H7 in the drawing and the second gate insulating layer 42 so that the upper surface of the second gate insulating layer 42 is not exposed. The difference in film thickness is formed to 20 nm or more. The first and second gate insulating layers 41 and 42 can also be formed by CVD, and the material of the first and second gate insulating layers 41 and 42 is silicon by heating in a nitrogen atmosphere. It is also possible to use a nitride film.

  Since the subsequent steps to the step of forming the gate electrodes MG1, MG2, MG3, SG, and TG are the same as those in the first embodiment, description thereof is omitted. Next, as shown in FIG. 34, a second gate electrode layer comprising a metal layer 29, a second gate electrode layer upper portion 26 and a second gate electrode layer lower portion 25 by anisotropic etching using the fourth mask material 30c as a mask. 27 and the interelectrode insulating layer 24, and then the etching is advanced by the thickness of the first gate electrode layer 23 (H2 in the drawing) in the memory cell transistor region 11a. At this time, the thickness of the first gate electrode layer 23 in the portion of the selection gate transistor region 11b and the peripheral circuit region 12 that is not masked by the fourth mask material 30c is set to be the second gate insulating layer 42 and the first gate insulating layer 22. It becomes equal to H7 in the figure which is the difference in film thickness. Therefore, the film thickness difference H7 needs to be lower than the product of H3, which is the film thickness of the first gate insulating layer 22, and the etching selectivity of the first gate electrode layer 23 to the first gate insulating layer 22. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  According to the present embodiment, the thick first gate insulating layer 41 is provided on the upper surface of the memory cell transistor region 11 a on the upper surface of the semiconductor substrate 21, and the first upper surface of the select gate transistor region 11 b and the upper surface of the peripheral circuit region 12 are provided. By providing the second gate insulating layer 42 thinner than the thickness of the gate insulating layer 41, the upper surface of the select gate transistor region 11b and the upper surface of the second gate insulating layer 42 on the upper surface of the peripheral circuit region 12 are arranged in the memory cell transistor region. 11a, the floating gate electrode layer 23a of the memory cell transistor MT is formed on the upper surface of the first gate insulating layer 41, and the upper surface of the second gate insulating layer 42 is positioned on the plane below the upper surface of the first gate insulating layer 41. Further, the lower gate electrode layers 23b and 23c of the select gate transistor ST and the MOS transistor TR have the same upper surface. Provided so as to be positioned on the surface.

  Therefore, the floating gate electrode layer 23a of the memory cell transistor MT is formed with a thin film thickness, while the lower gate electrode layers 23b and 23c of the selection gate transistor ST and the MOS transistor TR are more than the floating gate electrode layer 23a of the memory cell transistor MT. The lower portions of the openings 28b and 28c of the interelectrode insulating layer 24 of the select gate transistor ST and the MOS transistor TR are located in the lower gate electrode layers 23b and 23c. Therefore, the same effect as the first embodiment can be obtained.

  Further, since the second gate insulating layers 42b and 42c of the select gate transistor ST and the MOS transistor TR can be thinned, a NAND flash memory having a high switching speed and a high DATA transfer speed can be provided.

  In the present embodiment, the thickness of the second gate insulating layers 42b and 42c can be made different in a range thinner than the thickness of the floating gate electrode layer 23a, and a plurality of MOS transistors TR are provided in the peripheral circuit region 12. When arranged, the film thicknesses of the second gate insulating layers 42c of the plurality of MOS transistors TR can be made different.

[Fourth Embodiment]
The fourth embodiment is an example when the present invention is applied to a NOR type nonvolatile memory.

  FIG. 35 is a plan view schematically showing a NOR type nonvolatile memory according to the fourth embodiment of the present invention, and FIG. 36 is a sectional view taken along the line AA of FIG. For convenience of explanation, the same reference numerals are given to the same or similar parts as those in the first embodiment, and the characteristic parts of the present embodiment will be described.

  As shown in FIG. 35, in the memory cell region 11, a plurality of active areas 13 which are element formation regions in the Y direction in the figure are formed in parallel in a strip shape via the element isolation insulating film 14, and the Y direction in the figure. A plurality of word lines WL1, WL2,..., WL4 are formed in parallel in a strip shape in the X direction in the figure orthogonal to the figure. Further, the plurality of active areas 13 are coupled by an active area extending in the X direction in the figure between the word lines WL2 and WL3, and an impurity diffusion layer having a portion where the plurality of active areas 13 are coupled as a source region. 53. Memory cell transistors MT are formed at intersections of the active area 13 and the word lines WL1, WL2,. The impurity diffusion layer 53 functions as a common source for the memory cell transistors MT2a, MT2b, MT3a, and MT3b formed at the intersections of WL2 and WL3 and the active area 13. A contact electrode 17 for connecting data of the memory cell transistor MT to a bit line (not shown) is disposed between the word lines WL1 and WL2 and between WL3 and WL4. Here, unlike the first embodiment, the selection gate transistor ST is not arranged in the memory cell region 11. In the present embodiment, the number of word lines for each memory block is four. However, the number of word lines may be 16 or 32. Similarly, the number of active areas 13 is two, but a larger number of structures may be used. Further, since the structure of the peripheral circuit region 12 arranged outside the memory cell region 11 is the same as that of the first embodiment, the description thereof is omitted.

  As shown in FIG. 36, unlike the first embodiment, the memory cell region 11 is the same as the first embodiment except that the select gate transistor ST is not arranged. Further, the manufacturing method of this NOR type nonvolatile memory is the same as that of the NAND type nonvolatile memory according to the first embodiment, so that the description thereof is omitted.

  Also in this embodiment, the same effect as the first embodiment can be obtained. Further, the present invention can also be applied to AND-type and DiNOR-type non-volatile memories like the NOR-type non-volatile memories.

  Further, the present embodiment can be modified as in the second and third embodiments.

[Fifth Embodiment]
In the NAND-type nonvolatile memory according to the fifth embodiment, the second gate electrode and the second upper-layer gate electrode are arranged as resistance elements in the peripheral circuit region as resistors.

  FIG. 37 is a schematic plan view of the structure of the NAND nonvolatile memory according to the fifth embodiment. For convenience of explanation, the same or similar parts as those in the first embodiment described above are denoted by the same reference numerals, and characteristic parts of the present embodiment will be described.

  As shown in FIG. 37, one active area 63 surrounded by an element isolation insulating film 64 is provided outside the memory cell region 11, and the active area 63 is provided on the active area 63 and extends in the X direction in the drawing. One gate electrode RG is formed so as to cross over the element isolation insulating film 64. The gate electrode RG is separated from the left and right by the active area 63, a first gate contact electrode 68 a is formed on the gate electrode RG on the element isolation insulating film 64 protruding to the left side of the active area 63, and protrudes to the right side of the active area 63. A second gate contact electrode 68 b is formed on the gate electrode RG on the element isolation insulating film 64. The first and second gate contact electrodes 68a and 68b are respectively connected to electrically separated upper layer wirings (not shown). On the active area 63 in the gate electrode RG, a second interelectrode insulating layer 24c having an opening 28c is provided. The gate electrode RG functions as a resistance element RE using the electrical resistance of the gate electrode RG by applying a voltage to the first gate contact electrode 68a and connecting the second gate contact electrode 68b to the ground, for example. One or more active areas 63 may be arranged, or only one gate electrode RG may be arranged, but a plurality of active areas 63 may be arranged, and a plurality of gate electrodes RG are formed on one active area 63. It may be arranged.

  The cross-sectional structure and the manufacturing method are not described because the manufacturing method of the NAND nonvolatile memory is the same as that of the NAND nonvolatile memory according to the first embodiment.

  In this embodiment, the same effect as that of the first embodiment can be obtained. In addition, the distance and the number of the first and second gate contact electrodes 68a and 68b are changed, the thickness of the lower gate electrode layer 23c or the upper gate electrode layer 27c is changed, and the distance between the second electrodes is changed. The resistance value of the resistance element RE can be easily changed by changing the shape and number of the openings 28c of the insulating layer 24c or changing the shape of the gate electrode RG. It is also possible to produce various resistance elements by arranging a plurality of resistance elements RE in series or in parallel and connecting them with upper metal wiring.

  The shape of the opening 28c of the second interelectrode insulating layer 24c may be a shape other than a rectangle, for example, an ellipse or a cut shape, and includes the first and second gate contact electrodes 68a and 68b. The shape may be sufficient, and the shape including gate electrode RG may be sufficient. In addition, the first and second gate contact electrodes 68 a and 68 b can be disposed on the gate electrode RG on the active area 63. Further, the present embodiment can be modified as in the second and third embodiments.

[Sixth Embodiment]
In the sixth embodiment, a capacitor element using a second gate insulating layer as a charge storage layer is arranged in a peripheral circuit region in a NAND nonvolatile memory.

  FIG. 38 is a schematic plan view of the structure of the NAND nonvolatile memory according to the sixth embodiment. For convenience of explanation, the same or similar parts as those in the first embodiment described above are denoted by the same reference numerals, and characteristic parts of the present embodiment will be described.

  As shown in FIG. 38, on the outside of the memory cell region 11, there is one active area 73 surrounded by an element isolation insulating film 74, and a gate electrode CG and a contact electrode 77 provided on the active area 73. Is formed. A gate contact electrode 78 is formed on the gate electrode GC, and a second interelectrode insulating layer 24c having two openings 76 is provided on the active area 73 in the gate electrode CG. Contact electrode 77 and gate contact electrode 78 are electrically connected to an upper metal wiring (not shown) that is electrically separated. For example, the gate electrode CG functions as a capacitor element CP having a gate insulating layer 22c charge storage layer of the gate electrode CG by applying a voltage to the gate contact electrode 78 and connecting the contact electrode 77 to the ground. One or more active areas 73 may be arranged, a plurality of gate electrodes CG may be arranged, and a plurality of gate electrodes CG may be arranged on one active area 73.

  The cross-sectional structure and the manufacturing method are not described because the manufacturing method of the NAND nonvolatile memory is the same as that of the NAND nonvolatile memory according to the first embodiment.

  In this embodiment, the same effect as that of the first embodiment can be obtained. In addition, the capacitance of the capacitor element CP can be easily changed by changing the area where the gate electrode CG and the active area 73 are in contact with each other. It is also possible to create various capacitances by arranging a plurality of capacitor elements CP in series or in parallel and connecting them with upper metal wiring. It is also possible to change the number of gate contact electrodes 78 and the number of contact electrodes 77.

  In addition, the shape of the opening 76 of the second interelectrode insulating layer 24c can be a shape other than a rectangle, for example, an ellipse or a cut shape, and can include a gate contact electrode 78. The shape may include the gate electrode CG. The gate electrode CG can be formed on the element isolation insulating film 74 by protruding the active area 73. In this case, the gate contact electrode 78 is disposed on the gate electrode protruding on the element isolation insulating film 74. It is also possible to provide an interelectrode insulating layer having an opening 76 on the gate electrode protruding on the element isolation insulating film 74. Further, the present embodiment can be modified as in the second and third embodiments.

  The present invention is not limited to the NAND-type and NOR-type nonvolatile memories of the above-described embodiments, and can be applied to all semiconductor memory devices having a one-layer gate structure and a two-layer gate structure on the same semiconductor substrate. For example, even a DRAM or SRAM using a one-layer gate structure MOS transistor as a memory cell transistor can be applied when a resistor element or a capacitor element having a two-layer gate structure is arranged in the peripheral circuit region 12. In addition, the circuit elements arranged in the peripheral circuit area are not limited to MOS transistors, resistor elements, and capacitor elements, but are arranged in dummy patterns for keeping the density difference between the gate electrodes constant or in an optional circuit that is not used for the main body operation. The present invention can also be applied to a MOS transistor, a resistance element, and a capacitor element. For example, when the MOS transistor used for the main body operation is electrically connected and electrically connected due to pattern collapse due to dust, the same effects as those of the first embodiment can be obtained.

FIG. 1 is a plan view schematically showing the structure of a cell region and a peripheral circuit region of a NAND nonvolatile memory according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a schematic cross-sectional view showing a manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, continued from FIG. FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, continued from FIG. FIG. 6 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, continued from FIG. FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 12 is a schematic cross-sectional view showing a manufacturing process of the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 14 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 15 is a schematic cross-sectional view showing the manufacturing process of the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 16 is a schematic cross-sectional view showing a manufacturing process of a modified example of the manufacturing method of the NAND nonvolatile memory according to the first embodiment of the present invention. FIG. 17 is a schematic cross-sectional view showing the manufacturing process of the modified example of the method for manufacturing the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 18 is a schematic cross-sectional view showing the manufacturing process of the modified example of the method for manufacturing the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 19 is a plan view schematically showing the structure of a cell region and a peripheral circuit region in a modification of the NAND nonvolatile memory according to the first embodiment of the present invention. 20 is a cross-sectional view taken along line AA in FIG. FIG. 21 is a schematic cross-sectional view showing a manufacturing process of a variation of the NAND nonvolatile memory according to the first embodiment of the present invention. FIG. 22 is a schematic cross-sectional view showing the manufacturing process of the modification of the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 23 is a schematic cross-sectional view showing the manufacturing process of the modification of the NAND nonvolatile memory according to the first embodiment of the present invention, following FIG. FIG. 24 is a schematic cross-sectional view of a NAND flash memory according to the second embodiment of the present invention. FIG. 25 is a schematic cross-sectional view showing the manufacturing process of the NAND nonvolatile memory according to the second embodiment of the present invention. FIG. 26 is a schematic cross-sectional view showing the manufacturing process of the NAND nonvolatile memory according to the second embodiment of the present invention, following FIG. FIG. 27 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the second embodiment of the present invention, following FIG. FIG. 28 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the second embodiment of the present invention, following FIG. FIG. 29 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the second embodiment of the present invention, following FIG. FIG. 30 is a schematic cross-sectional view of a NAND flash memory according to the third embodiment of the present invention. FIG. 31 is a schematic cross-sectional view showing a manufacturing process of a NAND nonvolatile memory according to the third embodiment of the present invention. FIG. 32 is a schematic cross-sectional view showing the manufacturing process of the NAND-type nonvolatile memory according to the third embodiment of the present invention, following FIG. FIG. 33 is a schematic cross-sectional view showing the manufacturing process of the NAND nonvolatile memory according to the third embodiment of the present invention, following FIG. FIG. 34 is a schematic cross-sectional view showing the manufacturing process of the NAND nonvolatile memory according to the third embodiment of the present invention, following FIG. FIG. 35 is a plan view schematically showing structures of a cell region and a peripheral circuit region of a NOR type nonvolatile memory according to the sixth embodiment of the present invention. 36 is a cross-sectional view taken along line AA of FIG. FIG. 37 is a plan view schematically showing the structure of the cell region and the peripheral circuit region of the NAND nonvolatile memory according to the fifth embodiment of the present invention. FIG. 38 is a plan view schematically showing the structure of the cell region and the peripheral circuit region of the NAND nonvolatile memory according to the sixth embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Memory cell area | region, 11a ... Memory cell transistor area | region, 11b ... Selection gate transistor area | region, 12 ... Peripheral circuit area | region, 13, 63, 73 ... Active area, 14, 64, 74 ... Element isolation insulating film, 17, 77 ... Contact electrode 18, 78 ... Gate contact electrode, 20 ... Impurity diffusion layer, 21 ... Semiconductor substrate, 22, 22a, 22b, 22c, 22d ... Gate insulating layer, 23 ... First gate electrode layer, 23a ... Floating gate electrode layer , 23b, 23c ... lower gate electrode layer, 23d ... silicon oxide film, 24 ... interelectrode insulating layer, 24a ... first interelectrode insulating layer, 24b, 24c ... second interelectrode insulating layer, 25 ... second gate electrode layer Lower part, 25a ... Lower control gate electrode layer, 25b, 25c ... Lower upper gate electrode layer, 26 ... Second gate electrode layer upper part, 26a ... Control gate Upper layer, 26b, 26c ... Upper gate electrode layer, 27 ... Second gate electrode layer, 27a ... Control gate electrode layer, 27b, 27c ... Upper gate electrode layer, 28b, 28c ... Opening, 29, 29a, 29b 29c ... metal layer, 30a, 33 ... first mask material, 30b ... third mask material, 30c ... fourth mask material, 30d ... fifth mask material, 31 ... opening, 32 ... second gate insulating layer, 41 ... First gate insulating layer, 42 ... second gate insulating layer, 42b, 42c ... second gate insulating layer, 49 ... mask material, 53 ... impurity diffusion layer, 68a ... first gate contact electrode, 68b ... second gate contact electrode , 76 ... opening

Claims (7)

Processing the upper surface of the semiconductor substrate to form a first upper surface region and a second upper surface region having an upper surface located on a plane below the first upper surface region;
Forming a gate insulating layer on the first upper surface region and the second upper surface region so that the thicknesses of the insulating layers in the first and second upper surface regions are the same;
A gate electrode layer is formed on the gate insulating layer such that the film thicknesses of the electrode layers in the first and second upper surface regions are the same, and the upper surface of the first gate electrode layer in the first upper surface region is Locating on a plane above the upper surface of the first gate electrode layer in the second upper surface region;
Positioning the upper surface of the first gate electrode layer in the first upper surface region and the upper surface of the first gate electrode layer in the second upper surface region on the same plane;
Forming an interelectrode insulating layer on the first gate electrode layer;
Forming an opening exposing a part of the surface of the first gate electrode layer in the interelectrode insulating layer in the second upper surface region;
Removing a natural oxide film formed on the exposed surface of the first gate electrode layer;
Forming a second gate electrode layer on the exposed surface of the first gate electrode layer and the interelectrode insulating layer;
Selectively removing the second gate electrode layer, the interelectrode insulating layer, the first gate electrode layer and the gate insulating layer on the first and second upper surface regions to form a gate electrode;
A method of manufacturing a semiconductor memory device, comprising: Forming a gate insulating layer thicker on the first upper surface region of the semiconductor substrate than on the second upper surface region;
A first gate electrode layer is formed on the gate insulating layer so that the film thicknesses of the electrode layers in the first and second upper surface regions are the same, and an upper surface of the first gate electrode layer in the first upper surface region On a plane above the upper surface of the first gate electrode layer in the second upper surface region,
And positioning the upper surface of the first gate electrode layer in the first upper surface region and the upper surface of the first gate electrode layer in the second upper surface region on the same plane;
Forming an interelectrode insulating layer on the first gate electrode layer;
Forming an opening exposing a part of the surface of the first gate electrode layer in the interelectrode insulating layer in the second upper surface region;
Removing a natural oxide film formed on the exposed surface of the first gate electrode layer;
Forming a second gate electrode layer on the exposed surface of the first gate electrode layer and the interelectrode insulating layer;
Forming a gate electrode by selectively removing the second gate electrode layer, the interelectrode insulating layer, the first gate electrode layer, and the first gate insulating layer on the first and second upper surface regions; When,
A method of manufacturing a semiconductor memory device, comprising:   In the step of positioning the upper surface of the first gate electrode layer in the first upper surface region and the second upper surface region on the same plane, an upper portion of the first gate electrode layer on the first upper surface region is formed using CMP. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor memory device is removed. The step of positioning the upper surface of the first gate electrode layer in the first upper surface region and the second upper surface region on the same plane,
Replacing an upper portion of the first gate electrode layer in the first upper surface region with an oxide film corresponding to a difference in height of the first gate electrode layer in the first and second upper surface regions;
Removing the oxide film;
The method of manufacturing a semiconductor memory device according to claim 1, wherein: A semiconductor substrate comprising a first upper surface region and a second upper surface region whose upper surface is located on a plane below the first upper surface region;
A gate insulating layer provided on the first and second upper surface regions;
A floating gate electrode layer provided on the first upper surface region via the gate insulating layer;
A first inter-electrode insulating layer provided on the floating gate electrode layer;
A control gate electrode layer provided on the first inter-electrode insulating layer;
A lower gate electrode layer provided in the second upper surface region via the gate insulating layer and having an upper surface located on the same plane as the upper surface of the floating gate electrode layer;
A second inter-electrode insulating layer provided on the lower gate electrode layer and having an opening for exposing a partial upper surface of the lower gate electrode layer;
An upper gate electrode layer provided on the exposed surface of the lower gate electrode layer and the second inter-electrode insulating layer;
A semiconductor memory device, wherein the floating gate electrode layer is thinner than the lower gate electrode layer. A semiconductor substrate having a first upper surface region and a second upper surface region on the same plane;
A first gate insulating layer that is provided on the first upper surface region and is thicker than a second gate insulating layer provided on the second upper surface region;
A floating gate electrode layer provided on the first upper surface region via the gate insulating layer, a first inter-electrode insulating layer provided on the floating gate electrode layer, and the first inter-electrode insulating layer A provided control gate electrode layer;
A lower gate electrode layer provided on the second upper surface region via the gate insulating layer and having an upper surface located on the same plane as the upper surface of the floating gate electrode layer; provided on the lower gate electrode layer; and A second inter-electrode insulating layer having an opening for exposing a part of the upper surface of the lower gate electrode layer, and an upper gate provided on the exposed surface of the lower gate electrode layer and the second inter-electrode insulating layer An electrode layer,
A semiconductor memory device, wherein the floating gate electrode layer is thinner than the lower gate electrode layer.   The semiconductor memory according to claim 5, wherein the opening of the inter-electrode insulating layer has a shape exposing one side of the upper surface of the lower gate electrode layer. apparatus.

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