JPH07161851A - Semiconductor nonvolatile memory and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor nonvolatile memory, which can be manufactured in high integration in terms of the existing processing technology and at low cost, and its manufacturing method. CONSTITUTION:MONOS is used as a memory element. A first layer gate is thinned down by the resist ashing method. After an ONO film is formed, a transistor is made by a sidewall at a second layer which is a second polysilicon layer 4; then, the ONO film is formed to form a transistor between sidewalls in a third layer which is a third polysilicon layer 5. This enables the integration of a semiconductor nonvolatile memory to be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile memory, for example, a semiconductor nonvolatile memory device such as a flash EEPROM and a method for manufacturing the same.

[0002]

2. Description of the Related Art Nonvolatile memories are easy to use because their information is saved even when the power is turned off, and the market is expanding. The layout of such nonvolatile memory cells is roughly classified into NOR type and NAND type.

FIG. 6 shows the structure of a NOR type non-volatile memory cell.
It is a figure which shows an example. In FIG. 6, BL₁, BL₂Is
Bit line, WL₁, WL₂Is the word line, MT ₁₁, M
T₁₂, MT_{twenty one}, MT_{twenty two}Is it a memory cell transistor
Shows each. As shown in Figure 6, two adjacent tigers
Register MT₁₁And MT₁₂, MT_{twenty one}And MT_{twenty two}so,
Bit contact CNT_BLShare one. That is,
Bit contact C per transistor (1 bit)
NT_BL0.5 is required.

The NOR type non-volatile memory having such a structure is suitable for high-speed operation because it can be directly accessed without passing through other transistors, but it requires 0.5 contacts per bit, which increases the degree of integration. Is difficult.

On the other hand, in the NAND type nonvolatile memory, as shown in FIG. 7, a plurality of memory cell transistors MT _{1 to} MT are provided between the bit contact CNT _BL and the ground.
₈ are connected in series. In reality, the select transistor is inserted between the memory cell transistor and the bit contact CNT _BL and the ground, but the bit contact C
NT _BL is also shared with the adjacent series memory cell transistor group. Therefore, for an 8-bit serial cell, the total (8
+2) × 2 = 20 transistors is enough.

The NAND-type non-volatile memory having such a structure is suitable for high integration because it requires only one contact with respect to memory cells connected in series, but it is suitable for other transistors connected in series to the transistor to be accessed. Since the transistor is connected, it cannot be used for applications that require high-speed operation.

Therefore, when high speed is not required so much but a large capacity is required, for example, a NAND type non-volatile memory is promising for replacing a hard disk or for a fixed tape. When used for this type of application, low cost is extremely important as it is commonly used. Since the NAND type nonvolatile memory has a larger number of bits per unit area than the NOR type nonvolatile memory, it is advantageous in terms of cost, and in that sense, it is suitable for this type of application.

[0008]

However, in order to further improve the degree of integration with the normal NAND structure,
It is necessary to advance miniaturization, but it is limited only by using the current processing technology. Further, it is difficult in terms of time, technology and cost to develop a new fine processing technology for that purpose.

The present invention has been made in view of the above circumstances, and an object thereof is a semiconductor nonvolatile memory device capable of achieving high integration and cost reduction within the range of the current processing technology. It is to provide a manufacturing method.

[0010]

In order to achieve the above object, a semiconductor nonvolatile memory device for accumulating charges in a gate insulating film according to the present invention has at least two first memory elements formed at a predetermined interval. A second memory element having a gate formed of a sidewall formed on at least one side surface side of the gate portion of the first memory element via an interlayer film, and between two second memory elements spaced apart from each other by a predetermined distance. And a third memory element formed in.

In the semiconductor nonvolatile memory device of the present invention, at least one of the gate insulating film and the interlayer film for separating the elements is composed of an insulating film containing at least a nitride insulating film.

Further, in the semiconductor nonvolatile memory device of the present invention, the memory elements are arranged in a NAND type or a contactless NOR type.

Further, in the method of manufacturing a semiconductor nonvolatile memory device according to the present invention for accumulating charges in a gate insulating film, after forming an insulating film on a semiconductor substrate, a first polysilicon is deposited on the insulating film and then deposited. The formed first polysilicon layer is processed by resist ashing to form a predetermined space and at least 2
Forming a first memory element, forming an insulating film on the substrate and the surface of the first memory element, and then forming a second polysilicon layer on at least one side of the first memory element, and forming at least a second polysilicon layer. After forming an insulating film on the surface of the layer, a third polysilicon layer is formed between at least two second polysilicon layers with a predetermined spacing.

Further, in the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the third polysilicon layer is formed on the substrate, and the first polysilicon layer is formed on the substrate.
Then, a mask material is embedded in a groove formed on the second polysilicon layer after the formation of the third polysilicon layer in a self-aligned manner, and the third polysilicon layer is processed using this as a mask.

[0015]

According to the semiconductor non-volatile memory device of the present invention, the degree of integration of the semiconductor non-volatile memory device is improved four times within the range of the current processing technology.

According to the manufacturing method of the present invention, first,
After the insulating film is formed on the semiconductor substrate, the first insulating film is formed on the insulating film.
Polysilicon is deposited. The width of the deposited first polysilicon layer is processed by using a resist ashing method. As a result, at least two first memory elements are formed with a predetermined interval. Next, after an insulating film is formed on the surface of the substrate and the first memory element, a second polysilicon layer is formed on at least one side of the first memory element, and a second polysilicon layer is formed.
Storage element is configured. Next, after an insulating film is formed on at least the surface of the second polysilicon layer, a third polysilicon layer is formed between at least two second polysilicon layers that are spaced apart by a predetermined distance to form a third memory element. It

Also in accordance with the present invention, a third polysilicon layer is formed on the substrate and the first and second polysilicon layers. At this time, a groove is formed in the third polysilicon layer formed between the second polysilicon layers. A mask material is embedded in the groove formed after the formation of the third polysilicon layer in a self-aligned manner, and is processed so that the third polysilicon layer is located between the two second polysilicon layers using the mask material as a mask.

[0018]

1 is a sectional view showing an embodiment of a NAND type semiconductor nonvolatile memory device according to the present invention. In FIG. 1, Tr1 is a first transistor, Tr2 is a second transistor, Tr3 is a third transistor, 1 is a semiconductor substrate,
2 is a gate insulating film, 3 is a first polysilicon layer, 4 is a second
A polysilicon layer, 5 is a third polysilicon layer, and 6 and 7 are interlayer insulating films.

The first transistor Tr1 has a first gate
A so-called MONO composed of the polysilicon layer 3
It is an S-type transistor. That is, as shown in FIG. 2, the gate insulating film of the MOS transistor is SiO ₂ / S
The memory transistor is composed of an ONO insulating film composed of three layers of iN / SiO ₂ .

The second transistor Tr2 has a second gate
It is a MONOS type transistor composed of the polysilicon layer 4. Second polysilicon layer 4 forming the gate
Are formed as so-called sidewalls on both sides of the first polysilicon layer 3 with the interlayer insulating film 6 interposed therebetween.

The second transistor Tr3 has a third gate
It is a MONOS type transistor composed of the polysilicon layer 5. The third polysilicon layer 5 has an adjacent second
On the gate insulating film 2 between the transistors Tr2 of the
It is formed on the interlayer insulating film 7 formed on the polysilicon layer 3 and the second polysilicon 4.

As described above, in the present embodiment, the ONO film having the structure shown in FIG. 2 is used as the gate insulating film of the first to third transistors Tr1, Tr2, Tr3 to maintain the memory function. In addition to being used to do so, it also functions as an interlayer insulating film between each transistor. In this case, the lowermost oxide film of ONO (also referred to as Bottom Ox) is obtained by oxidizing polysilicon, but the oxide film on polysilicon has a property of becoming thicker than that on the substrate 1 made of single crystal silicon. Suitable for the purpose of interlayer insulation.

Next, a method of manufacturing the semiconductor nonvolatile memory device of FIG. 1 will be described with reference to FIG. In addition,
Descriptions of steps such as ion implantation that are not directly related to the shape are omitted.

First, as shown in FIG. 3A, after forming an ONO film to be the gate insulating film 2 on the substrate 1, CVD is performed.
Polysilicon Poly is deposited by the method to a film thickness of about 250 nm, and then phosphorus is doped. The thickness of the gate insulating film 2 is, for example, SiO ₂ of the lowermost layer of the ONO film.
2 nm, the intermediate SiN film thickness is 4 nm, and the uppermost SiO ₂ film thickness is 3 nm.

Next, as shown in FIG. 3B, a line / space (L / S) having a minimum design rule is patterned by a resist PR by a lithography method.
The pattern interval is set to about 0.4 μm, for example.

Next, as shown in FIG. 3C, the resist PR is isotropically etched in oxygen plasma by using a resist ashing method to reduce the resist line width to about 0.2 μm. At this time, the amount of thinning is determined by considering that the gate lengths of the first to third transistors Tr1, Tr2, Tr3 are finally the same. As a result, the distance between the adjacent resist patterns becomes about 0.6 μm. A specific condition of the resist ashing method is power 10
The setting is 0 W, the pressure is 200 mTorr, and the oxygen gas is 20 SCCM.

Then, as shown in FIG. 3D, RIE is performed.
After removing the polysilicon and the ONO film by, the resist is peeled off. Next, as shown in FIG. 3E, an ONO film is formed on the substrate 1 and the pattern. At this time,
The ONO film on the substrate 1 is the ONO film of the first transistor Tr1.
Although it is formed so as to have the same film thickness as the film, as described above, the ONO film on the side surface and the upper surface of the first transistor Tr1 is thicker than that on the substrate 1. This is because the bottom (Bottom) Ox becomes thicker on the polysilicon as described above.

Next, as shown in FIG. 4F, a second polysilicon layer 4 is formed by the CVD method, doped with phosphorus, and then etched back by RIE to form the second polysilicon layer 4.
To form the side wall. In this case, the ONO film in the region on the substrate 1 where the third transistor Tr3 will be formed later is removed in the region where the first polysilicon layer 3 and the second polysilicon layer 4 are not formed. Therefore, the ONO film on the upper surface of the first transistor Tr1 is almost removed.

Next, as shown in FIG. 4 (g), the substrate 1,
An ONO film is formed on the first polysilicon layer 3 and the second polysilicon layer 4. At this time, the ONO film on the substrate 1 is formed so as to have the same film thickness as the ONO films of the first transistor Tr1 and the second transistor Tr2, but as described above, it is formed on the upper surface of the first transistor Tr1. The ONO film on the upper surface of the second transistor Tr2 becomes thicker than that on the substrate 1.

Next, as shown in FIG.
The third polysilicon layer 3Pol is formed on the NO film by the CVD method.
After forming y (5), phosphorus is doped. Next, as shown in FIG. 4I, patterning is performed by lithography. At this time, the space may be the minimum distance according to the design rule, and it is not necessary to take a misalignment margin. This is because the misalignment margin can be substituted by the sidewall. Then, as shown in FIG.
Of the transistor Tr1 and the second transistor Tr2 located in the region near the first transistor Tr1 are removed, and the resist film is peeled off. Hereinafter, the process proceeds to the step of forming an interlayer insulating film.

Instead of the steps of FIGS. 4 (i) and 4 (j) described above, for example, a mask material such as SiO 2 is formed in the groove formed when the third polysilicon layer 5 is formed in FIG. 4 (h). ₂ , SOG or resist may be embedded in a self-aligned manner, and the third polysilicon layer 5 may be processed by using it as a mask.

Next, with reference to FIG. 5, it is considered how many memory transistors can be formed in one unit line / space. In FIG. 4, L represents the minimum design rule, and the line / space has a length of 4L / 4L for simplification. The ONO film thickness is ignored.

As shown in FIG. 5A, in the case of the normal first polysilicon, there is only one memory transistor per line / space unit. On the other hand, in this embodiment, as shown in FIG. 5B, four transistors having a gate length of 2L are formed in 4L + 4L = 8L. Specifically, the first transistor Tr1 is one, the second transistor Tr2 is two, and the third transistor Tr3 is one, for a total of four. As a result, according to the present embodiment, the integration degree can be increased to four times the normal level.

As described above, according to this embodiment,
MONOS is used as the element, the gate of the first layer is thinned by the resist ashing method, and the ONO film is formed.
A transistor is formed by a sidewall with the second polysilicon layer 2 of the second layer, an ONO film is further formed, and a transistor is formed between the sidewalls with the third polysilicon layer 5 of the third layer. Within the range, the degree of integration of the nonvolatile memory can be improved. As a result, the cost per bit can be reduced, which has the advantage of reducing the price of the product. Moreover, the misalignment margin can be absorbed by the sidewall, and the memory cell can be formed using the minimum processing dimension.

Although the NAND type semiconductor nonvolatile memory device has been described as an example in the present embodiment, the present invention is not limited to this, and the present invention is also applied to, for example, a contactless NOR semiconductor nonvolatile memory device. It goes without saying that you can do it.

[0036]

As described above, according to the present invention,
The degree of integration of the nonvolatile memory can be improved within the range of the current processing technology. As a result, the cost per bit can be reduced, which has the advantage of reducing the price of the product.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an embodiment of a NAND-type semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is an explanatory diagram of an ONO structure.

FIG. 3 is a diagram for explaining the manufacturing method of the semiconductor nonvolatile memory device in FIG.

FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor nonvolatile memory device in FIG. 1.

FIG. 5 is a diagram for comparing and explaining the degree of integration of the product of the present invention and the conventional product.

FIG. 6 is a diagram for explaining a NOR type memory cell.

FIG. 7 is a diagram illustrating a NAND memory cell.

[Explanation of symbols]

 Tr1 ... 1st transistor Tr2 ... 2nd transistor Tr3 ... 3rd transistor 1 ... Semiconductor substrate 2 ... Gate insulating film 3 ... 1st polysilicon layer 4 ... 2nd polysilicon layer 5 ... 3rd polysilicon layer 6, 7 ... Interlayer insulating film

Claims (6)

[Claims] 1. A semiconductor nonvolatile memory device for accumulating charges in a gate insulating film, comprising at least two first memory elements formed at predetermined intervals, and at least a gate portion of the first memory element. A second memory element having a sidewall as a gate, which is formed on one side surface side with an interlayer film interposed therebetween, and a third memory element formed between two second memory elements spaced apart by a predetermined distance. Semiconductor non-volatile memory device. 2. The semiconductor nonvolatile memory device according to claim 1, wherein at least one of the gate insulating film and the interlayer film for separating the elements is formed of an insulating film including at least a nitride insulating film. 3. The semiconductor nonvolatile memory device according to claim 1, wherein the memory elements are arranged in a NAND type. 4. The semiconductor nonvolatile memory device according to claim 1, wherein the memory elements are arranged in a contactless NOR type. 5. A method of manufacturing a semiconductor non-volatile memory device for accumulating charges in a gate insulating film, comprising: forming an insulating film on a semiconductor substrate; then depositing first polysilicon on the insulating film; The first polysilicon layer is processed by resist ashing to form at least two first memory elements with a predetermined spacing, and an insulating film is formed on the substrate and the surface of the first memory element. A second polysilicon layer is formed on at least one side of the memory element, an insulating film is formed on at least the surface of the second polysilicon layer, and then a third polysilicon layer is formed between at least two second polysilicon layers with a predetermined spacing. A method for manufacturing a semiconductor nonvolatile memory device, which comprises forming a layer. 6. A third polysilicon layer as a substrate, and a first polysilicon layer.
6. The third polysilicon layer is processed by forming a mask material in a self-aligned manner in a groove formed on the second polysilicon layer and after forming the third polysilicon layer, and using the mask material as a mask. Manufacturing method of semiconductor nonvolatile memory device.