JPH03191569A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory whose junction leak is small and whose data retention characteristic is excellent by a method wherein, when an insulating film is left on a sidewall of a gate electrode of a MOS transistor in a peripheral circuit part, the insulating film in a memory cell part is not etched. CONSTITUTION:A gate electrode 16 of a MOS transistor is formed on a memory cell part 14 and a peripheral circuit part 15; after that, the memory cell part 14 and the peripheral circuit part 15 are covered with an insulating film 18; the insulating film 18 on the peripheral circuit part 15 is etched selectively; and the insulating film 18 is left on sidewalls of the gate electrode 16 in the peripheral circuit part 15. Since the insulating film 18 on the memory cell part 14 is not etched in this case, a semiconductor substrate 11 in the memory cell part 14 is not damaged. Since ions of impurities 23 are not implanted, a crystal defect is hard to produce in the semiconductor substrate 11 in the memory cell part 14. Thereby, it is possible to obtain a semiconductor memory whose junction leak is small and whose data retention characteristic is excellent.

Description

[Detailed Description of the Invention] [Industrial Application Field] The invention of the present application has a memory cell section and a peripheral circuit section, and the memory cell section and the peripheral circuit section have MOS transistors. The present invention relates to a method for manufacturing a semiconductor memory.

[Summary of the invention]

The invention according to claim 1 is a method for manufacturing a semiconductor memory as described above, in which the insulating film in the memory cell part is not etched when leaving the insulating film on the side wall of the gate electrode of the MOS transistor in the peripheral circuit part. This makes it possible to manufacture a semiconductor memory with less junction leakage and excellent data retention characteristics.

The invention as claimed in claim 2 provides a semiconductor memory manufacturing method as described above, in which an insulating film to be left on the side wall of the gate electrode of the MOS transistor is formed at 21I in the memory cell portion, thereby reducing junction leakage and improving data retention characteristics. This makes it possible to manufacture an excellent semiconductor memory.

[Conventional technology]

As one measure against hot carriers associated with miniaturization of MOS transistors, an LDD structure has been adopted.

When forming a MOS transistor with an LDD structure, conventionally, after patterning the gate electrode, impurity ions are implanted at a low concentration, a 5i (h film) is deposited by CVD, and RIE is performed on the entire surface to form the sidewalls of the gate electrode. 5 iO
One film of spacers was formed.

[Problem to be solved by the invention]

However, anisotropic etching of a SiO film tends to damage the Si substrate. Particularly in semiconductor memories, the density of gate electrodes is higher in the memory cell part than in the peripheral circuit part, so the deposited Si film tends to become thinner in the memory cell part. For this reason, the Si substrate in the memory cell portion is overetched by RIE of the entire surface of the Si film, and the amount of damage to the Si substrate increases.

Therefore, crystal defects that cause junction leakage are particularly likely to be induced in the memory cell portion, making it impossible to manufacture a semiconductor memory with excellent data retention characteristics.

On the other hand, if the amount of overetching in the memory cell area is reduced, the Sin film will remain in the peripheral circuit area where the Si film is thickly deposited due to the low density of the gate electrode. As a result, a problem arises in that even if impurities are subsequently ion-implanted at a high concentration, the impurities are not implanted into the Si substrate in the peripheral circuit section.

[Means for solving problems]

The method for manufacturing a semiconductor memory according to claim 1 includes a memory cell portion 1.
4 and the peripheral circuit section 15; a step of covering the memory cell section 14 and the peripheral circuit section 15 with an insulating film 18 after forming the gate electrode 16; The insulating film 18 of the peripheral circuit section 15 is selectively etched to form the peripheral circuit section 15.
and a step of leaving the insulation [18] on the sidewalls of the gate electrodes 16, respectively.

A method for manufacturing a semiconductor memory according to a second aspect of the present invention provides a method for manufacturing a semiconductor memory in which a memory cell portion 1
4 and the peripheral circuit section 15, and a step of covering the memory cell section I4 and the peripheral circuit section 15 with a first insulating film 18 after forming the gate electrode I6. and the memory cell section 14
a step of covering the first insulating film I8 with a second insulating film 26, and etching the first and second insulating films 18, 26 to form at least the first insulating film on the sidewalls of the gate electrode 16. 18 remaining steps.

[Effect]

In the method for manufacturing a semiconductor memory according to claim 1, the peripheral circuit section 1
Since the insulating film 18 of the memory cell section 14 is not etched when leaving the insulating film 18 on the side wall of the gate electrode 16 of the MOS transistor No. 5, the semiconductor substrate 11 of the memory cell section 14 is not damaged at this time.

Furthermore, since the insulating film 18 remains in the memory cell section 14, the insulating film 18 left on the side wall of the gate electrode 16 in the peripheral circuit section 15
Even when the impurity 23 is ion-implanted into the semiconductor substrate 11 at a high concentration using the mask 8 and the like, the impurity 23 is not ion-implanted into the memory cell portion 14. Therefore, even if this ion implantation is performed, crystal defects are unlikely to occur in the semiconductor substrate 11 of the memory cell portion 14.

In the semiconductor memory manufacturing method according to the second aspect, in the memory cell portion 14, the first insulating film 18 is further replaced with a second insulating film 2G.
Since it is covered with It is possible to achieve the same effect as in the semiconductor memory manufacturing method of item 1.

Further, when leaving at least the first insulating film 18 on the sidewalls of the gate electrode 16, over-etching of the semiconductor substrate 11 of the memory cell section 14 is prevented, thereby reducing damage to the semiconductor substrate 11 of the memory cell section 14. You can also do it.

〔Example〕

Hereinafter, the first to fourth embodiments of the invention of the present application will be explained in Figs. 1 to 6.
This will be explained with reference to the figures.

FIG. 1 shows a first embodiment applied to the manufacture of MOS-DRAM. In this first embodiment, as shown in FIG. 1A, the St substrate 11 has five
After forming the iOt film 12, a gate insulating film of Sin
G membrane 13 membrane type 3.

After patterning a gate electrode 16 having a polycide structure in the memory cell section 14 and the peripheral circuit section 15, an N-type impurity 17 is injected into the Si substrate 11 at a low concentration using the gate electrode 16 and the Sing film 12 as a mask. ion implantation.

Next, as shown in Figure 1B, 5iOz
A film 18 is deposited. At this time, as described above, the Sing film 18 of the memory cell section 14 is thinner than the Sing film 18 of the peripheral circuit section 15.

Note that, rather than the SiO□ film 18, the PSG film or 5iOt/P
A three-layer film of SG/SiO□ is preferable in terms of low stress. The Sin and upper films above and below the three-layer film are Phos diffusion prevention films. Thereafter, the memory cell portion 14 is covered with a resist 21.

Next, using the resist 21 as a mask, sto, WAl 8
As shown in FIG. 1C, as shown in FIG. 1C, in the peripheral circuit section 15, s;o, JIl! I leave 8. Note that the S+0□ film 18 left in the memory cell portion 14 is made into an interlayer insulating film. After that, the resist 21 is removed.

Then, by CVD method or thermal oxidation, a thin Sin! Membrane 22 total 22
do. Then, in this state, A, which is the N-type impurity 23,
Sl ions are implanted at a high concentration into the Si substrate 11 in the N channel region.

Then, in the peripheral circuit section 15, the impurity 23 is ion-implanted into the Si-based fill using the gate electrode 16 and the SiO□ film 18 as its sidewall spacer as a mask. However, in the memory cell section 14, since the 5t02 film 8 is present on the entire surface as an insulating film between the eyebrows, the impurity 23 is not ion-implanted into the Si substrate 11.

Next, as shown in FIG. 1D, the sin of the memory cell section 14 is
, a contact hole 24 is opened in the membrane 18, and a storage node 25 is formed.
, dielectric film (not shown), plate electrode 8i (not shown)
,bottle! -1 (not shown) are sequentially formed to form MOS-1 (not shown).
Complete DRAM.

In the first embodiment as described above, although the N'' region is not formed in the memory cell portion 14, it does not have a large effect on the performance of the transfer MOS transistor.

FIG. 2 shows a second embodiment applied to the manufacture of MOS-DRAM. In this second embodiment as well, as shown in FIG. 2A, the steps up to the deposition of the SiO film 18 are carried out in the same manner as in the above-described first embodiment.

Next, as shown in FIG. 2B, a SiN film 26 with a thickness of several hundred layers is deposited on the Sing film 18 by low pressure CVD or plasma CVD.

Then, the memory cell section 14 is covered with a resist 21, and using this resist 21 as a mask, the peripheral circuit section 15 is
Etch 1%26. As the etching gas at this time, it is preferable to use SF gas, which can provide a certain degree of selectivity between the Sing film 18 and the SiN film 26.

Next, as shown in FIG. 2C, the resist 21 is removed and the S
By performing RIE on the entire surface of the iN film 26 and the 5tyx film 18, the Sin film 18 is left as a sidewall spacer for the gate electrode 16 in the peripheral circuit section 15, and the Sin film 18 is left as a sidewall spacer for the gate electrode 16 in the memory cell section 14. First, a 5in2 film 18 is left on the entire surface of the memory cell section 14.

Note that the thickness of the SiN film 26 and the SiN film 26 and Sin.

By appropriately selecting the RIE conditions for the film 18, the memory cell section 14 and the peripheral circuit section 15 can be
At the same time, the etching of the film 18 is completed, and the memory cell portion 1 is etched.
4 and the peripheral circuit section 15 can also be prevented from being overetched too much.

Thereafter, the steps from FIG. 1c onward in the first embodiment described above are performed.

In the second embodiment as described above, if the 5i02 film 18 is left on the entire surface of the memory cell section 14, the same effect as in the first embodiment can be achieved, and the over-etching of the Si substrate 11 can also be prevented. At least damage to the Si substrate 11 can be reduced.

Incidentally, contact between a polycide wiring such as the gate electrode 16 shown in FIGS. 1 and 2 and an Al wiring has conventionally been made as shown in FIG. 3.

That is, as shown in FIG. 3A, a polycrystalline Si film 2 is patterned and doped with impurities on an interlayer insulating film 27, etc.
On the polycide wiring 32 consisting of the 8 and -Six films 31 and the like, there is a sin insulating film between the eyebrows.

A film 33 and a SiN film 34 which is an impurity diffusion prevention film are deposited, and then an As5G film or a BPSGII! film is deposited. A low melting point glass film 35 such as the following is deposited.

Next, as shown in FIG. 3B, a contact hole 36 reaching the polycide wiring 32 is opened, and after the low melting point glass film 35 is allowed to flow, the Al wiring (37 in FIG. 4) is patterned.

However, in reality, the -Six film 31 was formed by low-temperature CVD.
When the low melting point glass film 35 flows, it is peeled off from the polycrystalline Si film 28 at the contact hole 36 portion, as shown in FIG. Therefore, a defect occurs in that the AP wiring 37 and the polycide wiring 32 are not in good contact with each other.

FIG. 5 shows a third embodiment in which contact is made between an Al wiring and a polycide wiring. In this third embodiment, a polycrystalline Si film 28, an ix film 31, and a conductive polycrystalline film 38 are used.
A polycide wiring 32 is formed with a three-layer film.

As the material of the polycrystalline film 38, polycrystalline St formed by CVD method, polycrystalline Si formed by sputtering method,
TiN, WN, Ti5iz, WSiz, MO
A high melting point metal such as S i z or a silicide thereof can be used.

Thereafter, as shown in FIG. 5B, the process up to the opening of the contact hole 36 is performed in substantially the same manner as in FIGS. 3 and 4. In this third embodiment, the SiN film 34 is not used, but the S
An iN film 34 may also be used.

Next, heat treatment is performed at about 900° C. in a 0□ atmosphere to cause the low melting point glass film 35 to flow, and then the AZ wiring (37 in FIG. 4) is patterned.

In the third embodiment as described above, since the polycrystalline M38 is present on the WSix film 31 during the heat treatment for causing the low melting point glass film 35 to flow, the WSix film 31 is made of polycrystalline S.
Peeling off from the i-film 28 is prevented.

Therefore, the contact between the F1 wiring and the polycide wiring 32 is good.

Moreover, the flow of the low melting point glass film 35 is 0! Since the process is carried out in an atmosphere, the surface of the area to be contacted with the Al wiring is oxidized, and Phos from the low melting point glass film 35 is oxidized.
Autodoping such as the following is prevented.

Therefore, even if the region to be contacted with the A1 wiring is a P' diffusion layer, the impurity concentration of this P' diffusion layer does not decrease. Therefore, poor contact between the Al wiring and the P diffusion layer is also prevented.

FIG. 6 shows a fourth embodiment in which contact is made between the Al wiring and the P diffusion layer in the semiconductor substrate.

In this fourth embodiment, as shown in FIG. 6A, a Si substrate 1
After forming a Si film 12 and the like for element isolation on the substrate 1, poron ions are implanted to form a P diffusion layer 41.

AI in areas other than P1 diffusion 1i41! Since several layers of wiring are formed below the wiring 37, as shown in FIG. 6B,
These interlayer insulating films 42 are also formed on the P' diffusion layer 41.

After that, a thin polycrystalline Si film 43 is deposited on the glabellar insulating film 42, and the polycrystalline Si film 43 is patterned so as to leave the contact hole 36 for the Al wiring 37 where it is to be formed.

However, it is not necessary to leave the polycrystalline Si film 43 in all the contact holes 36 for the Al wiring 37, and the P° diffusion layer 4I
You can also use only the top. Note that patterning of the polycrystalline Si film 43 does not reduce the degree of integration.

After that, a SiO□ film 44 is formed, and then a BPSG film 4 is formed.
5. Deposit to a total thickness of 4500 Å or more. In addition, SiO
□SiN film may be used for film formation 4.

Then, using a resist (not shown) as a mask, BPSG
The entire film 45 and the 45n2 film 44 are etched into a pattern of contact holes 36. This etching can be stopped at the polycrystalline Si film 43, as shown in FIG. 6B.

Thereafter, the polycrystalline Si film 43 is etched using the above resist as a mask, the resist is peeled off, and then B
The entire PSG film 45 is made 45-.

Therefore, if the material has an etching selectivity with 5i(b) of a predetermined value or more and can withstand high-temperature heat treatment of approximately 900°C, which is the total 45-temperature of the BPSG film 45, a film formed using this material can be used as a polycrystalline Si film. It can be used instead of 43.

Incidentally, before carrying out the flow of ['5Gll 45], the glabellar insulating film 42 may be etched to make the interlayer insulating film 42 as thin as possible.

Next, the entire surface is etched to form a contact hole 36 as shown in FIG. 6C, and an AI wiring 37 is further patterned.

In the fourth embodiment as described above, the entire BPSG film 45 is insulated between the eyebrows on the P diffusion layer 41. ! 42, Phos in the BPSG film 45 becomes P' diffusion layer 4.
No autodoping during 1.

Further, since the glabellar insulating film 42 is also present on the polycide wiring patterned in a region not shown, the silicide film does not peel off within the contact hole 36 for the polycide wiring.

〔Effect of the invention〕

In the method for manufacturing a semiconductor memory according to the first aspect, since the semiconductor substrate in the memory cell portion is not damaged and crystal defects are less likely to occur, it is possible to manufacture a semiconductor memory with less junction leakage and excellent data retention characteristics.

In the method for manufacturing a semiconductor memory according to claim 2, the semiconductor substrate in the memory cell portion is not damaged or can reduce damage, and crystal defects are less likely to occur, so that junction leakage is reduced (data retention characteristics are improved). Excellent semiconductor memory can be manufactured.

[Brief explanation of drawings]

1 and 2 are side sectional views sequentially showing first and second embodiments of the invention of the present application, FIG. 3 is a side sectional view sequentially showing a desirable contact forming process, and FIG. 4 is a conventional FIGS. 5 and 6 are side sectional views of contacts actually formed by this method, respectively, showing third and fourth embodiments of the present invention in sequence. Note that the reference numerals used in the drawings indicate the memory cell portion peripheral circuit portion gate electrode SiO□ film 6 tN film. Agent Masaru Tsuchiya Figure 3A Figure 3B Contact Figure 4 Contact formation process Figure 5A Figure 5B

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor memory having a memory cell portion and a peripheral circuit portion, the memory cell portion and the peripheral circuit portion each having a MOS transistor, comprising: forming a gate electrode of the MOS transistor in the peripheral circuit section and the peripheral circuit section; a step of covering the memory cell section and the peripheral circuit section with an insulating film after forming the gate electrode; and selectively etching the insulating film to leave the insulating film on a sidewall of the gate electrode in the peripheral circuit section. 2. A method for manufacturing a semiconductor memory having a memory cell section and a peripheral circuit section, the memory cell section and the peripheral circuit section each having a MOS transistor, wherein the memory cell section and the peripheral circuit section a step of forming a gate electrode of the MOS transistor in the MOS transistor; a step of covering the memory cell portion and the peripheral circuit portion with a first insulating film after forming the gate electrode; A semiconductor memory comprising the steps of: covering an insulating film with a second insulating film; and etching the first and second insulating films to leave at least the first insulating film on the sidewalls of the gate electrode. manufacturing method.