KR20020042309A - Method for manufacturing semiconductor semiconductor memory device - Google Patents

Abstract

PURPOSE: A fabrication method of a semiconductor memory device is provided to simplify manufacturing processes by selectively forming a transition metal silicide layer using a hard density plasma insulating layer. CONSTITUTION: Silicide prevention layers made of a buffer insulating layer(64) and a silicon nitride(66) is deposited on a substrate(50) defined with DRAM cell region(B1) and a logic cell region(B2) respectively having gate electrodes(g), source regions(60a,62a), and drain regions(60b,62b). The first transition metal silicide layers(70a,70b) are selectively formed on the gate electrodes(g), source and drain regions(60a,60b,62a,62b) in the logic cell region(B2). An etch stopper(72) is deposited on the resultant structure and a hard density plasma insulating layer(74) is then formed to fill the gap between the gate electrodes(g). The hard density plasma insulating layer(74), the etch stopper(72) and the silicide prevention layers(64,66) are etched to expose the gate electrodes(g) in the DRAM cell region(B1). Then, the second transition metal silicide layer(78) is formed on the gate electrodes(g) in the exposed DRAM cell region(B1).

Description

Method for manufacturing semiconductor semiconductor device

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing an embedded DRAM device including a logic circuit portion.

In general, an embedded DRAM is an integrated circuit having a DRAM cell and a logic cell formed on a single silicon chip. These embedded DRAMs can transfer large amounts of data at very high speeds. Due to such high memory capacity and speed, embedded DRAMs are used as internal components of high volume processing circuits such as graphic processors. Complete embedded DRAMs include logic circuits, transfer MOS transistors, and capacitors coupled with transfer MOS transistors. Here, the transfer MOS transistor actually serves as a switch between the lower electrode and the bit line of the capacitor. Thus, the data in the capacitor can be read and written.

1 is a cross-sectional view of a general embedded DRAM device.

Referring to FIG. 1, in order to define an active region in a predetermined portion of the semiconductor substrate 10, the device isolation region 11 is formed by a known method. The DRAM cell region A1 and the logic cell region A2 are defined in the active region of the semiconductor substrate 10. The gate insulating layer 12 and the doped polysilicon layer 13 are deposited on the semiconductor substrate 10. Next, the doped polysilicon film 13 is partially patterned to form the gate electrode G. As shown in FIG. The insulating spacers 15 are formed on both sidewalls of the gate electrode G in a known manner. Subsequently, impurities are implanted into the semiconductor substrate 10 on both sides of the gate electrode G to form source regions 18a and 20a and drain regions 18b and 20b.

Thereafter, a silicide blocking layer (not shown) is deposited on the resultant surface of the semiconductor substrate 10. Thereafter, the silicide blocking layer is opened so that only the tops of the source and drain regions 20a and 20b corresponding to the gate electrode G and the logic cell region A2 of the region where the silicide layer is to be formed are opened. Subsequently, the transition metal silicide film 22 is formed only on the exposed portions by a selective deposition method. At this time, the silicide film 22 is not formed in the source and drain regions 18a and 18b corresponding to the DRAM cell region A1 for the following reason. The transition metal silicide layer 22 serves to lower contact resistance due to excellent conduction characteristics. However, in the present case, when a shallow junction is formed in accordance with the high integration density, a leakage current is likely to be generated by the silicide film on the shallow junction region (source, drain region). In particular, since the leakage current is directly connected to the refresh characteristics of the capacitor, no silicide film is used in the junction region of the current DRAM element.

Then, an interlayer insulating film 24 is formed on the semiconductor substrate 10 on which the gate electrode G and the source and drain regions 18a, 18b, 20a, and 20b are formed. Thereafter, the interlayer insulating film 24 and the silicide blocking layer (not shown) are etched to form a storage node contact hole H so that a predetermined portion of the source region 18a of the DRAM cell region A1 is exposed.

The lower electrode 26 is formed on the interlayer insulating layer 24 to contact the source region 18a exposed by the storage node contact hole H. After forming the dielectric film 28 on the lower electrode 26 surface, the upper electrode 30 is formed on the dielectric 28 to form a capacitor.

However, the conventional embedded DRAM manufacturing method has the following problems.

In general, as the logic circuit reduces design rules of semiconductor devices, line widths of the source and drain regions are also reduced. As a result, in the process of forming a contact hole exposing the source and drain regions, it is difficult to secure the distance between the contact hole and the edge portion of the active region (hereinafter referred to as a contact overlay margin), and in some cases, the device isolation region is etched. Currently, in order to prevent etching of unwanted regions due to lack of contact overlay margin, an insulating film having a large etching selectivity and a silicon oxide film constituting the interlayer insulating film are interposed in the interlayer insulating film of the logic circuit. The film interposed in such an interlayer insulating film is called an etch stopper, and a silicon nitride film or a silicon nitride film can be used as the etch stopper.

On the other hand, since embedded DRAM includes not only logic circuits but also DRAM circuits, etch stoppers are applied not only to logic circuits but also to DRAM circuits. However, when the etch stopper is interposed in the DRAM cell region A1 as described above, an etching process for forming a contact hole is required in multiple steps. That is, the general contact hole etching of the DRAM cell region A1 is performed by etching the interlayer insulating layer formed of a silicon oxide layer and two-step etching etching the silicide blocking layer remaining on the substrate surface. However, when the etch stopper is interposed in the interlayer insulating film, a contact hole in the DRAM cell region is formed. Since the interlayer insulating film etching process, the etch stopper etching process, the interlayer insulating film etching process and the silicide blocking layer etching process of silicon oxide film are required. The process step is increased. This complicates the process and requires at least two etching gases (or etching solutions).

In addition, since the silicide film must be selectively formed only on the gate electrode G as described above, the process is very cumbersome.

More specifically, in order to form the silicide layer only on the gate electrode G of the DRAM cell region A1, only the source and drain regions 18a and 18b of the DRAM region are shielded, and then only the gate electrode G is covered. After the silicide film is formed, or after the silicide film is formed in the source and drain regions 18a and 18b, only the silicide layer on the source and drain regions 18a and 18b is selectively removed. However, both of these processes are not only very complicated in process but also very difficult to proceed with current semiconductor manufacturing processes.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of forming contact holes in a DRAM cell region in a simple step in manufacturing an embedded DRAM.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of forming a silicide film on a source and a drain region of a gate electrode region and a logic cell region of each region by a simple process in manufacturing an embedded DRAM. It is.

1 is a cross-sectional view of a general embedded DRAM device.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

50-semiconductor substrate 60a, 60b, 62a, 62b-source, drain region

64-Buffer Insulation 66-Silicon Nitride

68,76-photoresist pattern 70a, 70b-first transition metal silicide film

72-etch stopper 74-high density plasma insulation film

78-second transition metal silicide film 80-interlayer insulating film

82-lower electrode 84-dielectric film

86-upper electrode B1-DRAM cell area

B2-logic cell region g-gate electrode

H-Storage Node Contact Hole C-Storage Node Capacitor

In order to achieve the above object of the present invention, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention has the following configuration.

First, a silicide blocking layer is deposited on a surface of a semiconductor substrate, in which a DRAM cell region and a logic cell region are defined and a gate electrode and a source drain region are formed in the DRAM cell region and the logic cell region, respectively. Subsequently, a first transition metal silicide layer is selectively formed on the gate electrode, the source, and the drain region of the logic cell region. Thereafter, an etch stopper is deposited on the semiconductor substrate including the silicide blocking layer, and a high density plasma insulating film is formed on the etch stopper to fill the space between the gate electrodes. Next, the high density plasma insulating film, the etch stopper and the silicide blocking layer are etched back so as to shield the source and drain regions while exposing the gate electrode of the DRAM cell region. Thereafter, a second transition metal silicide layer is formed over the gate electrode of the exposed DRAM cell region.

In addition, according to another embodiment of the present invention, it has the following configuration.

A DRAM cell region and a logic cell region are defined, and a silicide blocking layer is deposited on a semiconductor substrate resultant surface having a gate electrode and a source drain region formed on both sides of the DRAM cell region and the logic cell region, respectively. Subsequently, a first transition metal silicide layer is selectively formed on the gate electrode, the source, and the drain region of the logic cell region. Thereafter, an etch stopper is deposited on the semiconductor substrate including the silicide blocking layer, and a high density plasma insulating film is formed on the etch stopper to fill the space between the gate electrodes. Next, the high density plasma insulating film, the etch stopper and the silicide blocking layer are etched back so as to shield the source and drain regions while exposing the gate electrode of the DRAM cell region. Thereafter, a second transition metal silicide film is formed over the gate electrode of the exposed DRAM cell region, and then an interlayer insulating film is formed over the semiconductor substrate resultant. Next, the interlayer insulating film, the high density plasma insulating film, the etch stopper, and the silicide blocking layer are etched to expose the source region of the DRAM cell region to form a storage node contact hole.

The forming of the silicide blocking layer may include depositing a buffer insulating film on the semiconductor substrate and forming a silicon nitride film on the buffer insulating film.

The etch stopper may have a different etch selectivity from the interlayer insulating layer and a material having an etch selectivity similar to that of a part of the silicide blocking layer, for example, a silicon nitride film or a silicon nitride oxide film. In addition, the second transition metal silicide film is preferably formed to have a different thickness from the first transition metal silicide film.

The forming of the first transition metal silicide layer selectively on the gate electrode, the source and the drain region of the logic cell region may include forming a photoresist pattern to expose the silicide blocking layer of the logic cell region, and exposing the first transition metal silicide layer. Removing the silicide blocking layer; Removing the photoresist pattern, depositing a transition metal film on the semiconductor substrate of the logic cell region, and reacting the transition metal film to form a first transition metal silicide on the gate electrode and the source drain region of the logic cell region. Forming a film, and removing the unreacted transition metal film.

The etching of the high density plasma insulating film, the etch stopper and the silicide blocking layer to shield the source and drain regions while exposing the upper gate electrode of the DRAM cell region may include exposing the DRAM cell region on the high density plasma insulating film. Forming a photoresist pattern and etching the high density plasma insulating film, the etch stopper, and the silicide blocking layer of the exposed DRAM cell region so as to be buried in a space between the gate electrodes while exposing the upper portion of the gate electrode.

In addition, after forming the storage node contact hole, forming a lower electrode on the interlayer insulating layer to contact the source region of the exposed DRAM cell region, coating a dielectric film on the lower electrode surface, and the The method may further include forming an upper electrode on the dielectric film.

According to the present invention, in manufacturing the embedded DRAM, the etch stopper is deposited to be in direct contact with the upper side of the silicide blocking layer. Accordingly, the storage node contact hole may be formed only by etching the silicon oxide based material during the storage node contact hole forming process and etching the silicon nitride based material, that is, the etch stopper and the silicide blocking layer. Is simplified.

In addition, by using the high density plasma insulating film, the transition metal silicide film may be selectively formed only on the gate electrode while covering the source and drain regions of the DRAM cell region. Accordingly, a complicated process such as a separate process of depositing and removing the silicide layer or a process of shielding only the source and drain regions of the DRAM cell region with the photolithography process is excluded. Therefore, the process is simplified.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to one embodiment of the present invention.

First, referring to FIG. 2A, a gate insulating layer 53 and a conductive layer for a gate electrode, for example, a doped polysilicon layer 55 are sequentially deposited on the semiconductor substrate 50. Here, the active region is defined by the device isolation region 51 of the semiconductor substrate 50, and the active region is also divided into the DRAM cell region B1 and the logic cell region B2. Thereafter, the doped polysilicon film 55 is partially patterned to form the gate electrode g. The spacer 57 is formed on both sidewalls of the gate electrode g in each of the regions B1 and B2 by using a known anisotropic etching method. Thereafter, impurities are implanted into the semiconductor substrate 50 on both sides of the gate electrode g to form source regions 60a and 62a and drain regions 60b and 62b. Here, reference numerals 60a and 60b denote sources and drain regions of the DRAM cell region B1, and 62a and 62b denote sources and drain regions of the logic cell region B2.

Next, a silicide blocking layer is formed on the semiconductor substrate 50 on which the gate electrode g and the source and drain regions 60a, 60b, 62a and 62b are formed. In this embodiment, a laminated film of the buffer insulating film 64 and the silicon nitride film 66 (SiN) is used as the silicide blocking layer. Here, the buffer insulating film 64 is interposed to enhance adhesion between the silicon nitride film 66 and the substrate 50 as a thin thermal oxide film. Thereafter, a photoresist film (not shown) is applied on the result of the semiconductor substrate 50, and then exposed and developed so as to remain only in the upper portion of the DRAM cell region B1 to form the first photoresist pattern 68. The silicide blocking layer, that is, the silicon nitride film 66 and the buffer insulating film 64 of the logic cell region B1 exposed by the first photoresist pattern 68 is removed in a known manner.

Thereafter, referring to FIG. 2B, the first photoresist pattern 68 is stripped, and then a transition metal film (not shown) is deposited on the semiconductor substrate 50. As the transition metal film, one film selected from refractory metal films such as Ti, Ta, W, Co, and Pt is used. Thereafter, the resultant semiconductor substrate is heat-treated to form first transition metal silicide layers 70a and 70b on the gate electrode g and the source and drain regions 62a and 62b of the exposed logic cell region B2. In this case, the first transition metal silicide layers 70a and 70b may be formed to have a thickness such that leakage current does not occur in the source and drain regions 62a and 62b of the logic cell region B1. Here, the transition metal film generally reacts with the silicon component in the heat treatment step to form a silicide film, but does not react with the insulating film. Accordingly, the transition metal film on the silicide blocking layer made of the silicon nitride film 66 and the buffer film 64 is not reacted even when the heat treatment step is performed. Next, the unreacted transition metal film is removed in a known manner. As described above, since the transition metal film does not react with the insulating layers, the transition metal silicide film is not formed in the DRAM cell region B1 covered by the silicon nitride film 66.

Subsequently, an etch stopper 72 is deposited on the resultant of the semiconductor substrate 50 on which the first transition metal silicide layers 70a and 70b are selectively formed. Here, the etch stopper 72 is a layer deposited to secure contact margins due to a decrease in design rules of semiconductor devices. A film having a difference in etching selectivity from silicon oxide formed of a general interlayer insulating film is used. In addition, the etch stopper 72 of the present embodiment may be a part of the silicide blocking layer, for example, a material having an etching selectivity similar to that of the silicon nitride film 66, for example, a silicon nitride film or a silicon nitride oxide film may be used.

Then, as shown in FIG. 2C, a hard density plasma insulating film 74 having a very high film quality and excellent interlayer embedding property is deposited on the etch stopper 72. At this time, the high density plasma insulating film 74 is a film formed by performing deposition and sputtering at the same time as is known. Accordingly, the high-density plasma insulating film 74 fills the space between the gate electrodes g, and is formed in the upper portion of the gate electrode g so that the upper region is narrower than the lower region, for example, in the form of a triangle or trapezoidal shape. .

Next, as shown in FIG. 2D, the photoresist film is coated on the high density plasma insulating film 74, and then, the second and second portions are disposed on the logic cell area B2 so that the DRAM cell area B1 is exposed by the exposure and development processes. The photoresist pattern 76 is formed. Then, the exposed high density plasma insulating film 74, the etch stopper 72, the silicon nitride film 66 and the buffer insulating film 64 of the DRAM cell region B1 are etched back to expose the upper region of the gate electrode g. do. At this time, the etch back process may be performed using, for example, HF gas. During the etch back process, the buffer insulating film 64, the silicon nitride film 66, the etch stopper 72, and the high density plasma insulating film 76 expose the source and drain of the DRAM cell region B1 while exposing the gate electrode g. Regions 60a and 60b must be etched back to shield.

Thereafter, as illustrated in FIG. 2E, a transition metal film (not shown) is deposited on the exposed DRAM cell region B1, and then the transition metal film is reacted by a heat treatment process. Then, the second transition metal silicide layer 78 is formed on the exposed gate electrode g of the DRAM cell region B1 by the reaction of the polysilicon layer and the transition metal layer. Subsequently, the unreacted transition metal film (not shown) is removed by a known method, and then the second photoresist pattern 76 is stripped by a known plasma etching method or the like. Accordingly, the second transition metal silicide layer 78 is selectively formed only on the gate electrode g of the DRAM cell region A1. In this case, the second transition metal silicide layer 78 may have a thickness different from those of the first transition metal silicide layers 70a and 70b. That is, since the second transition metal silicide film 78 is not formed at the same time as the silicide films formed on the source and drain regions 60a, 60b, 62a, and 62b, the second transition metal silicide film 78 is not affected by the leakage current, and thus is not limited in thickness. Do not. Accordingly, the thickness of the silicide layer 78 may be adjusted to obtain a desired sheet resistance Rs of the gate electrode.

Next, an interlayer insulating film 80 is formed over the high density plasma insulating film 74 and the silicide film 78. In this case, the interlayer insulating film 80 may be an insulating film composed of a single layer or multiple layers, or may be a multilayer insulating film including a planarization film. In addition, the interlayer insulating film 80 is preferably a silicon oxide film series. Next, the interlayer insulating film 80, the high density plasma insulating film 74, the etch stopper 72, the silicon nitride film 66, and the buffer insulating film 64 are predetermined so that the source region 60a of the DRAM cell region B1 is exposed. Partial etching is performed to form the storage node contact hole H. At this time, since the etch stopper 72 and the silicon nitride film 66 are sequentially stacked, the etch stopper 72 and the silicon nitride film 66 may be etched by one etching of the silicon nitride film. Accordingly, in the present exemplary embodiment, the storage node contact hole H may be formed by etching the interlayer insulating layer 80 and the high density insulating layer and etching the etch stopper 72 and the silicon nitride layer 66. Therefore, the etching process for forming the storage node contact hole H is simplified. At this time, the buffer insulating film 64 is easily removed when the silicon nitride film 66 is removed as a thin film oxide film.

Thereafter, the lower electrode 82 is formed to contact the source region 60a exposed on the interlayer insulating layer 80. In this case, the lower electrode 82 may have a cylinder shape as shown in the figure, or may be formed in a stack or fin type. The dielectric film 84 is coated on the lower electrode 82 surface. As the dielectric film 84, for example, an oxide-nitride-oxide (ONO) film, a ferroelectric film, a tantalum oxide film, or the like can be used. Thereafter, the upper electrode is covered over the dielectric film 84, so that the storage node capacitor C is completed.

Although not shown in the drawings, a process of forming a bit line may be performed before the storage node capacitor is formed.

In addition, although the storage node contact hole has been described as an example in the present embodiment, the present invention may be applied to the bit line contact hole without being limited thereto.

As described in detail above, according to the present invention, the following effects are exerted.

First, in the manufacture of embedded DRAMs, an etch stopper is deposited such that it directly contacts the top of the silicide blocking layer. Accordingly, the storage node contact hole may be formed only by etching the silicon oxide based material during the storage node contact hole forming process and etching the silicon nitride based material, that is, the etch stopper and the silicide blocking layer. Is simplified.

Second, the transition metal silicide layer may be selectively formed only on the gate electrode while covering the source and drain regions of the DRAM cell region by using the high density plasma insulating layer. Accordingly, a complicated process such as a separate process of depositing and removing the silicide layer or a process of shielding only the source and drain regions of the DRAM cell region with the photolithography process is excluded. Therefore, the process is simplified.

Third, since the transition metal silicide layer on the gate electrode of the DRAM cell region is formed independently, the thickness can be increased without regard to leakage current. Therefore, the sheet resistance of the gate electrode is improved, so that the signal delay characteristic of the DRAM cell is improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (14)

Providing a semiconductor substrate having a DRAM cell region and a logic cell region defined therein, each having a gate electrode and a source drain region formed at both sides thereof in the DRAM cell region and the logic cell region; Depositing a silicide blocking layer on a surface of the semiconductor substrate resultant; Selectively forming a first transition metal silicide layer on the gate electrode, the source, and the drain region of the logic cell region; Depositing an etch stopper on the semiconductor substrate including the silicide blocking layer; Forming a high density plasma insulating film on the etch stopper to fill a space between the gate electrodes; Etching back the high density plasma insulating film, the etch stopper and the silicide blocking layer so as to shield the source and drain regions while exposing the upper gate electrode of the DRAM cell region; And And forming a second transition metal silicide layer on the gate electrode of the exposed DRAM cell region. The method of claim 1, wherein forming the silicide blocking layer, Depositing a buffer insulating film on the semiconductor substrate; And forming a silicon nitride film over the buffer insulating film. The method of manufacturing a semiconductor memory device according to claim 1 or 2, wherein the etch stopper is a silicon nitride film or a silicon nitride oxide film. The method of claim 1, wherein the second transition metal silicide layer is formed to have a thickness different from that of the first transition metal silicide layer. The method of claim 1, wherein the forming of the first transition metal silicide layer selectively on the gate electrode, the source, and the drain region of the logic cell region, Forming a photoresist pattern to expose a silicide blocking layer of the logic cell region; Removing the exposed silicide blocking layer; Removing the photoresist pattern; Depositing a transition metal film on the semiconductor substrate in the logic cell region; Reacting the transition metal layer to form a first transition metal silicide layer on the gate electrode and the source drain region of the logic cell region; And removing the unreacted transition metal film. The method of claim 1, wherein the etching of the high density plasma insulating layer, the etch stopper and the silicide blocking layer to shield the source and drain regions while exposing the gate electrode of the DRAM cell region is performed. Forming a photoresist pattern on the high density plasma insulating layer to expose the DRAM cell region; And etching back the high density plasma insulating film, the etch stopper, and the silicide blocking layer of the exposed DRAM cell region so as to be buried in a space between the gate electrodes while exposing the upper portion of the gate electrode. Providing a semiconductor substrate having a DRAM cell region and a logic cell region defined therein, each having a gate electrode and a source drain region formed at both sides thereof in the DRAM cell region and the logic cell region; Depositing a silicide blocking layer on a surface of the semiconductor substrate resultant; Selectively forming a first transition metal silicide layer on the gate electrode, the source, and the drain region of the logic cell region; Depositing an etch stopper on the semiconductor substrate including the silicide blocking layer; Forming a high density plasma insulating film on the etch stopper to fill a space between the gate electrodes; Etching back the high density plasma insulating film, the etch stopper and the silicide blocking layer so as to shield the source and drain regions while exposing the upper gate electrode of the DRAM cell region; Forming a second transition metal silicide layer on the gate electrode of the exposed DRAM cell region; Forming an interlayer insulating film on the semiconductor substrate product; And And forming a storage node contact hole by etching the interlayer insulating film, the high density plasma insulating film, the etch stopper, and the silicide blocking layer so that the source region of the DRAM cell region is exposed. The method of claim 7, wherein forming the silicide blocking layer, Depositing a buffer insulating film on the semiconductor substrate; And forming a silicon nitride film over the buffer insulating film. The method of claim 7, wherein the etch stopper is a material having an etch selectivity similar to a portion of the silicide blocking layer while having an etch selectivity different from that of the interlayer insulating film. 10. The method of claim 9, wherein the etch stopper is a silicon nitride film or a silicon nitride oxide film. The method of claim 7, wherein the second transition metal silicide layer is formed to have a thickness different from that of the first transition metal silicide layer. The method of claim 7, wherein the forming of the first transition metal silicide layer on the gate electrode, the source, and the drain region of the logic cell region may be performed. Forming a photoresist pattern to expose a silicide blocking layer of the logic cell region; Removing the exposed silicide blocking layer; Removing the photoresist pattern; Depositing a transition metal film on the semiconductor substrate in the logic cell region; Reacting the transition metal layer to form a first transition metal silicide layer on the gate electrode and the source drain region of the logic cell region; And removing the unreacted transition metal film. 8. The method of claim 7, wherein the step of etching back the high density plasma insulating film, the etch stopper and the silicide blocking layer so as to shield the source and drain regions while exposing the upper gate electrode of the DRAM cell region, Forming a photoresist pattern on the high density plasma insulating layer to expose the DRAM cell region; And etching back the high density plasma insulating film, the etch stopper, and the silicide blocking layer of the exposed DRAM cell region so as to be buried in a space between the gate electrodes while exposing the upper portion of the gate electrode. The method of claim 7, further comprising: forming a lower electrode on the interlayer insulating layer to contact the source region of the exposed DRAM cell region after forming the storage node contact hole; Coating a dielectric film on the lower electrode surface; And forming an upper electrode on the dielectric film.