JP2550590B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device in which a contact electrode for a semiconductor substrate is formed between two gate electrodes formed on the semiconductor substrate.

B. SUMMARY OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which a contact electrode for a semiconductor substrate is formed between two gate electrodes formed on the semiconductor substrate, the two gate electrodes being formed by atmospheric pressure chemical vapor deposition. An insulating film is thinly formed on the gap portion, and the gate electrode gap portion is opened in a conformal manner to realize a good connection at a fine opening portion.

C. Conventional Technology In a semiconductor device such as a memory device, a semiconductor substrate may be connected to a contact electrode via an opening in a gap between two adjacent gate electrodes.

6 to 8 are views showing a semiconductor device in which the gate electrodes are contacted with each other.
Two gate electrodes 62A and 62B having a polycide structure are formed on the top. Sidewall portions 63 and 63 are formed on the side portions of the respective gate electrodes 62A and 62B, and oxide films 64 and 64 are formed on the upper portions of the respective gate electrodes 62A and 62B. A first interlayer insulating film 65 is formed on the top of the first interlayer insulating film 65, and an opening 67 is self-aligned in the gate electrode gap 66 between the two gate electrodes 62A and 62B. Is formed by. That is, the first
The inter-layer insulating film 65 is formed with a substantially uniform thickness, and since the oxide films 64, 64 are formed on the gate electrodes 62A, 62B in particular, the insulating material is thick, and therefore, the gate electrode gap portion 66 is self-aligned with impurities. An opening 67 exposing the region 69 is formed. A contact electrode 68 made of polycrystalline silicon is connected to the impurity region 69 exposed on the surface of the semiconductor substrate 61 through the opening 67, and the contact electrode 68 is an opening provided in the second interlayer insulating film 70. Aluminum wiring layer through 71
Connect with 72.

D. Problems to be Solved by the Invention Such a gate electrode gap 6 between the gate electrodes 62A and 62B
The miniaturization is required for the semiconductor device to be connected in 6, while the good connection is required.

However, in the above semiconductor device, the oxide film 64
The film quality at the contact portion 80 of the sidewall 63 is poor, and there is a portion where the breakdown voltage is locally reduced. Then, a leak or the like occurs at that portion, and the contact electrode 68 and the gate electrode 62A are
It becomes difficult to obtain a sufficient withstand voltage between and.

Therefore, an object of the present invention is to provide a semiconductor device manufacturing method for easily manufacturing a semiconductor device having a structure that realizes good connection.

E. Means for Solving the Problems The present invention relates to a method for manufacturing a semiconductor device in which a contact electrode for a semiconductor substrate is formed between two gate electrodes formed on the semiconductor substrate, and at least two gates are provided at predetermined intervals. An electrode formation step, a step of forming an insulating film thinner on the gate electrode gap than on the gate electrode by atmospheric pressure chemical vapor deposition, and an opening at least on the gate electrode and the gate electrode gap A step of forming an etching mask having: a step of selectively etching the insulating film on the gap between the gate electrodes by using the etching mask to expose the semiconductor substrate; and a contact connecting to the exposed semiconductor substrate. The above-mentioned problems are solved by a method of manufacturing a semiconductor device, which comprises a step of forming electrodes.

F. Action By forming the insulating film thinner on the gate electrode gap than on the gate electrode by the atmospheric pressure chemical vapor deposition method, the insulating film is formed on the gate electrode above the gate electrode gap where the opening is finally formed. In that case, the formed insulating film becomes thicker. Then, when anisotropic etching is performed through the etching mask extending from the gate electrode gap portion to each gate electrode, a part of the insulating film is formed on the gate electrode depending on the film thickness difference of the insulating film. Remains. The part where the film quality is poor is covered by this partially remaining insulating film, and the breakdown voltage does not deteriorate.

Here, the atmospheric pressure chemical vapor deposition method for forming the insulating film thinner on the gap between the gate electrodes than on the gate electrode will be described with reference to FIGS. 4 and 5. First, the fifth
The figure shows each parameter S, T _A , T _B
S is the distance between the two gate electrodes, T _A is the thickness of the insulating film formed on the gate electrode by atmospheric pressure chemical vapor deposition, and T _B is atmospheric pressure chemical vapor deposition. Is the film thickness of the insulating film formed in the gap between the gate electrodes. From the result of the experiment conducted by the present inventor, for example, when the thickness of the gate electrode is 3500Å, the correlation shown by the curve k between the parameter S and T _B / T _A as shown in FIG. 4 is obtained. Has been. That is, when the distance S between the two gate electrodes becomes shorter, the insulating film thickness T _{B in} the gap between the gate electrodes becomes relatively smaller than the insulating film thickness T _A on the gate electrode. When the distance S between the gate electrodes is 1.5 μm, T _B / T _A is 70%, when the distance S is 1.2 μm, T _B / T _A is 65%, when the distance S is 1.0 μm, T _B / T _A is
Data such as 60% are obtained. These values depend on the film thickness of the gate electrode and the performance of the atmospheric pressure chemical vapor deposition apparatus used, but as an example, T _B / T _A is 70% or less, that is, the distance S between the gate electrodes is 1.5 μm. Or less, more preferably T _B / T _A is 60% or less, that is, the distance S between the gate electrodes is 1.0
When the thickness is not more than μm, the insulating film can be left on the gate electrode by anisotropic etching using the above etching mask.

G. Embodiment A preferred embodiment of the present invention will be described with reference to the drawings.

This example is a method of manufacturing a memory device such as a DRAM, in which an insulating film is formed thinner on the gate electrode gap than on the gate electrode by atmospheric pressure chemical vapor deposition, and the film thickness This is a method of forming an opening for connection by self-alignment with a difference. Hereinafter, this embodiment will be described in accordance with the steps thereof with reference to FIGS. 1A to 1F.

(A) First, as shown in FIG. 1A, a semiconductor substrate 1 is provided with a gate oxide film 2 and an oxide film 4 on the upper surface of the semiconductor substrate 1.
Two polycide structures (eg tungsten silicide /
Gate electrodes 3A and 3B having a laminated structure of polycrystalline silicon) are formed. The distance S between the two gate electrodes 3A and 3B is, for example, 1.5 μm or less when the thickness of the gate electrode is 3500Å,
It is preferably 1.0 μm or less. Then, impurities of the opposite conductivity type to the semiconductor substrate 1 are introduced in self-alignment with the gate electrodes 3A, 3B to form impurity regions 5.

(B) Next, as shown in FIG. 1b, an insulating film is formed on the entire surface and is etched back to form the gate electrodes 3A, 3
Sidewall portions 6, 6 are formed on the side portions of B. After the surface oxidation, the side wall portions 6 and 6 and the gate electrode 3 are
Ions are implanted at a high concentration using A, 3B and the like as masks to form a high concentration impurity region 7 so as to form a so-called LDD structure MOS transistor. If the LDD structure is not used, the sidewall portion 6 need not be formed.

(C) Next, as shown in FIG. 1c, the insulating film 9 is formed on the gate electrodes 3A and 3B by atmospheric pressure chemical vapor deposition (atmospheric pressure CVD method).
The gate electrode gap portion 8 is formed thinner than the upper portion. That is, according to the correlation shown in FIG. 4, at the interval S, the film thickness T _A of the insulating film 9 on the gate electrodes 3A and 3B is thicker than the film thickness T _B of the insulating film 9 on the gate electrode gap portion 8. Become thick. Here, for example, the film thickness T _A of the insulating film 9 on the gate electrodes 3A and 3B is set to 300
In the case of 0Å, the insulating film 9 on the gate electrode gap 8
It is also possible to make the film thickness T _B of about 2000 Å. Such atmospheric pressure chemical vapor deposition method is performed by depositing silicon oxide at a low temperature (for example, about 410 ° C.) using an atmospheric pressure CVD apparatus.

(D) After forming the insulating film 9 so that a film thickness difference is generated between the gate electrodes 3A and 3B and the gate electrode gap portion 8, as shown in FIG. Use at least the above gate electrodes 3A, 3B
Then, an etching mask 11 having an opening 10 is formed on the gate electrode gap 8. Then, the insulating film 9 formed thick on the gate electrodes 3A and 3B and thin in the gate electrode gap 8 faces the bottom of the opening 11.

(E) Next, anisotropic etching is performed using this etching mask 11. This anisotropic etching is performed in self-alignment with the gate electrodes 3A and 3B. In this embodiment, in particular, as shown in FIG. The insulating film 9 on the gap 8 is selectively etched, and a part of the impurity region 7 of the semiconductor substrate 1 is exposed in the gate electrode gap 8. At the same time, the insulating film 9 remains on the gate electrodes 3A, 3B, and the oxide film 4 on the gate electrodes 3A, 3B is not exposed but remains covered. The film thickness T _C of the insulating film 9 on the remaining gate electrodes 3A and 3B is about the above film thickness (T _A −T _B ), and the film thickness of about 1000 Å can be left with the above numerical values. . Since the insulating film 9 remains on the gate electrodes 3A and 3B in this manner, a portion having poor film quality is completely covered, and good connection with less adverse effects such as leakage can be realized.

(F) After performing such selective etching, as shown in FIG. 1f, the etching mask 11 is removed, and the contact electrode 12 connected to the exposed impurity region 7 of the semiconductor substrate 1 is formed into a first layer. It is formed by the second-layer polycrystalline silicon layer.
Below the contact electrode 12 and above the gate electrode
Since not only the oxide film 4 but also the remaining insulating film 9 with a film thickness T _C is formed in the regions above 3A and 3B, even if the contact electrode 12 is formed after etching, the insulation The quality is good. Then, a second interlayer insulating film 13 is formed, and an opening 14 is provided in the second interlayer insulating film 13. Then, an aluminum wiring layer 15 to be a bit line or the like is formed through the opening 14, and the semiconductor device is substantially completed.

2 and 3 show an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device of the present embodiment,
In FIG. 2, a rectangular region Y indicated by a broken line is a region corresponding to the opening 10. In this region, selective etching due to the difference in film thickness of the insulating film 9 is performed and impurities in the contact electrode 12 and the semiconductor substrate 1 are removed. A connection with the area 7 is made. Incidentally, FIG. 1f
Corresponds to the sectional view taken along the line II 'of FIG. 2, and FIG. 3 corresponds to the sectional view taken along the line III-III' of FIG.

In the method of manufacturing a semiconductor device according to the present embodiment, when anisotropic etching is performed due to the film thickness difference between the gate electrodes 3A and 3B of the insulating film 9 and the gate electrode gap portion 8 as described above. In addition, the insulating film 9 can be left on the gate electrodes 3A and 3B. As a result, the portion with poor film quality between the side wall portion 6 and the oxide film 4 is covered, and the problem of breakdown voltage between the contact electrode 12 and the gate electrode 3A is solved. Further, since the leak and the like are effectively prevented as described above, the process margin and the like can be reduced, which is advantageous for miniaturization.

Although the gate electrode has a polycide structure in the above-described embodiments, the structure is not limited to this and may be another structure. The present invention can also be applied to a connection structure in which a plurality of contact electrodes are laminated.

H. Effect of the Invention In the method for manufacturing a semiconductor device of the present invention, as described above, the insulating film having the film pressure difference is formed by the atmospheric pressure chemical vapor deposition method over the gate electrode and over the gap between the gate electrodes. By utilizing this insulating film, the insulating film can be effectively left on the gate electrode. Therefore, it is possible to cover a portion having a poor film quality, and it is possible to enhance the withstand voltage and the like to achieve a good connection.

[Brief description of drawings]

1A to 1F are process cross-sectional views according to the steps of an example of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a semiconductor manufactured by applying the method for manufacturing a semiconductor device of the present invention. FIG. 3 is a plan view of an example of the apparatus, and FIG. 3 is a sectional view taken along the line III-III ′ of FIG. Further, FIG. 4 is a characteristic diagram showing the correlation between the distance S between the gate electrodes and the ratio T _B / T _A of the film thickness of the insulating film, and FIG. 5 is a schematic diagram showing its parameters. Also,
FIG. 6 is a diagram showing an example of a conventional semiconductor device.
FIG. 7 is a sectional view taken along the line VI-VI ′ of FIG. 7, FIG. 7 is a plan view showing an example of a conventional semiconductor device, and FIG. FIG. 1 ... Semiconductor substrate 3A, 3B ... Gate electrode 4 ... Oxide film 7 ... Impurity region 8 ... Gate electrode gap 9 ... Insulating film 10 ... Opening 11 ... Etching mask 12 ... Contact electrode T the distance between _a ...... insulating film on the gate electrode film thickness T _B ...... insulating film on the gate electrode gap portion thickness S ...... gate electrode

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device, wherein a contact electrode for a semiconductor substrate is formed between two gate electrodes formed on a semiconductor substrate, a step of forming at least two gate electrodes at a predetermined interval, and a normal pressure. Forming an insulating film thinner on the gate electrode gap than on the gate electrode by chemical vapor deposition; forming at least the gate electrode and an etching mask having an opening on the gate electrode gap A step of selectively etching the insulating film on the gap between the gate electrodes by using the etching mask to expose the semiconductor substrate, and a step of forming a contact electrode connected to the exposed semiconductor substrate. A method for manufacturing a semiconductor device, comprising: