JPH03256358A - Semiconductor memory device and manufacturing method - Google Patents

Abstract

PURPOSE:To obtain a fine memory cell which uses a thin ferroelectric film for accumulated electrodes by covering an offset induced by a separation oxide layer between a word line, a bit line and components with an insulation material so as to make the surface flat and then forming an accumulated capacity section which uses the ferroelectric thin film on the flattened surface. CONSTITUTION:An accumulated capacity section is not directly formed on an offset induced by a separation oxide layer 2 between a word line 4, a bit line 8 and components, but the capacity section, which comprises a lower part of electrode, a thin ferroelectric film 15 and a plate electrode 16, is formed on a flattened surface covered with an insulation film 12 after having formed a switching transistor and the bit line 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, a semiconductor memory device using a ferroelectric capacitor as an insulating film of a charge storage capacitor and a method for manufacturing the same. Regarding.

[Prior art] Regarding memories using conventional ferroelectric capacitors,
ISS CC 89, 1989, pp. 242-243.

[Problem to be solved by the invention] In the above conventional technology, the processing size is 3 μm, 1 cell size is 1
The ferroelectric capacitor is as large as 1×21 μm3 and is formed on a flat portion on the gate electrode.

On the other hand, DRAM (Dynamic Random Access Memory)
Memory) has been achieving high integration at a rate of four times in three years, and mass production of megabit memory has already begun. This high degree of integration has been achieved mainly by miniaturizing elements. However, due to the reduction in storage capacity accompanying miniaturization, adverse effects such as a reduction in the signal-to-noise (SN) ratio and signal inversion due to the incidence of alpha rays have become apparent, and ensuring reliability has become a major problem.

For this reason, instead of the conventional planar cell that uses only the surface of the substrate as a storage capacitor, a part of the storage capacitance can be used as a switching transistor or separated between elements as described in Japanese Patent Publication No. 61-55528. A stacked capacitor cell (ST) stacked on the oxide film 1
Tacked Capacitor)) is used.

Furthermore, as an STC structure for realizing a fine cell area, there are those described in Japanese Utility Model Application Publication No. 55-178894, and the one described in I. Niss.DM.88 (1988
) pp. 596-599 (IS DM88.1988
(pp. 596-599).

FIGS. 2 and 3 show respective planar layouts. In these STC structures, the bit line is formed before the storage electrode, so the area of the storage capacitor can be increased. On the other hand, the insulating film of the storage capacitor is
It is formed on a step formed by a bit line, an isolation oxide film between elements, or the like.

However, it is difficult to form a ferroelectric thin film on such a step, and for this reason, it is extremely difficult to realize an ultra-highly integrated memory using a ferroelectric as an insulating film for a storage capacitor. It is.

An object of the present invention is to provide an STC type super-high density integrated memory using a ferroelectric thin film.

[Means for solving the problem 1: Level differences caused by word lines, bit lines, element isolation oxide films, etc. are flattened by covering them with an insulating material, and then a storage capacitor using a ferroelectric thin film is formed on this flat surface. The gist is to form a section.

That is, the method for manufacturing a semiconductor memory device of the present invention includes a memory cell having one switching transistor and one charge storage capacitor, and a ferroelectric material is used as a dielectric film of the charge storage capacitor. The method for manufacturing the semiconductor memory device used includes the steps of: covering the semiconductor substrate on which the switch transistor is formed with an insulating material and flattening the underlying step; and then, forming a contact hole in the insulating material. , then, the step of filling the inside of the contact hole with a conductive material, the step of forming a lower electrode on the flat surface, and the step of forming a ferroelectric film on the lower electrode. Features.

Further, the semiconductor memory device of the present invention includes a memory cell having one switching transistor and one charge storage capacitor, and uses a ferroelectric material as an insulating film of the charge storage capacitor. The device is characterized by comprising an insulating material covering the semiconductor substrate on which the switching transistor is formed and flattening the underlying step, and a lower electrode and a ferroelectric film formed on the flat surface.

[Effect]

In the semiconductor memory device of the present invention, by forming the storage electrode portion on a flat surface, a fine memory cell using a ferroelectric thin film in the storage electrode portion can be realized.

Furthermore, in the method for manufacturing a semiconductor memory device of the present invention, it is possible to realize a fine memory hill using a ferroelectric thin film for the storage electrode part, and the lower electrode is also formed on a flat surface, so it is possible to use a method such as sputtering. It can be easily formed using a method that provides low step coverage.

Further, since the formation of the ferroelectric thin film can be performed separately from the formation of the switching transistor, problems such as damage to the S1 interface can be avoided.

Note that the structure of the present invention can be used for both a DRAM in which the polarization of a ferroelectric material is not inverted, and a nonvolatile memory in which the polarization is inverted.

[Example] Example 1 FIG. 1 is a sectional view of an STC type memory according to a first example of the present invention. 1 is a first conductive type semiconductor substrate, 2 is an element isolation oxide film, 3 is a gate oxide film, 4 is a word line, 5.7.
9, lo is an interlayer insulating film, 6 is a second conductivity type impurity diffusion layer,
8 is a bit line, 12 is a flattening insulating film, 11 and 13 are memory contact plugs, 14 is a lower electrode, 15 is a ferroelectric thin film, and 16 is a plate electrode.

The steps up to bit line formation in this embodiment are no different from the conventional process. In this embodiment, word line 4, bit line 8, element isolation oxidation JI! After forming the switching transistor and the bit line 8 instead of directly forming the storage capacitor section on the step such as 2,
A structure is used in which a storage capacitor section (lower electrode 14, ferroelectric thin film 15, plate electrode 16) is formed on the insulating film 12 covered and planarized. In this cross-sectional view, the source/drain has a simple impurity diffusion layer structure, but it is also possible to use a known electric field relaxation type source/drain impurity diffusion layer structure. Note that an interlayer insulating film (not shown) is formed on the plate electrode 15, and A1 etc. are wired.
It is omitted here.

Example 2 In this example, the planar layout shown in FIG. 2 was used. 21 is an active region where a channel region and an impurity diffusion layer of a switching transistor are formed; 4 is a word line serving as a gate electrode of the switching transistor; 23 is a contact hole for bringing the bit line 8 into contact with the diffusion layer of the substrate;
25 is a memory part contact hole for connecting the storage capacitor lower electrode and the diffusion layer, and 8 is a bit line. For clarity, the storage capacitor lower electrode and plate electrode disposed above the memory part contact hole 25 are omitted.

First, as shown in FIG. 4(2), a switch transistor is formed by a known MO3FET forming process. Here, 1 is a first conductivity type semiconductor substrate, 2 is an element isolation insulating film, 3 is a gate oxide film, 4 is a word line, 5 is an interlayer insulating film, and 6 is a second conductivity type impurity diffusion layer (for example, n type, arsenic, phosphorus, etc.).

Next, as shown in FIG. 4(b), a known CV is applied to the entire surface.
An insulating film 41 is deposited using the D method, and an opening is made using known photolithography and dry etching methods only in the portion where the bit line contacts the diffusion layer of the substrate. This insulating film serves as a base for processing bit lines in the next step, and serves to prevent the substrate surface from being exposed and the element isolation insulating film from being scraped. The film thickness is determined by the selection ratio with respect to the underlying layer during bit line processing. In this example, it was set to 20 to 1100n.

Next, bit lines 8 are formed as shown in FIG. 4(C). A laminated film of metal silicide and polycrystalline silicon or tungsten was used as the material for the bit line. On top of this, BP
A silicon oxide film-based insulating film 12 such as SG is deposited by CVD or the like and planarized. This insulating film needs to be thick enough to fill in the level difference underneath and flatten it.

In this example, the film thickness was set to 500 to 11000 nm. Note that a method may be used in which 5102 is deposited on the step by a CVD method and planarized by an etch-back method.

Next, as shown in FIG. 4(d), a memory part contact hole 42, through which the storage capacitance part comes into contact with the substrate, is opened using a known photolithography method and dry etching method. This contact hole is filled with a conductive material 43. In this embodiment, a method was used in which polycrystalline silicon was selectively grown using a known CVD method and then an impurity of the same conductivity type as the impurity diffusion layer was diffused, but tungsten may also be used.

Next, the lower electrode 14 is formed as shown in FIG. 4(e).

In this example, a thickness of approximately 100 mm was obtained using the DC sputtering method.
A Pt film was deposited. After patterning by sputter etching using photoresist as a mask,
A ferroelectric thin film 15 is formed on this surface. In this example, a thickness of approximately 50 nm was obtained by high-frequency magnetron sputtering.
m of PbTiO2 was formed, but as a ferroelectric film, PbTiO2 was formed.
b (Z rxT 1 +−x)03 or the like may be used. Further, as a method for forming the ferroelectric film, a known sol-gel method, CVD method, MOCVD method, or the like may be used.

Next, a plate electrode 16 is deposited to complete the storage capacitor portion of the memory cell. Finally, an interlayer insulating film is formed and Al wiring is formed on it to complete the memory cell.

Example 3 In this example, the planar layout shown in FIG. 3 was used. Here, 31 is an active region where a channel region and an impurity diffusion layer of a switching transistor are formed, and 4
33 is a contact hole for connecting the bit line 8 and the diffusion layer of the substrate; 35 is a memory part contact hole for connecting the storage capacitor lower electrode 14 and the diffusion layer; 16 is a plate electrode.

In this planar layout, the active area is the word line
Since it is arranged obliquely to the bit line, its cross-sectional view is taken along a line connecting the centers of two memory contact holes 35 in the same active region.

In this embodiment, as shown in FIG. 5(2), after a bit line is deposited in the same manner as in the second embodiment, an insulating film 9 is deposited on the bit line.
be coated with. Then, bit lines are processed together with this insulating film. Furthermore, an insulating film 10 is deposited to cover the sidewalls of the bit lines exposed in the previous processing by using a known dry etching method.

In this way, the region where the memory contact hole 35 is opened is surrounded by the insulated word line and the insulated bit line, and the memory contact region is formed in a self-aligned manner. Next, a conductor layer 11 is selectively grown only on the exposed diffusion layer in the memory contact region. In this example, polycrystalline silicon was selectively grown using a known CVD method, and impurities of the same conductivity type as the impurity diffusion layer were diffused (FIG. 5(b)).

In the first embodiment (FIG. 4(d)), it is necessary to form deep memory contact holes in narrow regions between word lines. If the hole is shifted onto the word line due to misalignment, there is a risk that the underlying word line will be exposed when the hole is formed. Therefore, as in this embodiment, the diffusion layer region is lifted (conductor layer 1
1) facilitates processing when opening a contact hole.

From FIG. 5(b) onward, after planarization is performed with an insulating film, a storage capacitor section and wiring are formed to complete a memory cell as shown in FIG. 1.

Although the present invention has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples, and it goes without saying that various modifications can be made without departing from the gist thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to form a minute memory cell using a ferroelectric material that has poor step coverage and is difficult to make into a thin film, and it is also possible to realize gigabit level memory.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a memory cell according to an embodiment of the present invention, and FIG.
The figure shows a conventional STC type DRAM and another embodiment of the present invention.
A plan view of the cell, FIG. 3 is a second plan view of the STC type DRAM cell of the conventional and another embodiment of the present invention, FIG. 4 (2)
~(d) is a manufacturing process diagram of an embodiment of the present invention, and FIG.
) and (b) are manufacturing process diagrams of another embodiment of the present invention. l...first conductivity type semiconductor substrate 2...element isolation oxide film 3...gate oxide film 4...word line 5.7.9.10...interlayer insulating film 6...th 2-conductivity type impurity diffusion eyebrow 8...Bit line 11.13...Memory part contact plug 14...
Lower electrode 15... Ferroelectric thin film 16... Plate electrode 21.31... Active region 3.33... Contact hole 5.35.42... Memory part contact... Insulating film 3...・Conductive substance ketopore

Claims (1)

[Claims] 1. A semiconductor memory device comprising one switching transistor and one memory cell having a charge storage capacitor, and using a ferroelectric material as a dielectric film of the charge storage capacitor. The manufacturing method includes the steps of: covering the semiconductor substrate on which the switch transistor is formed with an insulating material and flattening the underlying step; thereafter, forming a contact hole in the insulating material; A semiconductor memory comprising the steps of burying the inside of the hole with a conductive material, then forming a lower electrode on the flat surface, and then forming a ferroelectric film on the lower electrode. Method of manufacturing the device. 2. Before the semiconductor substrate on which the switch transistor is formed is covered with an insulating material to flatten the underlying step, a conductor layer is provided on the impurity-doped layer of the switch transistor, and the conductor layer is then flattened. 2. The method of manufacturing a semiconductor memory device according to claim 1. 3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the conductive material is polycrystalline silicon. 4. The method of manufacturing a semiconductor memory device according to claim 1 or 2, wherein the lower electrode is made of platinum. 5. The lower electrode is made of gold, copper, tungsten or C.
3. The method of manufacturing a semiconductor memory device according to claim 1, wherein the semiconductor memory device is u_3Au. 6. The lower electrode is made of tungsten silicide (WSi_
2), zirconium silicide (ZrSi_2) or molybdenum silicide (M
Claim 1 or 2 characterized in that oSi_2)
A method of manufacturing the semiconductor storage device described above. 7. Claims 1, 2, 3, and 4, wherein the ferroelectric film is formed by high-frequency magnetron sputtering.
or 5. The method of manufacturing a semiconductor memory device according to 5. 8. Claim 1, wherein the ferroelectric film is formed by a CVD method or an MOCVD method.
, 2, 3, 4 or 5, the method for manufacturing a semiconductor memory device. 9. The method of manufacturing a semiconductor memory device according to claim 1, 2, 3, 4 or 5, wherein the ferroelectric film is formed by a sol-gel method. 10. A semiconductor memory device comprising one switching transistor and one memory cell having a charge storage capacity, and using a ferroelectric material as an insulating film of the charge storage capacity, wherein the switching transistor is 1. A semiconductor memory device comprising: an insulating material that covers a formed semiconductor substrate and flattens an underlying step; and a lower electrode and a ferroelectric film formed on the flat surface.