US20010024862A1 - Method for forming a lower electrode by using an electroplating method - Google Patents
Method for forming a lower electrode by using an electroplating method Download PDFInfo
- Publication number
- US20010024862A1 US20010024862A1 US09/735,528 US73552800A US2001024862A1 US 20010024862 A1 US20010024862 A1 US 20010024862A1 US 73552800 A US73552800 A US 73552800A US 2001024862 A1 US2001024862 A1 US 2001024862A1
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- United States
- Prior art keywords
- approximately
- layer
- seed layer
- forming
- dummy oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
Definitions
- the present invention relates to a semiconductor device; and, more particularly, to a method for forming a lower electrode for use in a semiconductor device by using an electroplating method.
- a dynamic random access memory with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization.
- DRAM dynamic random access memory
- the capacitor such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor.
- the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
- Pt platinum
- RIE reactive ion etching
- a method for manufacturing a semiconductor device for use in a memory cell comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a seed layer on top of the active matrix; c) forming a dummy oxide layer on top of the seed layer; d) patterning the dummy oxide layer into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs; e) filling the exposed portions with a first conductive material to a predetermined thickness; f) removing the dummy oxide layer; g) removing portions of the seed layer which are not covered with the conductive material, thereby obtaining lower electrodes; h) forming a capacitor dielectric layer on the lower electrodes; and i) forming a second conductive layer on the
- FIGS. 1A to 1 H are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.
- FIGS. 1A to 1 H cross sectional views setting forth a method for manufacturing a semiconductor device incorporating therein a lower electrode which is formed by using an electroplating method in accordance with preferred embodiments of the present invention.
- FIGS. 1A to 1 H are schematic cross sectional views setting forth the method for manufacture of a capacitor structure 150 for use in a semiconductor memory device 100 in accordance with the present invention.
- the process for manufacturing the semiconductor device 100 begins with the preparation of an active matrix 110 including a silicon substrate 102 , an isolation region 104 , diffusion regions 106 , gate oxides 108 , gate lines 112 , a sidewall 114 , a bit line 118 , poly plugs 116 , barrier metals 126 , anti-reflection coating (ARC) films 124 and an insulating layer 122 , as shown in FIG. 1A.
- the bit line 118 is electrically connected to one of the diffusion regions 106 to apply an electric potential.
- Each of the poly plugs 116 is electrically connected to the other diffusion regions 106 , respectively.
- the capacitor structures 140 can be connected to a plate line (not shown) to apply thereto a common constant potential.
- the insulating layer 122 is made of a material, e.g., boron-phosphor-silicate glass (BPSG).
- the barrier metals 126 are formed on top of the poly plugs 116 and the ARC films 124 are formed on portions of the active matrix 110 which are not covered with the barrier metals 126 . It is preferable that the barrier metals 126 are made of a material selected from a group consisting of TiN, TiSiN, TiAlN, TaSiN, TaAlN or the like. And also, the ARC films 124 are formed with a material having a high etch selectivity with respect to a dummy oxide layer to be formed thereon in a thickness ranging from approximately 300 ⁇ to approximately 1,000 ⁇ .
- films 125 e.g., made of TiS x , can be formed between the poly plugs 116 and the barrier metals 126 in a thickness ranging from approximately 100 ⁇ to approximately 300 ⁇ .
- CMP chemical mechanical polishing
- a seed layer 130 is formed by using a chemical vapor deposition (CVD) method on top of the ARC films 124 and the barrier metals 126 , as shown in FIG. 1B.
- the seed layer 130 can be made of a material selected from a group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like. It is preferable that if Pt is selected as the seed layer 130 , the seed layer 130 has a thickness ranging from approximately 50 ⁇ to approximately 1,000 ⁇ .
- a dummy oxide layer is formed on top of the seed layer 130 by using a method such as CVD.
- the dummy oxide layer can be made of PSG or USG.
- the dummy oxide has a thickness ranging from approximately 5,000 ⁇ to approximately 20,000 ⁇ .
- the dummy oxide layer is patterned into a predetermined configuration in such a way that portions of the seed layer 130 located on top of the poly plugs 116 are exposed, thereby forming a patterned dummy oxide 132 , as shown in FIG. 1C.
- the active matrix 110 is dipped into a solution selected from a 90% H 2 SO 4 solution, H 2 SO 4 /H 2 O 2 solution, HF/H 2 O solution, HF/HN 4 F solution during 2-3600 seconds in order to remove particles or foreign material remaining on the exposed seed layer 130 .
- the exposed portions of the seed layer 130 are electroplated with a material selected from a group consisting of consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like, as shown in FIG. 1D.
- a material selected from a group consisting of consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like is preferable that an electroplating material 134 corresponds to that of the seed layer 130 .
- the electroplating material is Pt
- a thickness of the electroplating material 134 has a thickness ranging from approximately 3,000 ⁇ to approximately 10,000 ⁇ .
- the electroplating process is carried out with a current density ranging from approximately 0.1 mA/cm 2 to approximately 10 mA/cm 2 . 20.
- the patterned dummy oxide 132 is removed by using a method such as a wet etching, as shown in FIG. 1E.
- each of the lower electrodes includes a electroplating material 134 and an etched seed layer 136 , as shown in FIG. 1F.
- a capacitor dielectric layer 138 e.g., made of barium strontium titanate (BST), are formed on the lower electrodes 137 and the ARC film 124 by using a CVD method at a temperature ranging from approximately 400° C. to approximately 600° C. in a thickness ranging from approximately 150 ⁇ to approximately 500 ⁇ , as shown in FIG. 1G. It is possible that the capacitor dielectric layer 138 are crystallized by using a rapid thermal process (RTP) at a temperature ranging from approximately 500° C. to approximately 700° C. in the presence of N 2 for 30-180 seconds.
- RTP rapid thermal process
- an upper electrode layer 140 is formed on the capacitor dielectric layer 138 by using a method such as a CVD, thereby forming capacitor structures 150 , as shown in FIG. 1H.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
- The present invention relates to a semiconductor device; and, more particularly, to a method for forming a lower electrode for use in a semiconductor device by using an electroplating method.
- As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by downsizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
- To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
- Since capacitance is a function of dielectric area and the dielectric constant of the dielectric material, there have been introduced a high K dielectric, e.g., barium strontium titanate (BST) or the like, as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film to increase capacitance in a given area. However, the use of high dielectric constant materials presents a problem when using a conventional material like ruthenium (Ru) as an electrode. The Ru electrode creates leakage current in the capacitance device.
- Therefore, platinum (Pt) is suitable for use as electrodes in this situation. However, Pt is very difficult to be patterned by a conventional process such as a reactive ion etching (RIE), vertically, which, in turn, gives sloped sidewalls to a patterned thick Pt layer.
- Thus, there remains a need for a method of forming an electrode compatible with a high K capacitor dielectric without representing the above-described problems.
- It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein lower electrodes which are formed by using an electroplating method.
- In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; b) forming a seed layer on top of the active matrix; c) forming a dummy oxide layer on top of the seed layer; d) patterning the dummy oxide layer into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs; e) filling the exposed portions with a first conductive material to a predetermined thickness; f) removing the dummy oxide layer; g) removing portions of the seed layer which are not covered with the conductive material, thereby obtaining lower electrodes; h) forming a capacitor dielectric layer on the lower electrodes; and i) forming a second conductive layer on the capacitor dielectric layer.
- The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
- FIGS. 1A to1H are schematic cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.
- There are provided in FIGS. 1A to1H cross sectional views setting forth a method for manufacturing a semiconductor device incorporating therein a lower electrode which is formed by using an electroplating method in accordance with preferred embodiments of the present invention.
- FIGS. 1A to1H are schematic cross sectional views setting forth the method for manufacture of a
capacitor structure 150 for use in a semiconductor memory device 100 in accordance with the present invention. - The process for manufacturing the semiconductor device100 begins with the preparation of an
active matrix 110 including asilicon substrate 102, anisolation region 104,diffusion regions 106,gate oxides 108,gate lines 112, asidewall 114, abit line 118,poly plugs 116,barrier metals 126, anti-reflection coating (ARC)films 124 and aninsulating layer 122, as shown in FIG. 1A. Thebit line 118 is electrically connected to one of thediffusion regions 106 to apply an electric potential. Each of thepoly plugs 116 is electrically connected to theother diffusion regions 106, respectively. Although thebit line 118 actually extends in right and left directions bypassing thepoly plugs 116, the drawing does not show these parts of thebit line 118. Thecapacitor structures 140 can be connected to a plate line (not shown) to apply thereto a common constant potential. Theinsulating layer 122 is made of a material, e.g., boron-phosphor-silicate glass (BPSG). - In the preferred embodiment, the
barrier metals 126 are formed on top of thepoly plugs 116 and theARC films 124 are formed on portions of theactive matrix 110 which are not covered with thebarrier metals 126. It is preferable that thebarrier metals 126 are made of a material selected from a group consisting of TiN, TiSiN, TiAlN, TaSiN, TaAlN or the like. And also, theARC films 124 are formed with a material having a high etch selectivity with respect to a dummy oxide layer to be formed thereon in a thickness ranging from approximately 300 Å to approximately 1,000 Å. In order to reduce contact resistance between thepoly plugs 116 and thebarrier metals 126,films 125, e.g., made of TiSx, can be formed between thepoly plugs 116 and thebarrier metals 126 in a thickness ranging from approximately 100 Å to approximately 300 Å. After the formation of thebarrier metals 126, a chemical mechanical polishing (CMP) can be carried out to make their top surface flatted. - In an ensuing step, a
seed layer 130 is formed by using a chemical vapor deposition (CVD) method on top of theARC films 124 and thebarrier metals 126, as shown in FIG. 1B. Theseed layer 130 can be made of a material selected from a group consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like. It is preferable that if Pt is selected as theseed layer 130, theseed layer 130 has a thickness ranging from approximately 50 Å to approximately 1,000 Å. - In a following step, a dummy oxide layer is formed on top of the
seed layer 130 by using a method such as CVD. The dummy oxide layer can be made of PSG or USG. Preferably, the dummy oxide has a thickness ranging from approximately 5,000 Å to approximately 20,000 Å. Thereafter, the dummy oxide layer is patterned into a predetermined configuration in such a way that portions of theseed layer 130 located on top of thepoly plugs 116 are exposed, thereby forming a patterneddummy oxide 132, as shown in FIG. 1C. - Optionally, the
active matrix 110 is dipped into a solution selected from a 90% H2SO4 solution, H2SO4/H2O2 solution, HF/H2O solution, HF/HN4F solution during 2-3600 seconds in order to remove particles or foreign material remaining on the exposedseed layer 130. - In a next step, the exposed portions of the
seed layer 130 are electroplated with a material selected from a group consisting of consisting of Pt, Ru, Ir, Os, W, Mo, Co, Ni, Au, Ag or the like, as shown in FIG. 1D. It is preferable that anelectroplating material 134 corresponds to that of theseed layer 130. If the electroplating material is Pt, a thickness of theelectroplating material 134 has a thickness ranging from approximately 3,000 Å to approximately 10,000 Å. In this case, the electroplating process is carried out with a current density ranging from approximately 0.1 mA/cm2 to approximately 10 mA/cm2. 20. Alternatively, it is possible to deposit a conductive material on top of the exposed positions of theseed layer 130 by using a CVD. - Thereafter, the patterned
dummy oxide 132 is removed by using a method such as a wet etching, as shown in FIG. 1E. - And then, the portions of the
seed layer 130 which are not covered by theelectroplating material 134 are etched-back by using a method such as a dry etching, thereby forminglower electrodes 137, wherein each of the lower electrodes includes aelectroplating material 134 and anetched seed layer 136, as shown in FIG. 1F. - In a subsequent step, a capacitor
dielectric layer 138, e.g., made of barium strontium titanate (BST), are formed on thelower electrodes 137 and theARC film 124 by using a CVD method at a temperature ranging from approximately 400° C. to approximately 600° C. in a thickness ranging from approximately 150 Å to approximately 500 Å, as shown in FIG. 1G. It is possible that the capacitordielectric layer 138 are crystallized by using a rapid thermal process (RTP) at a temperature ranging from approximately 500° C. to approximately 700° C. in the presence of N2 for 30-180 seconds. - Finally, an
upper electrode layer 140 is formed on the capacitordielectric layer 138 by using a method such as a CVD, thereby formingcapacitor structures 150, as shown in FIG. 1H. - While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Claims (20)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990062959A KR100342821B1 (en) | 1999-12-27 | 1999-12-27 | Method of manufacturing a capacitor in a semiconductor device |
KR1999-62959 | 1999-12-27 | ||
KR99-62959 | 1999-12-27 | ||
KR00-43958 | 2000-07-29 | ||
KR1020000043958A KR20020010308A (en) | 2000-07-29 | 2000-07-29 | Method for forming a metal electrode of a semiconductor device |
Publications (2)
Publication Number | Publication Date |
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US20010024862A1 true US20010024862A1 (en) | 2001-09-27 |
US6451666B2 US6451666B2 (en) | 2002-09-17 |
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Application Number | Title | Priority Date | Filing Date |
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US09/735,528 Expired - Fee Related US6451666B2 (en) | 1999-12-27 | 2000-12-14 | Method for forming a lower electrode by using an electroplating method |
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US (1) | US6451666B2 (en) |
JP (1) | JP2001210806A (en) |
DE (1) | DE10065350B4 (en) |
Families Citing this family (8)
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KR100504943B1 (en) * | 2000-11-15 | 2005-08-03 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
KR100501595B1 (en) * | 2000-11-15 | 2005-07-14 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
KR100414872B1 (en) * | 2001-08-29 | 2004-01-13 | 주식회사 하이닉스반도체 | Semiconductor device and fabricating method of the same |
KR100422594B1 (en) * | 2001-09-12 | 2004-03-16 | 주식회사 하이닉스반도체 | Capacitor in semiconductor device and method for fabricating the same |
KR100440073B1 (en) * | 2001-12-10 | 2004-07-14 | 주식회사 하이닉스반도체 | A method for forming a capacitor of a semiconductor device |
KR100579846B1 (en) * | 2003-12-11 | 2006-05-12 | 동부일렉트로닉스 주식회사 | A metal layer of semiconductor device, and a method thereof |
KR100641546B1 (en) * | 2004-12-16 | 2006-11-01 | 동부일렉트로닉스 주식회사 | Method of fabricating a MIMMetal- Insulator-Metal capacitor |
KR100675895B1 (en) * | 2005-06-29 | 2007-02-02 | 주식회사 하이닉스반도체 | Metal interconnection of semiconductor device and method of fabricating the same |
Family Cites Families (8)
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US5392189A (en) * | 1993-04-02 | 1995-02-21 | Micron Semiconductor, Inc. | Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same |
US5757612A (en) * | 1996-04-23 | 1998-05-26 | International Business Machines Corporation | Structure and fabrication method for non-planar memory elements |
DE19640241C1 (en) * | 1996-09-30 | 1998-04-16 | Siemens Ag | Manufacturing process for a high epsilon dielectric or ferroelectric layer and use of the process |
KR100269326B1 (en) * | 1998-06-08 | 2000-10-16 | 윤종용 | Capacitor having electrode formed by electroplating and method for manufacturing the same |
CN1516275A (en) * | 1998-07-03 | 2004-07-28 | ���µ�����ҵ��ʽ���� | Semiconductor device and its mfg. method |
KR100299594B1 (en) * | 1998-07-13 | 2001-09-22 | 윤종용 | Manufacturing method of DRAM device |
KR100505397B1 (en) * | 1998-12-30 | 2006-05-16 | 주식회사 하이닉스반도체 | Method for fabricating capacitor of semiconductor device |
KR100612561B1 (en) * | 2000-06-19 | 2006-08-11 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
-
2000
- 2000-12-14 US US09/735,528 patent/US6451666B2/en not_active Expired - Fee Related
- 2000-12-27 JP JP2000396570A patent/JP2001210806A/en not_active Ceased
- 2000-12-27 DE DE10065350A patent/DE10065350B4/en not_active Expired - Fee Related
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JP2001210806A (en) | 2001-08-03 |
DE10065350A1 (en) | 2001-07-26 |
DE10065350B4 (en) | 2008-08-07 |
US6451666B2 (en) | 2002-09-17 |
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