KR100342821B1 - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR100342821B1 KR100342821B1 KR1019990062959A KR19990062959A KR100342821B1 KR 100342821 B1 KR100342821 B1 KR 100342821B1 KR 1019990062959 A KR1019990062959 A KR 1019990062959A KR 19990062959 A KR19990062959 A KR 19990062959A KR 100342821 B1 KR100342821 B1 KR 100342821B1
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- South Korea
- Prior art keywords
- capacitor
- forming
- film
- semiconductor device
- platinum
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- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 76
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 35
- 238000009713 electroplating Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052707 ruthenium Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052741 iridium Inorganic materials 0.000 claims description 4
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052762 osmium Inorganic materials 0.000 claims description 4
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 2
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 claims description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 claims description 2
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 13
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052788 barium Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Abstract
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 하부전극으로 플래티늄(Pt)을 이용하는 스택형 BST 캐패시터에서, 플래티늄의 열악한 식각 특성으로 인하여 셀당 요구되는 캐패시턴스를 확보할 수 없는 문제점을 해결하기 위하여, 플래티늄 등을 이용하여 시드(Seed)층을 매우 얇게 형성하고, 시드층 상에 더미 패턴을 형성한 후, 전기도금(ElectroChemical Deposition)으로 플래티늄을 증착하고 더미 패턴을 제거하여 스택형 플래티늄 하부전극을 형성하므로써, BST 캐패시터의 캐패시턴스 특성을 개선할 수 있도록 한 반도체 소자의 캐패시터 제조방법이 개시된다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, in a stack type BST capacitor using platinum (Pt) as a lower electrode, in order to solve the problem that the required capacitance per cell cannot be secured due to poor etching characteristics of platinum, A seed layer is formed very thin using platinum, a dummy pattern is formed on the seed layer, and platinum is deposited by electroplating, and the dummy pattern is removed to form a stacked platinum lower electrode. Therefore, a method of manufacturing a capacitor of a semiconductor device is disclosed, which can improve the capacitance characteristics of a BST capacitor.
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 전기도금(ElectroChemical Deposition) 플래티늄(Pt) 프로세스를 이용한 BST(Barium Strontium Titanate; (Ba, Sr)TiO3) 캐패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more particularly, to a method for manufacturing a BST (Barium Strontium Titanate; (Ba, Sr) TiO 3 ) capacitor using an electroplating (Pt) process.
일반적으로, 높은 유전특성을 나타내는 BST는 0.1㎛ 이하의 소자에서 캐패시터 유전물질로 사용하기 위해서는 셀당 요구되는 캐패시턴스를 얻기 위해 셀 면적 확보가 필요하다. 그런데 BST 캐패시터의 하부전극으로 사용하는 플래티늄(Pt)은 식각 특성이 매우 불량하여 0.5㎛ 이상의 높이로 수직(vertical) 식각하는 것이 거의 불가능하여, 이에 대한 대안으로 식각특성이 플래티늄보다 우수한 루테늄(Ru)을 사용하기 위한 연구가 진행되었다. 그러나 루테늄 전극은 누설전류 특성이 매우 열악한 단점이 있다. 그러므로 우수한 BST 특성을 확보할 수 있는 플래티늄 전극의 스택형 하부전극의 개발이 필요하다.In general, BST, which exhibits high dielectric properties, needs to secure a cell area in order to obtain a required capacitance per cell in order to use it as a capacitor dielectric material in an element of 0.1 μm or less. However, since platinum (Pt) used as a lower electrode of the BST capacitor is very poor in etching characteristics, it is almost impossible to etch it vertically to a height of 0.5 μm or more. As an alternative, ruthenium (Ru) having better etching characteristics than platinum A study was conducted to use. However, ruthenium electrode has the disadvantage of very poor leakage current characteristics. Therefore, it is necessary to develop a stack type lower electrode of the platinum electrode capable of securing excellent BST characteristics.
따라서, 본 발명은 식각 특성이 불량한 플래티늄의 식각 공정을 실시하지 않고 스택형 BST 캐패시터를 제조하여 셀당 요구되는 캐패시턴스를 만족하기 위한 면적을 확보할 수 있도록 한 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device in which a stack-type BST capacitor is manufactured without performing an etching process of platinum having poor etching characteristics to secure an area for satisfying a required capacitance per cell. There is this.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 하부구조가 형성된 기판 상에 층간 절연막 및 반사 방지막을 순차적으로 형성한 후, 콘택홀을 형성하는 단계; 상기 콘택홀을 포함하는 전체구조 상에 도프트 폴리실리콘층을 형성하고 상기 폴리실리콘층 일부를 식각하여 리세스부를 형성하는 단계; 상기 리세스부를 포함하는 전체구조 상에 티타늄 실리사이드층을 형성한 후, 전체구조 상에 확산 방지막을 형성하고 평탄화하여 캐패시터 플러그를 형성하는 단계; 상기 캐패시터 플러그를 포함하는 전체구조 상에 시드층을 형성하는 단계; 상기 시드층 상에 상기 캐패시터 플러그가 노출되는 더미 산화막 패턴을 형성하는 단계; 상기 노출된 캐패시터 플러그 상에 전기 도금 플래티늄막을 형성하고 이로 인하여 하부전극이 형성되는 단계; 상기 더미 산화막을 제거한 후, 노출된 상기 시드층을 제거하는 단계; 상기 하부전극을 포함하는 전체구조 상에 유전체막을 형성하는 단계; 및 상기 유전체막이 형성된 전체구조 상에 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device. Forming a doped polysilicon layer on the entire structure including the contact hole and etching a portion of the polysilicon layer to form a recess; Forming a titanium silicide layer on the entire structure including the recess, and then forming a diffusion barrier on the entire structure and planarizing to form a capacitor plug; Forming a seed layer on the entire structure including the capacitor plug; Forming a dummy oxide pattern on the seed layer to expose the capacitor plug; Forming an electroplating platinum film on the exposed capacitor plug, thereby forming a lower electrode; Removing the exposed seed layer after removing the dummy oxide layer; Forming a dielectric film on the entire structure including the lower electrode; And forming an upper electrode on the entire structure in which the dielectric film is formed.
도 1a 내지 1f는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1F are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 기판 12 : 층간 절연막11 substrate 12 interlayer insulating film
13 : 반사 방지막 14 : 폴리실리콘층13 antireflection film 14 polysilicon layer
15 : 티타늄 실리사이드층 16 : 확산 방지막15 titanium silicide layer 16 diffusion barrier film
17 : 시드층 18 : 더미 산화막17 seed layer 18 dummy oxide film
19 : 전기도금 플래티늄막 20 : CVD BST막19: electroplating platinum film 20: CVD BST film
21 : 상부전극21: upper electrode
본 발명은 식각특성이 열악한 플래티늄(Pt)의 식각 공정을 생략하여 스택형 BST 캐패시터를 용이하게 제조하고자 한다. 이를 위하여, 플래티늄 등을 이용하여 시드(Seed)층을 매우 얇게 형성하고, 시드층 상에 산화막이나 포토레지스트막을 이용하여 더미 패턴을 형성한 후, 전기도금(ElectroChemical Deposition)으로 플래티늄을 증착하고 더미 패턴을 제거하며, 이에 의해 스택형 플래티늄 하부전극이 형성되게 된다.The present invention is to easily manufacture a stacked BST capacitor by eliminating the etching process of platinum (Pt) having a poor etching characteristics. To this end, a seed layer is formed very thin using platinum, a dummy pattern is formed on the seed layer by using an oxide film or a photoresist film, and then platinum is deposited by electroplating, and the dummy pattern is deposited. In this way, the stacked platinum lower electrode is formed.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 1a 내지 도 1f는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1F are cross-sectional views of devices sequentially shown to explain a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 하부구조가 형성된 기판(11) 상에 기판(11)과 캐패시터와의 절연을 위하여 층간 절연막(12) 및 반사 방지막(13)을 순차적으로 형성한다. 여기에서, 반사 방지막(13)은 산화물과 식각 선택비가 우수한 실리콘 나이트라이드막을 이용하여 300 내지 1000Å의 두께로 형성한다.As shown in FIG. 1A, an interlayer insulating film 12 and an antireflection film 13 are sequentially formed to insulate the substrate 11 and the capacitor from the substrate 11 on which the substructure is formed. Here, the anti-reflection film 13 is formed to a thickness of 300 to 1000 Å using a silicon nitride film having excellent oxide and etch selectivity.
이후, 기판(11)과 캐패시터 사이의 수직 배선을 위한 콘택홀을 형성한 후, 화학기상증착법에 의해 도프트 폴리실리콘층(14)을 형성하고, 에치-백 공정에 의해 폴리실리콘층(14) 일부를 식각하여 리세스부를 형성한다. 여기에서, 폴리실리콘층(14)은 500 내지 3000Å의 두께로 형성하며, 에치-백 후의 리세스부는 500 내지 1500Å의 깊이를 갖도록 한다.Thereafter, after forming contact holes for vertical wiring between the substrate 11 and the capacitor, the doped polysilicon layer 14 is formed by chemical vapor deposition, and the polysilicon layer 14 is formed by an etch-back process. A portion is etched to form a recess. Here, the polysilicon layer 14 is formed to a thickness of 500 to 3000 kPa, and the recessed portion after the etch-back has a depth of 500 to 1500 kPa.
다음에, 전체구조 상에 캐패시터 플러그와 배리어 메탈간의 접촉저항을 감소시키기 위해 티타늄을 증착하고 열처리하여 티타늄 실리사이드층(15)을 형성한 후, 미반응 티타늄을 습식 식각 방법으로 제거한다. 여기에서, 티타늄은 100 내지 300Å의 두께로 형성하며, 열처리 공정은 급속 열처리 공정(RTP)으로 진행한다.Next, in order to reduce the contact resistance between the capacitor plug and the barrier metal on the entire structure, titanium is deposited and heat treated to form the titanium silicide layer 15, and then unreacted titanium is removed by a wet etching method. Here, titanium is formed to a thickness of 100 to 300 kPa, and the heat treatment process proceeds to a rapid heat treatment process (RTP).
이후, 전체구조 상에 확산 방지막(16)을 형성하고 화학적 기계적 연마(CMP) 공정에 의해 평탄화하므로써 캐패시터 플러그가 형성되게 된다. 여기에서, 확산 방지막(16)은 티타늄 나이트라이드(TiN), 티타늄 실리콘 나이트라이드(TiSiN), 티타늄 알루미늄 나이트라이드(TiAlN), 탄탈륨 실리콘 나이트라이드(TaSiN), 탄탈륨 알루미늄 나이트라이드(TaAlN)를 PVD 또는 CVD 방법에 의해 증착하여 형성한다.Thereafter, the capacitor plug is formed by forming the diffusion barrier 16 on the entire structure and planarizing by chemical mechanical polishing (CMP) process. Herein, the diffusion barrier 16 may include titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), and tantalum aluminum nitride (TaAlN). It forms by vapor deposition by the CVD method.
다음에, 시드(Seed)층(17)을 형성하고, 시드층(17) 상에 더미 산화막(18) 또는 포토레지스트막을 형성한 후 캐패시터 플러그가 노출되도록 더미 산화막(18) 또는 포토레지스트막을 패터닝한다. 여기에서, 시드층(17)은 루테늄(Ru), 플래티늄(Pt), 이리듐(Ir), 오스뮴(Os), 텅스텐(W), 몰리브덴(Mo), 코발트(Co), 니켈(Ni), 금(Au), 은(Ag) 등을 사용하여 50 내지 1000Å의 두께로 형성한다. 또한, 더미 산화막(18)은 PSG 또는 USG 산화막을 이용하여 5000 내지 15000Å의 두께로 형성한다.Next, a seed layer 17 is formed, a dummy oxide film 18 or a photoresist film is formed on the seed layer 17, and then the dummy oxide film 18 or the photoresist film is patterned so that the capacitor plug is exposed. . Here, the seed layer 17 is ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), etc., are used to form a thickness of 50 to 1000 mm. In addition, the dummy oxide film 18 is formed to a thickness of 5000-15000 kPa using PSG or USG oxide film.
도 1b에 도시된 바와 같이, 전기 도금법으로 플래티늄(19)을 도금하여 스택 구조를 형성한다. 여기에서, 전기도금 플래티늄막(19)은 3000 내지 10000Å의 두께로 형성한다. 또한, 전기도금 플래티늄막(19) 형성시에는 전류밀도의 범위가 0.1 내지 10㎃/㎠가 되도록 하고, 사용 전력은 DC, 펄스 또는 펄스 리버스(Pulse reverse) 방법을 이용하여 발생시켜 준다. 또한, 전기도금 플래티늄막(19) 대신 식각 특성이 우수한 루테늄(Ru), 플래티늄(Pt), 이리듐(Ir), 오스뮴(Os), 텅스텐(W), 몰리브덴(Mo), 코발트(Co), 니켈(Ni), 금(Au), 은(Ag) 등을 사용하는 것도 가능하다.As shown in FIG. 1B, the platinum 19 is plated by electroplating to form a stack structure. Here, the electroplating platinum film 19 is formed to a thickness of 3000 to 10000 kPa. When the electroplating platinum film 19 is formed, the current density ranges from 0.1 to 10 mA / cm 2, and the power used is generated by using a DC, pulse, or pulse reverse method. In addition, instead of the electroplating platinum film 19, ruthenium (Ru), platinum (Pt), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), and nickel having excellent etching characteristics It is also possible to use (Ni), gold (Au), silver (Ag) and the like.
도 1c에 도시된 바와 같이, 더미 산화막(18)을 제거한 후, 도 1d에 도시된 바와 같이, 하부전극 간의 절연을 위하여 블랭킷 식각 방법에 의하여 노출된 시드층(17)을 제거한다. 여기에서, 시드층(17)은 건식 식각 방법에 의해 제거한다.As shown in FIG. 1C, after removing the dummy oxide layer 18, as illustrated in FIG. 1D, the seed layer 17 exposed by the blanket etching method is removed to insulate the lower electrodes. Here, the seed layer 17 is removed by a dry etching method.
도 1e에 도시된 바와 같이, 전체구조 상에 유전체막으로서 CVD BST막(20)을 형성한다. CVD BST막(20)은 400 내지 600℃의 온도범위에서 150 내지 500Å의 두께로 BST를 증착한 후 500 내지 700℃ 온도범위 및 질소 가스 분위기에서 30 내지 180초 동안 급속 열처리(RTP)하여 결정화하여 형성한다.As shown in Fig. 1E, a CVD BST film 20 is formed as a dielectric film on the entire structure. The CVD BST film 20 is BST deposited at a thickness of 150 to 500 kPa in a temperature range of 400 to 600 ° C., and then crystallized by rapid heat treatment (RTP) for 30 to 180 seconds in a temperature range of 500 to 700 ° C. and a nitrogen gas atmosphere. Form.
도 1f에 도시된 바와 같이, 유전체막이 형성된 전체구조 상에 상부전극(21)을 형성한다. 여기에서, 상부전극은 플래티늄을 화학기상증착법으로 증착하여 형성한다.As shown in Fig. 1F, the upper electrode 21 is formed on the entire structure in which the dielectric film is formed. Here, the upper electrode is formed by depositing platinum by chemical vapor deposition.
상술한 바와 같이, 본 발명은 시드층을 형성한 후 전기도금 방법에 의해 플래티늄 하부전극을 형성하므로써, 식각 특성이 열악한 플래티늄의 식각공정을 생략하고도 스택형 BST 캐패시터를 용이하게 제조할 수 있다. 이에 따라, 0.1㎛ 이하의 소자에서 셀당 요구되는 캐패시턴스를 만족하기 위한 면적을 확보할 수 있으며, 캐패시터의 하부전극으로 플래티늄을 사용함에 따라 BST 캐패시터의 특성을 개선할 수 있게 된다. 또한, 화학기상증착법으로 플래티늄을 증착하는 경우에 비해 소오스로 사용되는 전해질 플래티늄 용액의 비용이 매우 저렴하여 공정 단가를 낮출 수 있고, 플래티늄 식각 공정을 생략할 수 있기 때문에 공정 단계를 최소화할 수 있는 효과가 있다.As described above, in the present invention, since the lower layer of the platinum is formed by the electroplating method after forming the seed layer, the stacked BST capacitor can be easily manufactured without the etching process of platinum having poor etching characteristics. Accordingly, it is possible to secure an area for satisfying the capacitance required per cell in an element of 0.1 μm or less, and to improve the characteristics of the BST capacitor by using platinum as the lower electrode of the capacitor. In addition, compared to the case of depositing platinum by chemical vapor deposition, the cost of the electrolyte platinum solution used as the source is very low, and thus, the process cost can be reduced, and the etching process of the platinum can be omitted, thereby minimizing the process step. There is.
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| KR1019990062959A KR100342821B1 (en) | 1999-12-27 | 1999-12-27 | Method of manufacturing a capacitor in a semiconductor device |
| US09/735,528 US6451666B2 (en) | 1999-12-27 | 2000-12-14 | Method for forming a lower electrode by using an electroplating method |
| DE10065350A DE10065350B4 (en) | 1999-12-27 | 2000-12-27 | A method of manufacturing a semiconductor device with a capacitor using an electroplating method |
| JP2000396570A JP2001210806A (en) | 1999-12-27 | 2000-12-27 | Method for forming lower electrode by utilizing electroplating |
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| KR100646947B1 (en) * | 2000-06-29 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100676534B1 (en) * | 2000-06-28 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
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| KR100346833B1 (en) * | 1999-10-14 | 2002-08-03 | 삼성전자 주식회사 | Method for manufacturing capacitor of semiconductor memory device using electroplating method |
| KR100331570B1 (en) * | 2000-06-13 | 2002-04-06 | 윤종용 | Method for manufacturing capacitor of semiconductor memory device using electroplating method |
| KR100448852B1 (en) * | 2001-12-26 | 2004-09-18 | 주식회사 하이닉스반도체 | Method for manufacturing a capacitor of semiconductor device |
| KR100444300B1 (en) * | 2001-12-26 | 2004-08-16 | 주식회사 하이닉스반도체 | Capacitor of semiconductor device and method for manufacturing the same |
| KR100443361B1 (en) * | 2002-04-26 | 2004-08-09 | 주식회사 하이닉스반도체 | Method for fabricating capacitor using electro chemical deposition |
| KR100428658B1 (en) * | 2002-04-26 | 2004-04-28 | 주식회사 하이닉스반도체 | Method for fabricating capacitor using electro chemical deposition and wet etching |
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| KR100676534B1 (en) * | 2000-06-28 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
| KR100646947B1 (en) * | 2000-06-29 | 2006-11-17 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
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