KR100414869B1 - Method for fabricating capacitor - Google Patents

Abstract

The present invention is to provide a method of manufacturing a capacitor suitable for preventing the lowering of the dielectric capacity and the electrical degradation due to the subsequent thermal process when the lower electrode is etched back to etch the lower electrode by the electroplating method at the same time, Forming a Ru / TiN seed layer stacked in the order of ruthenium and titanium nitride on the step; forming a sacrificial film on the Ru / TiN seed layer; selectively etching the sacrificial film to form the Ru / TiN seed layer Forming a recess exposing a predetermined surface, depositing a platinum lower electrode in the recess by an electrochemical deposition method using the Ru / TiN seed layer in the recess as a seed layer, and selectively removing the sacrificial film. Etching the Ru / TiN seed layer exposed after removing the sacrificial layer to insulate the platinum lower electrode; Through the process steps it is achieved by Po, and forming a dielectric film, an upper electrode on the platinum lower electrode in order to modify the Ru / TiN seeding layer by a single RuTiN seed layer.

Description

Manufacturing method of a capacitor {METHOD FOR FABRICATING CAPACITOR}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.

The capacitance C of the capacitor in the semiconductor device is (ε: dielectric constant, A: surface area, d: dielectric thickness), which is proportional to the surface area of the storage node (or lower electrode) and the dielectric constant of the dielectric material.

Therefore, in the manufacturing process of semiconductor devices that are miniaturized, in order to secure a certain amount of capacitance for proper operation of the semiconductor devices, the shape of the storage node is formed in a three-dimensional structure to increase the surface area of the storage node or to have a high dielectric constant. A method of securing capacitance by using a high dielectric material such as BST [(Ba, Sr) TiO ₃ ] has been studied.

However, the formation of a three-dimensional storage node requires a complicated process, which leads to a decrease in yield due to an increase in manufacturing costs and an increase in the process, and the use of BST high dielectric materials makes it difficult to strictly maintain oxygen stoichiometry. There is a problem that the leakage current characteristics deteriorate.

In the case of BST capacitors, noble metals such as platinum and iridium, which are highly resistant to oxidation, should be used as storage nodes. Since such noble metals are very stable and difficult to etch, the vertical profile is mainly performed by etching by sputtering. There is a problem that is difficult to obtain.

In order to solve this problem, a method of forming a capacitor pattern using an oxide film, depositing a noble metal using an Electro Chemical Deposition (ECD), and then etching back was studied.

1A to 1C illustrate a method of manufacturing a capacitor according to the prior art.

As shown in FIG. 1A, a transistor manufacturing process is performed on a semiconductor substrate 11. First, a word line (not shown) and a source / drain 12 are formed on the semiconductor substrate 11, and then a semiconductor substrate is formed. An interlayer insulating film 13 for insulating the semiconductor substrate and the capacitor is deposited on (11). Then, the interlayer insulating film 13 and Si ₃ N ₄ 14 having high etching selectivity are deposited on the interlayer insulating film 13.

Next, Si ₃ N ₄ (14) and the interlayer insulating film 13 are selectively etched to form contact holes for vertical wiring between the source / drain 12 and the capacitor, and polysilicon is formed on the entire surface including the contact holes. Deposit.

Subsequently, the polysilicon is etched back to recess the polysilicon plug 15 in the contact hole.

Next, in order to lower the contact resistance of the polysilicon plug 15 and the subsequent diffusion barrier layer on the front surface, titanium (Ti) is deposited, and a rapid thermal process (RTP) is performed on the surface of the polysilicon plug 15. Ti-silicide) 16 is formed.

Subsequently, titanium nitride (TiN) 17 is deposited on the titanium silicide 16 as a diffusion barrier film, and then chemically mechanically polished until the surface of Si ₃ N ₄ 14 is exposed to titanium nitride 17 Level). At this time, the titanium nitride 17 serves as a diffusion barrier of oxygen from the storage node to the polysilicon plug 15 or the semiconductor substrate 11 in a subsequent heat treatment process.

Subsequently, the platinum_seed layer 18 is deposited on the entire surface of the resultant product in which the stack structure of the polysilicon plug 15, the titanium silicide 16, and the titanium nitride 17 is embedded, and then the platinum_seed layer 18 The sacrificial film 19 is deposited on the.

Here, the platinum_seed layer 18 is a seed layer for forming the storage node by electrochemical deposition (ECD), which is a type of electroplating method, and is formed by physical vapor deposition (PVD).

Next, after the photoresist is coated on the sacrificial layer 19, the photoresist is patterned by exposure and development to form a storage node mask (not shown), and then the dry sacrificial layer 19 is dry-etched with the storage node mask to form platinum. A region (hereinafter, abbreviated as “concave portion”) on which the bottom electrode exposing the surface of the seed layer 18 is to be formed is formed.

As shown in FIG. 1B, the platinum_lower electrode (hereinafter referred to as "electrode deposition") on the exposed platinum_seed layer 18 in the recess 20 by applying a bias to the platinum_seed layer 18. 20 is abbreviated as 'ECD-Pt'.

Next, the sacrificial film 19 is etched to expose the surface of the SiON film 14 to expose the platinum_seed layer 18 on which the ECD-Pt 19 is not deposited.

As shown in FIG. 1C, after the sacrificial layer 19 is removed, the exposed platinum_seed layer 18 is dry etched back and completely removed. At this time, since the platinum seed layer 18 is separated from each other, the lower electrodes between adjacent cells, that is, the ECD-Pt 20, are insulated from each other.

In the above-described conventional technology, platinum is not directly etched when the platinum_lower electrode is formed, thereby reducing the burden on platinum etching.

However, in the related art, after dry etching back to separate the platinum_seed layer 18, the ECD-Pt 20 is simultaneously etched to lower the height of the ECD-Pt 20 (A).

As a result, the area of the lower electrode is reduced, so that the dielectric capacity of the capacitor is reduced, which in turn reduces the efficiency of the capacitor.

In addition, the by-product (B) of the platinum_seed layer after etch back is redeposited on the sidewall of the ECD-Pt to cause a capacitor short circuit.

On the other hand, the use of a ruthenium seed layer in addition to the platinum_seed layer has the advantage that the etchback process can be easily carried out without loss of ECD-Pt and redeposition of etching by-products. Easily diffuses to the surface through grain boundaries of ECD-Pt, forms a Pt-Ru alloy, and easily oxidizes during subsequent BST deposition and thermal treatment to degrade electrical properties.

The present invention has been made to solve the above-mentioned problems of the prior art, and prevents the lowering of the dielectric capacity due to the simultaneous etching of the lower electrode during the etch back to isolate the lower electrode by the electroplating method and electrical degradation due to subsequent thermal process. It is an object of the present invention to provide a method for manufacturing a capacitor suitable for

1A to 1C are cross-sectional views illustrating a method of manufacturing a capacitor by an ECD method according to the prior art;

2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor by an ECD method according to an embodiment of the present invention;

3A to 3D are cross-sectional views illustrating a method of manufacturing a capacitor by an ECD method according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: source / drain

33: interlayer insulating film 34: Si ₃ N ₄

35: polysilicon plug 36: titanium silicide

37: titanium nitride 38: Ru / TiN seed layer

39: sacrificial film 40: ECD-Pt

41: BST 42: Upper electrode

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, which comprises forming a Ru / TiN seed layer on a semiconductor substrate in the order of ruthenium and titanium nitride, and forming a sacrificial layer on the Ru / TiN seed layer. Selectively etching the sacrificial layer to form a recess exposing a predetermined surface of the Ru / TiN seed layer; using the Ru / TiN seed layer in the recess as a seed layer, a platinum lower electrode in the recess Depositing an electrochemical vapor deposition method, selectively removing the sacrificial layer, and etching back the Ru / TiN seed layer exposed after removing the sacrificial layer to insulate the platinum lower electrode, and the Ru / TiN through heat treatment. Modifying the seed layer with a single RuTiN seed layer, and sequentially forming a dielectric film and an upper electrode on the platinum lower electrode. It characterized by true.

In addition, the method of manufacturing a capacitor of the present invention comprises the steps of forming a ruthenium film on a semiconductor substrate, forming a titanium nitride on the ruthenium film, forming a sacrificial film on the titanium nitride, selectively etching the sacrificial film Forming a recess exposing a predetermined surface of the titanium nitride; depositing a platinum lower electrode by electrochemical deposition in the recess using the titanium nitride in the recess as a seed layer; Removing the sacrificial layer, etching back the titanium nitride to expose the platinum lower electrode, and reacting the ruthenium with titanium nitride to form RuTiN through heat treatment. It features.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D illustrate a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 2A, a transistor manufacturing process is performed on a semiconductor substrate 31. First, a word line (not shown) and a source / drain 32 are formed on the semiconductor substrate 31, and then the semiconductor substrate is formed. SiO ₂ is deposited on the 31 as the interlayer insulating film 33 for insulating the semiconductor substrate 31 and the capacitor. Then, Si ₃ N ₄ (34) having a high etching selectivity and an interlayer insulating film 33 are deposited on the interlayer insulating film 33, where Si ₃ N ₄ (34) is a lower interlayer insulating film during subsequent seed layer etching back ( 33) is an etch barrier film that prevents damage.

At this time, the interlayer insulating film 33 and Si ₃ N ₄ 34 are deposited to a total thickness of 300 mW to 1000 mW.

Next, the Si ₃ N ₄ 34 and the interlayer dielectric layer 33 are selectively etched to form contact holes for vertical wiring between the source / drain 32 and the capacitor, and polysilicon is formed on the entire surface including the contact holes. Deposit.

Subsequently, the polysilicon is etched back to recess the polysilicon plug 35 in the contact hole at 500 1 to 1500 Å, and then titanium (Ti) to reduce the contact resistance between the polysilicon plug 35 and the subsequent diffusion barrier film on the front surface. Is deposited to a thickness of 100 kPa to 300 kPa and subjected to rapid heat treatment (RTP) to form titanium silicide (Ti-silicide) 36 on the surface of the polysilicon plug 35.

Then, by removing the unreacted titanium by wet, depositing titanium nitride (37) as a diffusion barrier on the titanium silicide (36), chemical mechanical polishing until the surface of Si ₃ N ₄ (34) is exposed to titanium Nitride 37 is planarized.

At this time, the titanium nitride 37 serves as a diffusion barrier of oxygen from the lower electrode to the polysilicon plug 35 or the semiconductor substrate 31 in the subsequent heat treatment process.

Here, any one of TiSiN, TiAlN, TaSiN or TaAlN is used as the diffusion barrier in addition to the titanium nitride 37, and the diffusion barriers are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Subsequently, a seed layer of a ruthenium / titanium nitride double structure (hereinafter, referred to as a 'Ru / TiN seed layer) is formed on the entire surface of the resultant product in which the polysilicon plug 35, the titanium silicide 36, and the titanium nitride 37 are stacked. 38 is deposited, and then a sacrificial film 39 is deposited on the Ru / TiN seed layer 38.

Here, the Ru / TiN seed layer 38 is a seed layer for forming platinum, which is a lower electrode, by electrochemical deposition (ECD), which is a kind of electroplating method, and has a thickness of Ru (50 mV to 500 mV) / TiN (50 mV to 500 mV). Is deposited.

The sacrificial film 39 is a photosensitive film or is deposited to a thickness of 5000 kPa to 10,000 kPa as an oxide film by chemical vapor deposition.

Next, after the photoresist is coated on the sacrificial layer 39, the photoresist is patterned by exposure and development to form a storage node mask (not shown), and then the dry sacrificial layer 39 is dry-etched with the storage node mask to form Ru. A region (hereinafter abbreviated as 'concave portion') on which the bottom electrode to which the surface of the / TiN seed layer 38 is exposed is formed is formed.

As shown in FIG. 2B, after pre-cleaning, the lower electrode ECD-Pt 40 is deposited on the exposed Ru / TiN seed layer 38 in the recess by electrochemical deposition. Deposition is carried out in a form in which the recess is embedded at a predetermined depth.

At this time, the current density used during deposition of the ECD-Pt 40 is in the range of 0.1 to 10 mA / cm ² , and power is applied by direct current (DC), pulses, or pulse reverses.

Next, the sacrificial film 39 is wet-dipped out to expose the surface of the Si ₃ N ₄ 34 to reveal the Ru / TiN seed layer 38 on which the ECD-Pt 40 is not deposited. . At this time, during wet dip-out of the sacrificial film 39, HF or HF / NH ₄ F mixed solution is used.

As shown in FIG. 2C, the Ru / TiN seed layer 38 exposed after the sacrificial layer 39 is removed by the blanket etchback for the lower electrode insulation is removed, and then ammonia (NH ₃ ) gas or an ammonia plasma atmosphere is removed. The Ru / TiN seed layer 38 is modified to a single RuTiN 41 by heat treatment at 400 ° C. to 800 ° C. for 1 to 60 minutes.

At this time, the blanket etch back Ru / TiN seed layer 38 prevents the loss of the ECD-Pt 40 because the etch back process is easier than the platinum or iridium seed layer. In addition, heat treatment in an ammonia gas or an ammonia plasma atmosphere modifies the RuTiN 41 to form an ECD-Pt laminate having excellent thermal stability.

As shown in FIG. 2D, the BST 42 and the upper electrode 43 are deposited on the entire surface along the exposed ECD-Pt 40 after the blanket etch back.

Here, the BST 42 is deposited by a chemical vapor deposition (CVD) at a temperature of 300 ° C. to 500 ° C. to a thickness of 150 ° C. to 500 ° C., followed by rapid heat treatment for 30 seconds to 300 seconds in a nitrogen atmosphere of 500 ° C. to 700 ° C. RTP) to crystallize.

At this time, since ECD-Pt 39 and RuTiN 41 have excellent thermal stability, the heat treatment temperature for crystallization of BST 42 can be increased. This reduces the effective oxide thickness (T _ox ) of the capacitor.

Then, platinum is deposited on the upper electrode 43 by chemical vapor deposition.

3A to 3D are cross-sectional views illustrating a method of manufacturing a capacitor according to another embodiment of the present invention.

As shown in FIG. 3A, a transistor fabrication process is performed on a semiconductor substrate 51. First, a word line (not shown) and a source / drain 52 are formed on the semiconductor substrate 51, and then the semiconductor substrate is formed. SiO ₂ is deposited on the 51 as the interlayer insulating film 53 for insulating the semiconductor substrate 51 and the capacitor. Then, Si ₃ N ₄ (54) having a high etching selectivity and an interlayer insulating film 53 is deposited on the interlayer insulating film 53, where Si ₃ N ₄ (54) is a lower interlayer insulating film at the time of subsequent seed layer etching back ( 53) is an etch barrier film that prevents damage.

At this time, the interlayer insulating film 53 and Si ₃ N ₄ 54 are deposited to a total thickness of 300 mW to 1000 mW.

Next, the Si ₃ N ₄ 54 and the interlayer dielectric layer 53 are selectively etched to form a contact hole for vertical wiring between the source / drain 52 and the capacitor, and polysilicon is formed on the entire surface including the contact hole. Deposit.

Subsequently, the polysilicon is etched back to recess the polysilicon plug 55 in the contact hole at 500 1 to 1500 Å, and then titanium (Ti) to lower the contact resistance of the polysilicon plug 55 and the subsequent diffusion barrier film on the front surface. Is deposited to a thickness of 100 kPa to 300 kPa and subjected to rapid heat treatment (RTP) to form titanium silicide (Ti-silicide) 56 on the surface of the polysilicon plug 55.

After the unreacted titanium is wet, the ruthenium (57) is deposited on the titanium silicide (56) as a diffusion barrier, followed by chemical mechanical polishing until the surface of the Si ₃ N ₄ (54) is exposed. Level). At this time, the ruthenium 57 serves as a diffusion barrier of oxygen from the lower electrode to the polysilicon plug 55 or the semiconductor substrate 51 in a subsequent heat treatment process.

Here, ruthenium 57 is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Subsequently, a titanium nitride seed layer (hereinafter referred to as a 'TiN seed layer') 58 is formed on the entire surface of the resultant product in which the polysilicon plug 55, the titanium silicide 56, and the ruthenium 57 are stacked. After the deposition, the sacrificial film 59 is deposited on the TiN seed layer 58.

Here, the TiN seed layer 58 is deposited as a seed layer for forming platinum, which is a lower electrode, by electrochemical deposition (ECD), a kind of electroplating method, having a thickness of 50 kPa to 300 kPa.

The sacrificial film 59 is a photosensitive film or is deposited to a thickness of 5000 kPa to 10,000 kPa as an oxide film by chemical vapor deposition.

Next, after the photoresist is coated on the sacrificial layer 59, the photoresist layer is patterned by exposure and development to form a storage node mask (not shown), followed by dry etching the sacrificial layer 59 with the storage node mask to form TiN. A recess is formed to form a lower electrode on which the surface of the seed layer 58 is exposed.

As shown in FIG. 3B, after pre-cleaning, the ECD-Pt 60, which is a lower electrode, is deposited on the exposed TiN seed layer 58 in the recess by electrochemical deposition. It is deposited to a thickness to embed it to a predetermined depth.

At this time, the current density used in the deposition of the ECD-Pt 60 is in the range of 0.1 to 10 mA / cm ² , and power is applied by direct current (DC), pulses, or pulse reverses.

Next, the sacrificial film 59 is wet-dipped out to expose the surface of the Si ₃ N ₄ 54 to expose the TiN seed layer 38 on which the ECD-Pt 60 is not deposited. At this time, during wet dip-out of the sacrificial film 59, HF or HF / NH ₄ F mixed solution is used.

As shown in FIG. 3C, next, the TiN seed layer 58 exposed after the removal of the sacrificial layer 59 by the blanket etch back is removed for insulation between the lower electrodes, and then ammonia (NH ₃ ) gas or an ammonia plasma atmosphere is removed. 1 to 60 minutes at 400 ℃ to 800 ℃ of the ruthenium (57) and the TiN seed layer 58 is reacted to modify the RuTiN (61).

At this time, since the TiN seed layer 58 during the blanket etch back is easier to etch back than the platinum or iridium seed layer, the loss of the ECD-Pt 60 is prevented. In addition, since the ruthenium 57 and the TiN seed layer 58 are reacted with each other by heat treatment in an ammonia atmosphere to modify the RuTiN 61, an ECD-Pt laminate having excellent thermal stability is formed.

As shown in FIG. 3D, the BST 62 and the upper electrode 63 are deposited on the entire surface along the exposed ECD-Pt 60 after the blanket etch back.

Here, the BST 62 is deposited by a chemical vapor deposition (CVD) at a temperature of 300 ° C. to 500 ° C. to a thickness of 150 ° C. to 500 ° C., followed by rapid thermal treatment for 30 seconds to 300 seconds in a nitrogen atmosphere of 500 ° C. to 700 ° C. RTP) to crystallize.

At this time, since ECD-Pt 59 and RuTiN 61 have excellent thermal stability, the heat treatment temperature for crystallization of BST 62 can be increased. This reduces the effective oxide thickness (T _ox ) of the capacitor.

Then, platinum is deposited on the upper electrode 63 by chemical vapor deposition.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention uses the electroplating method, so that the lower electrode can be formed by stacking rather than etching, and since the Ru / TiN seed layer is used, the lower electrode can be easily separated.

In addition, since ECD-Pt and RuTiN are thermally stable, the effective oxide film thickness can be reduced through the subsequent thermal process temperature increase of BST, and thus BST capacitors using platinum electrodes can be stably implemented.

Claims (11)

In the manufacturing method of a capacitor, Forming a Ru / TiN seed layer deposited on the semiconductor substrate in the order of ruthenium and titanium nitride; Forming a sacrificial layer on the Ru / TiN seed layer; Selectively etching the sacrificial layer to form a recess to expose a predetermined surface of the Ru / TiN seed layer; Depositing a platinum lower electrode in the recess by electrochemical deposition using the Ru / TiN seed layer in the recess as a seed layer; Selectively removing the sacrificial layer; Etching the Ru / TiN seed layer exposed after removing the sacrificial layer to insulate the platinum lower electrode; Modifying the Ru / TiN seed layer into a single RuTiN seed layer through heat treatment; And Sequentially forming a dielectric film and an upper electrode on the platinum lower electrode Method for producing a capacitor, characterized in that comprises a. The method of claim 1, Depositing the platinum lower electrode, A method for manufacturing a capacitor, comprising an electrochemical vapor deposition method, applying a current density of 0.1 to 10 mA / cm ² and power selected from DC, pulse, or pulse reverse. The method of claim 1, In the forming of the Ru / TiN seed layer, The Ru / TiN is a capacitor manufacturing method, characterized in that deposited to a thickness of 50 ~ 500Å / 50Å ~ 500Å. The method of claim 1, Modifying the Ru / TiN seed layer into a single RuTiN seed layer, A process for producing a capacitor, characterized in that it is carried out for 1 minute to 60 minutes at 400 ℃ to 800 ℃ in ammonia gas or ammonia plasma atmosphere. The method of claim 1, The sacrificial film is any one selected from a photosensitive film or a CVD oxide film, the method of manufacturing a capacitor, characterized in that the deposition to a thickness of 5000 ~ 20000 Å. The method of claim 1, Selectively removing the sacrificial layer, Method for producing a capacitor, characterized in that made using either HF or HF / NH ₄ F mixed solution. The method of claim 1, Forming the dielectric film, The dielectric film includes BST, After depositing the BST to a thickness of 150Å to 500Å by chemical vapor deposition at a temperature of 300 ° C to 500 ° C, rapid heat treatment for 30 seconds to 300 seconds in a nitrogen atmosphere of 500 ° C to 700 ° C to crystallize the BST. The manufacturing method of a capacitor. In the manufacturing method of a capacitor, Forming a ruthenium film on the semiconductor substrate; Forming titanium nitride on the ruthenium film; Forming a sacrificial film on the titanium nitride; Selectively etching the sacrificial layer to form a recess exposing a surface of the titanium nitride; Depositing a platinum lower electrode in the recess by electrochemical deposition using the titanium nitride in the recess as a seed layer; Selectively removing the sacrificial layer; Insulating the platinum lower electrode by etching back the titanium nitride exposed after removing the sacrificial layer; And Reacting ruthenium and titanium nitride through heat treatment to form RuTiN Method for producing a capacitor, characterized in that comprises a. The method of claim 8, The titanium nitride is a method for producing a capacitor, characterized in that deposited to a thickness of 50 ~ 300Å. The method of claim 8, The heat treatment is, A process for producing a capacitor, characterized in that it is carried out for 1 minute to 60 minutes at 400 ℃ to 800 ℃ in ammonia gas or ammonia plasma atmosphere. The method of claim 8, The ruthenium film is a method of manufacturing a capacitor, characterized in that deposited by any one of chemical vapor deposition or physical vapor deposition method.