KR19990016233A - Capacitor Electrode and Capacitor Formation Method of Semiconductor Device Having High-k Dielectric Film - Google Patents

Abstract

Disclosed are a capacitor electrode employing a high dielectric constant material as a dielectric film and a method of manufacturing a capacitor using the electrode. The capacitor electrode of the semiconductor device according to the present invention and a method of manufacturing a capacitor using the same are formed by selecting one of a material which is well etched and easy to form into a stack, for example, Ru, RuO 2, Ti, TiN, and a combination of metals. A first metal layer and a second metal layer 112 ', 212' formed using a material selected from a metal selected from among Pt, Ir, and IrO2 having excellent leakage current characteristics due to poor etching but poor oxidation. It characterized by forming. The first metal layer is formed under the second metal layer, and is formed thicker than the second metal layer. Therefore, an etch inclination may be prevented when the lower electrode is formed, thereby reducing the cross-sectional area of the lower electrode of the capacitor, and the height of the capacitor may be increased, thereby increasing capacitance in the capacitor of the semiconductor device using the high-k material.

Description

Capacitor Electrode and Capacitor Formation Method of Semiconductor Device Having High-k Dielectric Film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a capacitor electrode employing a high dielectric constant material as a dielectric film and a method of manufacturing a capacitor using the electrode.

As semiconductor memory devices are increasingly integrated, there is an increasing need for capacitors that can be formed in a small area while maintaining high capacitance in semiconductor memory devices such as dynamic random access memory (DRAM). To meet this need, capacitors with complex process steps, such as trenches or cylinders, have emerged. However, the above-described trench-type or cylindrical-type capacitors show a limit in realizing high capacitance and high integration required in highly integrated semiconductor memory devices.

Recently, to solve this problem, high dielectric constant materials such as barium strontium titanate (BST), PZT, and Ta ₂ O ₅ , which have a dielectric constant several hundred times higher than conventional dielectrics, are used as a dielectric for capacitors. A method of forming a capacitor in a stack type is becoming common. When the capacitor is formed using the high-k material, conductive materials that can be used as the upper and lower electrodes of the capacitor include ruthenium (Ru), ruthenium dioxide (RuO ₂ ), and platinum (Pt). Here, although ruthenium (Ru) and ruthenium dioxide (RuO ₂ ) are easier to etch than the platinum film, there is a problem that the leakage current characteristic is 10 to 100 times that of platinum.

On the other hand, the platinum film is a stable material that does not react to the oxidation reaction on the surface of the dielectric electrode generated during the high temperature treatment of the BST dielectric film, and is a material having excellent electrical conductivity and does not cause oxidation reaction on the surface of the platinum film during the process. Compared with other types of conductive films, the leakage current generated in the dielectric electrodes of the capacitors has a small characteristic. However, when the upper and lower electrodes of the capacitor are to be formed using platinum, patterning using dry etching is very difficult. This is because platinum is a non-reactive metal, making it difficult to react with other chemicals. Generally, the platinum film is etched by using ion sputtering. At this time, the etching residue is generated, and the etching slope of the platinum film is smoothed so that the lower electrode formed of platinum is high. In this case, a problem arises that patterning is difficult due to a bridge.

As described above, the prior art using a platinum film as a lower electrode of a capacitor is disclosed in Texas Instruments as US 5,489,548 (Title: Method of forming high-dielectric constant material electrodes comprising side wall spacers, Date of Patent: Feb. 6, 1996). Has been patented.

1 is a cross-sectional view when a capacitor electrode of a semiconductor device is formed using a high dielectric constant material according to the prior art.

Referring to FIG. 1, patterning is performed on the semiconductor substrate 30 via an insulating layer 32 to form contact holes for capacitor formation. The contact hole is completely filled with a plug 34 made of polysilicon doped with impurities. Subsequently, a capacitor using a high dielectric constant material is formed by forming a barrier layer 36 made of TiN connected to the plug 34, a lower electrode 42 containing platinum, and a high dielectric film 44 such as BST and an upper electrode. Complete the formation of. Here, reference numeral 40 denotes an insulating film spacer made of an oxide film formed for the purpose of preventing oxidation of the barrier layer 36 and deterioration of the characteristics of the capacitor.

However, the problem in the above-described prior art is that when the platinum film used as the lower electrode 42 is etched, the upper edge of the platinum film is eroded to have a slope. Therefore, the lower electrode 42 which is inclinedly etched has a problem of reducing the cross-sectional area of the capacitor electrode, thereby reducing the capacitance characteristics, and increasing the capacitance by increasing the height of the lower electrode.

The technical problem to be achieved by the present invention is to form a capacitor electrode of two metal layers containing platinum and ruthenium to facilitate etching, improve the etch gradient to increase the cross-sectional area of the electrode, and to form a higher height of the lower electrode To provide a capacitor electrode of a semiconductor device using a high dielectric constant material.

Another object of the present invention is to provide a method of forming a capacitor of a semiconductor device using the capacitor electrode.

1 is a cross-sectional view when a capacitor electrode of a semiconductor device is formed using a high dielectric constant material according to the prior art.

2 to 10 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device using a high dielectric constant material according to the first embodiment of the present invention.

11 to 19 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device using a high dielectric constant material according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100, 200: semiconductor substrate, 102, 202: interlayer insulating film,

104, 204: plug 106, 206 ': Ohmic layer,

108, 208 ': barrier layer,

110; 210 ': first metal layer, 112', 212 ': second metal layer,

114; 214 ': mask layer, 116, 216: photoresist pattern,

118 ', 218': metal spacer, 120, 220: high dielectric film,

122, 222: upper electrode, 232: insulating film spacer

In order to achieve the above technical problem, the present invention provides a capacitor electrode of a semiconductor device using a high dielectric constant material as a dielectric film, wherein the capacitor electrode is well etched to form a first metal layer that can be stacked. And a second metal layer having excellent etching current but excellent leakage current characteristics, and a capacitor electrode of a semiconductor device using a high dielectric constant material.

According to a preferred embodiment of the present invention, the first metal layer is suitably formed of one material selected from Ru, RuO2, Ti, TiN and a combination of metals, and the second metal layer is one selected from Pt, Ir and IrO2 It is suitable to be formed using the material of. In addition, the first metal layer is located below the second metal layer, and in order to increase the size of the electrode to improve the capacitance, it is preferable to form a thicker thickness than the second metal layer.

In order to achieve the above technical problem, the present invention provides a first step of forming a plug in a semiconductor substrate in which a contact hole for forming a capacitor is formed, and an ohmic layer on the plug. A second step of stacking and planarizing a barrier layer, a third step of sequentially stacking a first metal layer for a capacitor electrode and a metal layer for a second electrode on a front surface of the planarized semiconductor substrate, and a mask on the resultant A fourth step of forming a layer, a fifth step of patterning first and second metal layers using the mask layer, a removal of the mask layer and formation of metal spacers on both sidewalls of the first and second metal layers And a seventh step of stacking a high dielectric film and an upper electrode on the resultant product on which the metal layer spacer is formed, and patterning the high dielectric film and the upper electrode to form a capacitor. Provides a capacitor formed in a semiconductor device using a high-dielectric material, it characterized in that it comprises an eighth step of sex.

According to a preferred embodiment of the present invention, it is preferable that the plug of the first step is formed so as not to completely fill the contact hole, and the planarization of the second step is performed to have the same height as the insulating film on which the contact hole is formed.

In addition, the first metal layer is formed by selecting one of Ru, RuO2, Ti, TiN and a combination of metals, and the second metal layer is formed using one metal from Pt, Ir and IrO2, and the first The metal layer is preferably thicker than the second metal layer so as to increase the area of the lower electrode.

Preferably, the metal spacer of the sixth step is formed using one metal from Pt, Ir, and IrO2, which is the same as the second metal layer, and the high dielectric film of the seventh step is one selected from BST, PZT, and Ta2O5. It is suitable to form using materials.

In order to achieve the above technical problem, the present invention provides a first step of forming a plug in a semiconductor substrate in which a contact hole for forming a capacitor is formed, and an ohmic layer on a front surface of the semiconductor substrate in which the plug is formed. A second step of sequentially laminating an ohmic layer and a barrier layer, a third step of sequentially laminating a first metal layer and a second metal layer for a capacitor electrode on the barrier layer, and on the second metal layer A fourth step of forming a mask layer to form a lower electrode by patterning a lower second metal layer, a first metal layer, a barrier layer, and an ohmic layer; and a fifth step of forming insulating film spacers on both sidewalls of the barrier layer and the ohmic layer. And a sixth step of forming metal spacers on both side walls of the first metal layer and the second metal layer, and laminating a high dielectric film and an upper electrode on the resultant product on which the metal spacer is formed. Provides a seventh stage, a capacitor forming a semiconductor device using a high dielectric constant material, comprising an eighth step of forming a capacitor by patterning the high-dielectric film and an upper electrode.

According to a preferred embodiment of the present invention, the plug of the first step is formed to completely fill the contact hole, the first metal layer of the third step is selected from Ru, RuO2, Ti, TiN and a combination of metals And the second metal layer is formed using one metal from Pt, Ir, and IrO2, and the first metal layer is formed to have a thicker thickness than the second metal layer.

In addition, the insulating film spacer of the fifth step is formed using SOG or TEOS, and the metal spacer of the sixth step is formed using one metal of Pt, Ir and IrO2 having the same film quality as the second metal layer, The seven-step high dielectric film is suitable to be formed using one material selected from BST, PZT, and Ta2O5.

According to the present invention, when the lower electrode is formed, an etch gradient is prevented to reduce the cross-sectional area of the lower electrode of the capacitor, and the height of the capacitor can be increased to increase the capacitance in the capacitor of the semiconductor device using the high dielectric constant material. Can be.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a structure and a feature of a capacitor electrode of a semiconductor device using a high dielectric constant material according to the present invention will be described with reference to FIGS. 10 and 19.

10 and 19, the structure of the capacitor electrode of the semiconductor device according to the present invention is ① in a well-etched material that is easy to form a stack, such as Ru, RuO2, Ti, TiN and a metal combination thereof A first metal layer 110 'or 210' formed by selecting one, and a second metal layer formed by using a material selected from a metal selected from the group consisting of Pt, Ir, and IrO2, which is not well etched but has excellent leakage current characteristics. 112 ', 212'). The first metal layers 110 ′ and 210 ′ are formed under the second metal layers 112 ′ and 212 ′, and are thicker than the second metal layers 112 ′ and 212 ′.

Therefore, when etching the capacitor lower electrode composed of the composite film of the first metal layer 110 ′, 210 ′ and the second metal layer 112 ′, 212 ′, the lower electrode surface is disposed on the second metal layer 112 ′, 212 ′. By improving leakage current characteristics, the first metal layers 110 ′ and 210 ′ constituting most of the lower electrodes are easily etched, thereby increasing the lower electrode due to an etching slope problem or the like. The problem of being unable to form can be limited to increase the cross-sectional area.

Next, a capacitor forming method of a semiconductor device using the capacitor electrode having the high dielectric constant material will be described with reference to FIGS. 2 and 19.

(First embodiment)

2 to 10 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device using a high dielectric constant material according to a first embodiment of the present invention.

Referring to FIG. 2, an interlayer insulating film 102 for forming a capacitor is formed on a semiconductor substrate 100 on which substructures such as transistors and bit lines are formed. A photoresist is coated on the interlayer insulating layer 102 and a photolithography and etching process are performed to form a buried contact hole exposing the source region of the transistor. Subsequently, a plug 104 for filling the buried contact hole is formed using polysilicon doped with impurities. At this time, it is preferable that the plug 104 is formed so as not to completely fill the buried contact hole.

Referring to FIG. 3, an ohmic layer 106 that lowers contact resistance on a semiconductor substrate on which the plug 104 is formed and a barrier layer for preventing diffusion of impurities from the lower plug 104. (barrier layer 108) is laminated using Ti and TiN. At this time, at the interface between the plug 104 made of polysilicon and the ohmic layer 106 made of Ti, Ti and Si react to generate TiSix, thereby improving conductivity characteristics in the buried contact hole. Subsequently, the surface of the interlayer insulating layer 102 may be exposed by performing an etch back or chemical mechanical polishing (CMP) process on the semiconductor substrate on which the ohmic layer 106 and the barrier layer 108 are stacked. Proceed until to achieve overall planarization.

Referring to FIG. 4, a first metal layer 210 is stacked on a semiconductor substrate on which the planarization is achieved, one selected from Ru, RuO 2, Ti, TiN, and a combination of metals, and one metal selected from Pt, Ir, and IrO 2 is formed. The second metal layer 212 is formed using a metal organic CVD (MOCVD) or a sputtering method. In this case, the second metal layer 212 is formed to be thinner than the first metal layer 210 to facilitate etching.

Referring to FIG. 5, a mask layer 114, such as an oxide film for forming a mask, is stacked on the second metal layer 212, a photoresist film is coated on the mask layer 114, and exposed and developed. The photoresist pattern 116 is formed.

Referring to FIG. 6, a mask pattern 114 ′ is formed by patterning a mask layer 114 formed of an oxide layer under the photoresist pattern 116 as a mask. Subsequently, an ashing process is performed to remove the photoresist pattern 116. In general, a mask layer including a mixture of an oxide film and another film is used to etch a second metal layer such as platinum, but the present invention does not require a separate mask layer because the thickness of the second metal layer 112 is relatively thin. Do not.

Referring to FIG. 7, dry etching is performed on the mask pattern 114 ′ formed of the oxide layer using an etch mask to etch the second metal layer 112 such as platinum and the first metal layer 110 such as ruthenium. At this time, since the second metal layer 112 has a relatively thin thickness, even if erosion occurs at an edge of the second metal layer 112 by being etched obliquely, it is not a big problem. In addition, the first metal layer 110 thickly formed as ruthenium in the lower portion is etched at a desired angle relatively close to a right angle. Therefore, the overall shape of the lower electrode can be formed without excessive deformation.

Referring to FIG. 8, the mask pattern 114 ′ formed of the oxide film is removed, and the metal layer 118 for spacer formation is stacked using one metal selected from Pt, Ir, and IrO 2 having a predetermined thickness on the entire semiconductor substrate. do.

9, the metal layer 118 is etched back to form metal spacers 118 ′ on both sidewalls of the first metal layer 110 ′ and the second metal layer 112 ′. The etch back process may be achieved by anisotropically etching the metal layer 118 through dry etching such as reactive ion etching (RIE). Here, the second metal layer 112 'and the metal spacer 118' made of one material selected from Pt, Ir, and IrO2 formed to surround the outside of the first metal layer 110 'may have a leakage current at the surface of the lower electrode. It suppresses the occurrence of leakage current.

Referring to FIG. 10, a high dielectric film 120 is formed on the resultant using one material selected from BST, PZT, and Ta 2 O 5, and a conductive material is formed to form the upper electrode 122 of the high dielectric film 120. A layer is formed and patterned to complete the capacitor forming process of the semiconductor device using the high dielectric constant material according to the embodiment of the present invention.

Second embodiment

11 to 19 are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device using a high dielectric constant material according to a second embodiment of the present invention. Here, in the case where the configuration and the formation method of each member overlap with the first embodiment, detailed description is omitted, and all the reference numerals are configured to correspond to the first embodiment.

Referring to FIG. 11, an interlayer insulating film 202 is formed in a semiconductor substrate 200, and the interlayer insulating film is patterned to form a buried contact hole. Subsequently, a plug 204 made of polysilicon completely filling the buried contact hole is formed at the same height as the interlayer insulating film 202.

Referring to FIG. 12, an ohmic layer 206 and a barrier layer 208 are formed on the interlayer insulating layer 202 so as to be connected to the plug 204 completely embedded therein. Subsequently, the first metal layer 210, the second metal layer 212, and the mask layer 214 are sequentially stacked.

Referring to FIG. 13, a photoresist pattern 216 is formed on the mask layer 214 through an exposure and development process.

Referring to FIG. 14, the mask layer 214 is patterned using the photoresist pattern 216 to form a mask 214 'formed of an oxide film, and then the lower layer is formed using the mask 214' composed of the oxide film. The lower electrode is formed by patterning the second metal layer 212, the first metal layer 210, the barrier layer 208, and the ohmic layer 206.

Referring to FIG. 15, an insulating film 230 for forming a spacer on the resultant material, for example, a film that can be deposited at a low temperature such as SOG (Silicon On Glass) or TEOS is deposited on the entire semiconductor substrate.

Referring to FIG. 16, an insulating layer spacer 232 is formed to completely cover both sidewalls of the barrier layer 208 ′ and the ohmic layer 206 ′ by performing reactive ion etching (RIE) on the spacer forming insulating layer 230. To form. Here, the insulating film spacer 232 is formed in order to prevent the ohmic layer 206 'and the barrier layer 208' from being oxidized and deteriorating capacitance characteristics in a subsequent step.

Referring to FIG. 17, a metal layer 218 using the same material as that of the second metal layer 210 is stacked on a resultant on which the insulating film spacer 232 is formed.

Referring to FIG. 18, anisotropic etching of the metal layer 218 by dry etching is performed to form metal spacers 218 ′ on both sidewalls of the first metal layer 210 ′ and the second metal layer 212 ′. Therefore, the metal spacer 218 ′ is formed on the insulating film spacer 232 and is formed to surround the outside of the first metal layer 210 ′ to suppress leakage current generated from the surface of the capacitor lower electrode. Will be performed.

Referring to FIG. 19, the semiconductor device according to the second embodiment of the present invention is formed by stacking and patterning a high-k dielectric film 220 and a conductive film for forming the upper electrode 222 on a resultant in which the metal spacer 218 ′ is formed. Complete the capacitor formation process.

The present invention is not limited to the above-described embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit to which the present invention belongs.

Therefore, according to the present invention described above, the lower electrode of the capacitor is eroded during the etching process (erosion) to improve the problem of etching with a gentle gradient, and by raising the height of the capacitor lower electrode to increase the cross-sectional area of the electrode efficiently the capacitance You can increase it.

Claims (22)

A capacitor electrode of a semiconductor device using a high dielectric constant material as a dielectric film, The capacitor electrode may include a first metal layer which is well etched into a stack type; And A capacitor electrode of a semiconductor device using a high dielectric constant material, comprising a second metal layer having excellent leakage current characteristics due to poor etching but poor oxidation. The capacitor electrode of a semiconductor device using a high dielectric constant material according to claim 1, wherein the high dielectric constant material is made of one material selected from BST, PZT, and Ta ₂ O ₅ . The capacitor electrode of claim 1, wherein the first metal layer is formed of one selected from Ru, RuO ₂ , Ti, TiN, and a combination of metals. The capacitor electrode of claim 1, wherein the second metal layer is formed using one metal selected from Pt, Ir, and IrO ₂ . The capacitor electrode of claim 1, wherein the first metal layer is formed under the second metal layer. The method of claim 1, wherein the first metal layer has a thickness thicker than that of the second metal layer. Forming a plug in a semiconductor substrate in which a contact hole for forming a capacitor is formed; Stacking and planarizing an ohmic layer and a barrier layer on the plug; A third step of sequentially stacking the first metal layer for the capacitor electrode and the metal layer for the second electrode on the entire surface of the planarized semiconductor substrate; A fourth step of forming a mask layer on the resultant product; A fifth step of patterning first and second metal layers using the mask layer; A sixth step of removing the mask layer and forming metal spacers on both sidewalls of the first and second metal layers; Stacking a high dielectric film and an upper electrode on the resultant product on which the metal layer spacer is formed; And an eighth step of patterning the high dielectric film and the upper electrode to form a capacitor. 8. The method of claim 7, wherein the plug of the first step is formed so as not to completely fill the contact hole. The method of claim 7, wherein the planarization of the second step is performed to have the same height as that of the insulating film on which the contact hole is formed. 8. The semiconductor device of claim 7, wherein the first metal layer of the third step is formed using a material selected from Ru, RuO 2, Ti, TiN, and a combination of metals. 9. How to form a capacitor. The method of claim 7, wherein the second metal layer of the third step is formed by using one material selected from Pt, Ir, and IrO 2. 8. The method of claim 7, wherein the first metal layer is formed thicker than the second metal layer. The method of claim 7, wherein the metal spacer of the sixth step is formed by using one material selected from Pt, Ir, and IrO 2. The method of claim 1, wherein the high-k dielectric film of the seventh step is formed by using a material selected from a high-k dielectric material consisting of BST, PZT, and Ta 2 O 5. . Forming a plug in a semiconductor substrate in which a contact hole for forming a capacitor is formed; A second step of sequentially stacking an ohmic layer and a barrier layer on an entire surface of the semiconductor substrate on which the plug is formed; A third step of sequentially stacking a first metal layer and a second metal layer for a capacitor electrode on the barrier layer; Forming a lower electrode by forming a mask layer on the second metal layer to pattern a lower second metal layer, a first metal layer, a barrier layer, and an ohmic layer; Forming a insulating film spacer on both sidewalls of the barrier layer and the ohmic layer; A sixth step of forming metal spacers on both side walls of the first metal layer and the second metal layer; Stacking a high dielectric film and an upper electrode on the resultant product on which the metal spacers are formed; And an eighth step of patterning the high dielectric film and the upper electrode to form a capacitor. 16. The method of claim 15, wherein the method of forming the plug of the first step is such that the plug is completely filled with the contact hole. The semiconductor device of claim 15, wherein the first metal layer of the third step is formed by using one material selected from Ru, RuO 2, Ti, TiN, and metals in combination thereof. How to form a capacitor. 16. The method of claim 15, wherein the second metal layer of the third step is formed by using one metal selected from Pt, Ir, and IrO2. 16. The method of claim 15, wherein the first metal layer is formed thicker than the second metal layer. The method of claim 15, wherein the insulating film spacer of the fifth step is formed using silicon on glass (SOG) or TEOS. 16. The method of claim 15, wherein the metal spacer of the sixth step is formed by using one metal selected from Pt, Ir, and IrO2. 16. The method of claim 15, wherein the high dielectric film of the seventh step is formed using a material selected from high dielectric constant materials consisting of BST, PZT, and Ta2O5. .