KR100414227B1 - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR100414227B1 KR100414227B1 KR10-2001-0038886A KR20010038886A KR100414227B1 KR 100414227 B1 KR100414227 B1 KR 100414227B1 KR 20010038886 A KR20010038886 A KR 20010038886A KR 100414227 B1 KR100414227 B1 KR 100414227B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
Abstract
본 발명은 전기도금법에 의한 스토리지노드 형성시, 스토리지노드를 절연시키기 위한 에치백시 스토리지노드가 동시에 식각됨에 따른 유전용량 저하를 개선시키도록 한 캐패시터의 제조 방법을 제공하기 위한 것으로, 반도체기판상에 시드층을 형성하는 단계, 상기 시드층상에 희생막을 형성하는 단계, 상기 희생막을 선택적으로 식각하여 상기 시드층을 노출시키는 하부전극이 형성될 오목부를 오픈시키는 단계, 상기 오목부내의 상기 시드층상에 상기 오목부를 일부 채우는 형태로 하부전극을 증착시키는 단계, 상기 하부전극을 포함한 전면에 식각보호막을 형성하는 단계, 상기 희생막의 표면이 드러날때까지 상기 식각보호막을 화학적기계적연마하여 상기 하부전극 상에 잔류시키는 단계, 상기 희생막을 선택적으로 제거하는 단계, 상기 희생막 제거후 드러난 상기 시드층을 에치백하여 상기 하부전극을 절연시키는 단계, 및 상기 식각보호막을 선택적으로 제거하는 단계를 포함하여 이루어진다.The present invention is to provide a method for manufacturing a capacitor to improve the reduction in dielectric capacity due to the etching of the storage node at the same time when the storage node is formed by the electroplating method, to insulate the storage node, on a semiconductor substrate Forming a seed layer, forming a sacrificial layer on the seed layer, selectively etching the sacrificial layer to open a recess in which a lower electrode exposing the seed layer is to be formed, and on the seed layer in the recess Depositing a lower electrode to partially fill the recess, forming an etch protective film on the entire surface including the lower electrode, and chemically mechanically polishing the etch protective film until the surface of the sacrificial film is exposed to remain on the lower electrode. Selectively removing the sacrificial layer; The geohu etched back to the seed layer exposed step of insulating the lower electrode, and comprises the step of selectively removing the etching protective film.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 캐패시터의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.
반도체소자에서 캐패시터의 정전용량(Capacitance; C)은(ε: 유전율, A: 표면적, d: 유전체 두께)로 나타내는데, 스토리지노드(또는 하부전극)의 표면적과 유전체의 유전율에 비례하는 값을 갖는다.The capacitance C of the capacitor in the semiconductor device is (ε: dielectric constant, A: surface area, d: dielectric thickness), which is proportional to the surface area of the storage node (or lower electrode) and the dielectric constant of the dielectric material.
따라서 미세화되어 가는 반도체소자의 제조 공정에 있어 반도체소자가 적절히 동작하기 위한 일정량 이상의 정전용량을 확보하기 위하여 스토리지노드의 모양을 3차원 구조로 형성하여 스토리지노드의 표면적을 증가시키거나, 높은 유전율을 갖는 BST[(Ba,Sr)TiO3] 등과 같은 고유전체 물질을 사용하여 정전용량을 확보하는 방법이 연구되고 있다.Therefore, in the manufacturing process of semiconductor devices that are miniaturized, in order to secure a certain amount of capacitance for proper operation of the semiconductor devices, the shape of the storage node is formed in a three-dimensional structure to increase the surface area of the storage node or to have a high dielectric constant. A method of securing capacitance by using a high dielectric material such as BST [(Ba, Sr) TiO 3 ] has been studied.
그러나, 3차원 형태의 스토리지노드를 형성하기에는 복잡한 공정이 요구되므로 제조 원가의 상승 및 공정 증가에 따른 수율 하락의 단점이 있으며, BST 고유전체의 사용은 산소 화학정량(Oxygen stoichiometry)을 엄격히 유지하기 어려워 누설전류 특성이 열화되는 문제가 있다.However, the formation of a three-dimensional storage node requires a complicated process, which leads to a decrease in yield due to an increase in manufacturing costs and an increase in the process, and the use of BST high dielectric materials makes it difficult to strictly maintain oxygen stoichiometry. There is a problem that the leakage current characteristics deteriorate.
또한, BST 캐패시터의 경우 스토리지노드로 산화저항성이 큰 백금, 루테늄과 같은 귀금속(noble metal)을 사용해야 하는데, 이런 귀금속이 매우 안정하여 식각 공정이 어려울뿐만 아니라, 주로 스퍼터링에 의한 식각을 진행하므로 수직 프로파일을 얻기 어려운 문제점이 있다.In the case of BST capacitors, noble metals such as platinum and ruthenium, which are highly resistant to oxidation, should be used as storage nodes. Since such noble metals are very stable and difficult to etch, the vertical profile is mainly performed by etching by sputtering. There is a problem that is difficult to obtain.
이를 해결하기 위해 산화막을 이용하여 캐패시터 패턴을 형성한 후 귀금속을 전기화학증착법(Electro Chemical Deposition; ECD)을 이용하여 증착한 후, 에치백하는 방법이 연구되었다.In order to solve this problem, a method of forming a capacitor pattern using an oxide film, depositing a noble metal using an Electro Chemical Deposition (ECD), and then etching back was studied.
도 1a 내지 도 1c는 종래기술에 따른 캐패시터의 제조 방법을 도시한 도면이다.1A to 1C illustrate a method of manufacturing a capacitor according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 트랜지스터 제조 공정을 실시하는데, 먼저 반도체기판(11)상에 워드라인(도시 생략), 소스/드레인(12)을 형성한 후, 반도체기판(11)상에 반도체기판과 캐패시터의 절연을 위한 층간절연막(13)을 증착한다. 그리고, 층간절연막(13)상에 층간절연막(13)과 식각선택비가 높은 SiON막(14)을 증착한다.As shown in FIG. 1A, a transistor manufacturing process is performed on a semiconductor substrate 11. First, a word line (not shown) and a source / drain 12 are formed on the semiconductor substrate 11, and then a semiconductor substrate is formed. An interlayer insulating film 13 for insulating the semiconductor substrate and the capacitor is deposited on (11). Then, the interlayer insulating film 13 and the SiON film 14 having a high etching selectivity are deposited on the interlayer insulating film 13.
다음으로, SiON막(14)과 층간절연막(13)을 선택적으로 식각하여 소스/드레인(12)과 캐패시터 사이의 수직배선을 위한 콘택홀을 형성하고, 콘택홀을 포함한 전면에 폴리실리콘을 증착한다.Next, the SiON film 14 and the interlayer insulating film 13 are selectively etched to form contact holes for vertical wiring between the source / drain 12 and the capacitor, and polysilicon is deposited on the entire surface including the contact holes. .
계속해서, 폴리실리콘을 에치백(Etchback)하여 콘택홀에 폴리실리콘 플러그(15)를 리세스(Recess)시킨다.Subsequently, the polysilicon is etched back to recess the polysilicon plug 15 in the contact hole.
다음으로, 전면에 폴리실리콘플러그(15)와 후속 확산배리어막의 접촉저항을 낮추기 위해 티타늄(Ti)을 증착하고 급속열처리(Rapid Thermal Process; RTP)하여 폴리실리콘 플러그(15)의 표면에 티타늄실리사이드(Ti-silicide)(16)를 형성한다.Next, in order to reduce the contact resistance between the polysilicon plug 15 and the subsequent diffusion barrier layer on the front surface, titanium (Ti) is deposited, and a rapid thermal process (RTP) is performed on the surface of the polysilicon plug 15. Ti-silicide) 16 is formed.
계속해서, 티타늄실리사이드(16)상에 확산배리어막으로서 티타늄나이트라이드(TiN)(17)을 증착한 후, SiON막(14)의 표면이 노출될때까지 화학적기계적연마하여 티타늄나이트라이드(17)를 평탄화시킨다. 이 때, 티타늄나이트라이드(17)는 후속 열처리공정시 스토리지노드로부터 폴리실리콘플러그(15) 또는 반도체기판(11)으로의 산소의 확산방지막 역할을 한다.Subsequently, after depositing titanium nitride (TiN) 17 as a diffusion barrier film on the titanium silicide 16, the titanium nitride 17 is chemically polished until the surface of the SiON film 14 is exposed. Planarize. At this time, the titanium nitride 17 serves as a diffusion barrier of oxygen from the storage node to the polysilicon plug 15 or the semiconductor substrate 11 in a subsequent heat treatment process.
계속해서, 폴리실리콘 플러그(15), 티타늄실리사이드(16) 및 티타늄나이트라이드(17)의 적층구조가 매립된 결과물의 전면에 백금_시드층(18)을 증착한 다음, 백금_시드층(18)상에 희생막(19)을 증착한다.Subsequently, the platinum_seed layer 18 is deposited on the entire surface of the resultant product in which the stack structure of the polysilicon plug 15, the titanium silicide 16, and the titanium nitride 17 is embedded, and then the platinum_seed layer 18 The sacrificial film 19 is deposited on the.
여기서, 백금_시드층(18)은 스토리지노드를 전기도금법의 일종인 전기화학증착법(ECD)으로 형성하기 위한 시드층으로서 물리적기상증착법(Physical Vapor Deposition; PVD)으로 형성한다.Here, the platinum_seed layer 18 is a seed layer for forming the storage node by electrochemical deposition (ECD), which is a type of electroplating method, and is formed by physical vapor deposition (PVD).
다음으로, 희생막(19)상에 감광막을 도포한 다음, 감광막을 노광 및 현상으로 패터닝하여 스토리지노드 마스크(도시 생략)를 형성한 후, 스토리지노드 마스크로 희생막(19)을 건식식각하여 백금_시드층(18)의 표면이 노출되는 스토리지노드가 형성될 영역(이하 '오목부'라 약칭함)(20)을 오픈시킨다.Next, after the photoresist is coated on the sacrificial layer 19, the photoresist is patterned by exposure and development to form a storage node mask (not shown), and then the dry sacrificial layer 19 is dry-etched with the storage node mask to form platinum. Open the region 20 (hereinafter, abbreviated as “concave portion”) in which the storage node on which the surface of the seed layer 18 is exposed is formed.
도 1b에 도시된 바와 같이, 백금_시드층(18)에 바이어스를 인가하는 전기화학증착법으로 오목부(20)내의 노출된 백금_시드층(18)상에 백금_하부전극(21)을 적층시킨다.As shown in FIG. 1B, the platinum_lower electrode 21 is deposited on the exposed platinum_seed layer 18 in the recess 20 by an electrochemical deposition method of applying a bias to the platinum_seed layer 18. Let's do it.
다음으로, SiON막(14)의 표면이 드러나도록 희생막(19)을 식각하여 백금_하부전극(21)이 증착되지 않은 백금_시드층(18)을 노출시킨다.Next, the sacrificial film 19 is etched to expose the surface of the SiON film 14 to expose the platinum_seed layer 18 on which the platinum_lower electrode 21 is not deposited.
도 1c에 도시된 바와 같이, 희생막(19) 제거후 노출된 백금_시드층(18)을 건식 에치백(dry etchback)하여 완전히 제거한다. 이 때, 백금_시드층(18)이 서로 분리되므로 인접한 셀간 백금_하부전극(21)이 분리된다.As shown in FIG. 1C, after the sacrificial layer 19 is removed, the exposed platinum_seed layer 18 is dry etched back and completely removed. At this time, since the platinum_seed layer 18 is separated from each other, the platinum_lower electrode 21 is separated between adjacent cells.
상술한 종래기술은 백금_하부전극(21) 형성시 백금을 직접 식각하지 않으므로 백금 식각에 대한 부담을 감소시키고 있다.In the above-described conventional technique, since platinum is not directly etched when the platinum_lower electrode 21 is formed, the burden on platinum etching is reduced.
그러나, 종래기술은 백금_시드층(18)을 분리시키기 위한 건식 에치백후, 백금_하부전극(21)도 동시에 식각되어 백금_하부전극(21)의 높이가 낮아지는 문제점이 있다(A).However, in the related art, after the dry etch-back for separating the platinum_seed layer 18, the platinum_lower electrode 21 is also simultaneously etched to lower the height of the platinum_lower electrode 21 (A).
이로 인해 백금_하부전극(21)의 면적이 감소하여 캐패시터의 유전용량이 감소하고, 결국 캐패시터의 효율을 감소시키게 된다.As a result, the area of the platinum_lower electrode 21 is reduced to reduce the dielectric capacitance of the capacitor, thereby reducing the efficiency of the capacitor.
이를 해결하기 위해 식각보호막으로 티타늄나이트라이드(TiN)나 산화막(Oxide)을 증착할 수 있으나, 산화막을 이용하는 경우, 백금_시드층 건식 에치백시 잔류하기 어렵고, 잔류한다 하더라도 에치백 공정후 제거과정에서 백금_하부전극 하부의 층간절연막을 어택시키는 문제가 있다.To solve this problem, titanium nitride (TiN) or oxide (Oxide) may be deposited as an etch protective layer. However, in the case of using an oxide layer, it is difficult to remain during the platinum etch back dry etchback, and even after the etchback process, it is removed. Has a problem of attacking the interlayer insulating film under the platinum_lower electrode.
또한, 티타늄나이트라이드막을 사용한 경우는 식각을 방지하는 효과는 우수하나, 하부전극과 플러그간의 오정렬(misalign)이 발생된 경우에는 티타늄나이트라이드 제거시에 확산방지막으로 이용된 티타늄나이트라이드까지 습식식각되기 때문에 그 적용가능성이 저하된다.In addition, when the titanium nitride film is used, the effect of preventing etching is excellent, but when misalignment between the lower electrode and the plug occurs, wet etching is performed to the titanium nitride used as the diffusion barrier film when the titanium nitride is removed. Therefore, the applicability is lowered.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 전기도금법에 의한 하부전극 증착시, 셀간 하부전극을 절연시키기 위한 에치백에 의해 하부전극이 동시에 식각됨에 따른 캐패시터의 유전용량 저하를 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and when the lower electrode deposition by the electroplating method, the lowering of the capacitance of the capacitor as the lower electrode is simultaneously etched by the etch back to insulate the lower electrode between cells. It is an object of the present invention to provide a method of manufacturing a capacitor suitable for preventing.
도 1a 내지 도 1c는 종래기술에 따른 ECD법에 의한 캐패시터의 제조 방법을 도시한 공정 단면도,1A to 1C are cross-sectional views illustrating a method of manufacturing a capacitor by an ECD method according to the prior art;
도 2a 내지 도 2d는 본 발명의 실시예에 따른 ECD법에 의한 캐패시터의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor by an ECD method according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 소스/드레인31: semiconductor substrate 32: source / drain
33 : 층간절연막 34 : SiON막33 interlayer insulating film 34 SiON film
35 : 폴리실리콘플러그 36 : 티타늄실리사이드35: polysilicon plug 36: titanium silicide
37 : 티타늄나이트라이드 38 : 백금_시드층37: titanium nitride 38: platinum _ seed layer
39 : 희생막 40 : 백금_하부전극39: sacrificial film 40: platinum _ lower electrode
41 : 루테늄_보호막 42 : BST41: ruthenium _ shield 42: BST
43 : 상부전극43: upper electrode
상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체기판상에 시드층을 형성하는 단계, 상기 시드층상에 희생막을 형성하는 단계, 상기 희생막을 선택적으로 식각하여 상기 시드층을 노출시키는 하부전극이 형성될 오목부를 오픈시키는 단계, 상기 오목부내의 상기 시드층상에 상기 오목부를 일부 채우는 형태로 하부전극을 증착시키는 단계, 상기 하부전극을 포함한 전면에 식각보호막을 형성하는 단계, 상기 희생막의 표면이 드러날때까지 상기 식각보호막을 화학적기계적연마하여 상기 하부전극 상에 잔류시키는 단계, 상기 희생막을 선택적으로 제거하는 단계, 상기 희생막 제거후 드러난 상기 시드층을 에치백하여 상기 하부전극을 절연시키는 단계, 및 상기 식각보호막을 선택적으로 제거하는 단계를 포함하여 이루어짐을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor, which includes forming a seed layer on a semiconductor substrate, forming a sacrificial layer on the seed layer, and selectively etching the sacrificial layer to expose the seed layer. Opening a recess in which an electrode is to be formed, depositing a lower electrode to partially fill the recess on the seed layer in the recess, forming an etch protective film on the entire surface including the lower electrode, and a surface of the sacrificial layer Chemically polishing the etch-protection layer and remaining on the lower electrode until it is revealed, selectively removing the sacrificial layer, and etching back the seed layer exposed after removing the sacrificial layer to insulate the lower electrode. And selectively removing the etch protection film. It shall be.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 도면이다.2A to 2D illustrate a method of manufacturing a capacitor according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(31)상에 트랜지스터 제조 공정을 실시하는데, 먼저 반도체기판(31)상에 워드라인(도시 생략), 소스/드레인(32)을 형성한 후, 반도체기판(31)상에 반도체기판(31)과 캐패시터의 절연을 위한 층간절연막(33)으로서 SiO2을 증착한다. 그리고, 층간절연막(33)상에 층간절연막(33)과 식각선택비가 높은 SiON막(34)을 증착하는데, 여기서, SiON막(34)은 후속 시드층 에치백시 하부 층간절연막(33)이 손상되는 것을 방지하는 식각배리어막이다.As shown in FIG. 2A, a transistor manufacturing process is performed on a semiconductor substrate 31. First, a word line (not shown) and a source / drain 32 are formed on the semiconductor substrate 31, and then the semiconductor substrate is formed. SiO 2 is deposited on the 31 as the interlayer insulating film 33 for insulating the semiconductor substrate 31 and the capacitor. Then, the interlayer insulating film 33 and the SiON film 34 having a high etching selectivity are deposited on the interlayer insulating film 33, where the SiON film 34 is damaged during the subsequent seed layer etch back. It is an etching barrier film that prevents the formation.
이 때, 층간절연막(33)과 SiON막(34)은 총 300Å∼1000Å의 두께로 증착된다.At this time, the interlayer insulating film 33 and the SiON film 34 are deposited to a total thickness of 300 mW to 1000 mW.
다음으로, SiON막(34)과 층간절연막(33)을 선택적으로 식각하여 소스/드레인(32)과 캐패시터 사이의 수직배선을 위한 콘택홀을 형성하고, 콘택홀을 포함한 전면에 폴리실리콘을 증착한다.Next, the SiON film 34 and the interlayer insulating film 33 are selectively etched to form contact holes for vertical wiring between the source / drain 32 and the capacitor, and polysilicon is deposited on the entire surface including the contact holes. .
계속해서, 폴리실리콘을 에치백하여 콘택홀에 폴리실리콘 플러그(35)를 500Å∼1500Å으로 리세스시킨 다음, 전면에 폴리실리콘플러그(35)와 후속 확산배리어막의 접촉저항을 낮추기 위해 티타늄(Ti)을 100Å∼300Å의 두께로 증착하고 급속열처리(RTP)하여 폴리실리콘 플러그(35)의 표면에 티타늄실리사이드(Ti-silicide)(36)를 형성한다.Subsequently, the polysilicon is etched back to recess the polysilicon plug 35 in the contact hole at 500 1 to 1500 Å, and then titanium (Ti) to reduce the contact resistance between the polysilicon plug 35 and the subsequent diffusion barrier film on the front surface. Is deposited to a thickness of 100 kPa to 300 kPa and subjected to rapid heat treatment (RTP) to form titanium silicide (Ti-silicide) 36 on the surface of the polysilicon plug 35.
그리고, 미반응 티타늄을 습식으로 제거한 다음, 티타늄실리사이드(36)상에 확산방지막으로서 티타늄나이트라이드(37)를 증착한 후, SiON막(34)의 표면이 노출될때까지 화학적기계적연마하여 티타늄나이트라이드(37)를 평탄화시킨다. 이 때,티타늄나이트라이드(37)는 후속 열처리공정시 스토리지노드로부터 폴리실리콘플러그 또는 반도체기판으로의 산소의 확산방지막 역할을 한다.After the unreacted titanium is wet, the titanium nitride 37 is deposited on the titanium silicide 36 as a diffusion barrier layer, and then chemically mechanically polished until the surface of the SiON film 34 is exposed. Flatten 37. At this time, the titanium nitride 37 serves as a diffusion barrier of oxygen from the storage node to the polysilicon plug or the semiconductor substrate in the subsequent heat treatment process.
여기서, 티타늄나이트라이드(37)외에 확산방지막으로 TiSiN, TiAlN, TaSiN, TaAlN을 이용할 수 있으며, 이러한 확산방지막들은 물리기상증착법(PVD) 또는 화학기상증착법(CVD)으로 증착된다.Here, in addition to the titanium nitride 37, TiSiN, TiAlN, TaSiN, TaAlN may be used as the diffusion barrier, and these diffusion barriers are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
계속해서, 폴리실리콘 플러그(35), 티타늄실리사이드(36) 및 티타늄나이트라이드(37)의 적층구조가 매립된 결과물의 전면에 백금_시드층(38)을 50Å∼1000Å의 두께로 증착한 다음, 백금_시드층(38)상에 희생막(39)을 증착한다.Subsequently, the platinum_seed layer 38 was deposited to a thickness of 50 kPa to 1000 kPa on the entire surface of the resultant product in which the laminated structure of the polysilicon plug 35, titanium silicide 36 and titanium nitride 37 was embedded. A sacrificial film 39 is deposited on the platinum seed layer 38.
여기서, 백금_시드층(38)은 백금_스토리지노드를 전기도금법의 일종인 전기화학증착법(ECD)으로 형성하기 위한 시드층으로서 물리적기상증착법(PVD)으로 형성하고, 희생막(39)은 감광막이거나, 또는 화학기상증착법에 의한 산화막으로서 5000Å∼10000Å의 두께로 증착된다.Here, the platinum_seed layer 38 is a seed layer for forming the platinum_storage node by electrochemical deposition (ECD), which is a kind of electroplating method, and is formed by physical vapor deposition (PVD), and the sacrificial film 39 is a photoresist film. Or as an oxide film by chemical vapor deposition, deposited at a thickness of 5000 kPa to 10,000 kPa.
다음으로, 희생막(39)상에 감광막을 도포한 다음, 감광막을 노광 및 현상으로 패터닝하여 스토리지노드 마스크(도시 생략)를 형성한 후, 스토리지노드 마스크로 희생막(39)을 건식식각하여 백금_시드층(38)의 표면이 노출되는 하부전극이 형성될 영역(이하 '오목부'라 약칭함)을 오픈시킨다.Next, after the photoresist is coated on the sacrificial layer 39, the photoresist layer is patterned by exposure and development to form a storage node mask (not shown), and then the dry sacrificial layer 39 is dry-etched with the storage node mask to form platinum. Open the region (hereinafter, abbreviated as 'concave portion') in which the lower electrode on which the surface of the seed layer 38 is exposed is formed.
그리고, 전세정(pre-cleaning)을 실시한 후 오목부내의 노출된 백금_시드층(38)상에 전기화학증착법으로 백금_스토리지노드(40)를 증착시키되, 스토리지노드 영역의 소정 높이만큼 증착시킨다.Then, after pre-cleaning, the platinum_storage node 40 is deposited on the exposed platinum_seed layer 38 in the recess by electrochemical deposition, and deposited by a predetermined height of the storage node region. .
이 때, 백금_스토리지노드(40) 증착시 사용되는 전류밀도는 0.1∼10㎃/cm2의 범위이고, 전력은 직류(DC), 펄스(pulse) 또는 펄스 리버스(pulse reverse)를 인가한다.At this time, the current density used in depositing the platinum_storage node 40 is in the range of 0.1 to 10 mA / cm 2 , and power is applied by direct current (DC), pulses, or pulse reverses.
도 2b에 도시된 바와 같이, 백금_스토리지노드(40)를 포함한 희생막(39)상에 루테늄막을 증착한 후, 희생막(39)의 표면이 드러날때까지 화학적기계적연마하여 백금_스토리지노드(40) 상부를 덮는 루테늄_보호막(41)을 형성한다.As shown in FIG. 2B, the ruthenium film is deposited on the sacrificial film 39 including the platinum_storage node 40, and then chemically mechanically polished until the surface of the sacrificial film 39 is exposed. 40) A ruthenium _ protective film 41 covering the upper portion is formed.
도 2c에 도시된 바와 같이, SiON막(34)의 표면이 드러나도록 희생막(39)을 습식 딥아웃(dip-out)하여 백금_스토리지노드(40)가 증착되지 않은 백금_시드층(38)을 드러낸다. 이 때, 희생막(39)의 습식 딥아웃시, HF 또는 HF/NH4F 혼합용액을 이용한다.As illustrated in FIG. 2C, the sacrificial layer 39 is wet-dipped out so that the surface of the SiON layer 34 is exposed, and the platinum_seed layer 38 in which the platinum_storage node 40 is not deposited. ) At this time, during wet dip-out of the sacrificial film 39, HF or HF / NH 4 F mixed solution is used.
다음으로, 스토리지노드간 절연을 위하여 블랭킷 에치백에 의하여 희생막(39) 제거후 드러난 백금_시드층(38)을 제거한다. 이 때, 루테늄_보호막(41)은 백금_시드층(38)의 에치백시 백금_스토리지노드(40)가 손실되는 것을 방지한다.Next, the platinum seed layer 38 exposed after removing the sacrificial layer 39 by the blanket etch back is removed to insulate the storage nodes. At this time, the ruthenium_protective film 41 prevents the platinum_storage node 40 from being lost during etch back of the platinum_seed layer 38.
계속해서, 도 2d에 도시된 바와 같이, 루테늄_보호막(41)은 습식식각 방식으로 제거하되, 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6], 질산(HNO3) 그리고 증류수(D.I water)를 섞은 혼합용액(이하 'CAN 용액'이라 약칭함)에 딥핑(dipping)하여 제거한다.Subsequently, as shown in FIG. 2D, the ruthenium_protective film 41 is removed by wet etching, with ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ], nitric acid (HNO 3 ), and distilled water. Dip into the mixed solution (hereinafter abbreviated as 'CAN solution') mixed with (DI water) and remove.
여기서, CAN 용액내 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6]의 중량비%를 1%∼40%로 하고, 질산(HNO3)의 중량비%를 0.5%∼30%로 한다. 그리고, CAN 용액을 이용한 루테늄_보호막(41)의 식각 공정은 실온∼100℃에서 진행되고, 반도체기판(31)을 스핀 회전시키면서 진행된다.Here, the weight ratio of ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ] in the CAN solution is 1% to 40%, and the weight ratio of nitric acid (HNO 3 ) is 0.5% to 30%. . Then, the etching process of the ruthenium_protective film 41 using the CAN solution proceeds at room temperature to 100 ° C, while spin-rotating the semiconductor substrate 31.
상술한 조건에 의해 CAN 용액을 이용하여 루테늄_보호막(41)을 식각하는 경우, 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6]의 세륨(Ce)이 6(Ⅵ)가에서 3(Ⅲ)가로 변화하면서 루테늄(Ru)을 산화시켜 Ru(OH)x형태로 만들어 루테늄막을 식각한다.When the ruthenium_protective film 41 is etched using the CAN solution under the above-described conditions, cerium (Ce) of ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ] is 6 (VI) The ruthenium layer is etched by oxidizing ruthenium (Ru) to form Ru (OH) x while changing to 3 (III).
이 때, 질산(HNO3)은 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6])가 증류수에서 가수분해(hydrolyze)되는 것을 억제시킨다.At this time, nitric acid (HNO 3 ) prevents ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ]) from hydrolyzing in distilled water.
다음으로, CAN 용액에 딥핑한 후, 희석된 HF(HF:H2O=1:50)을 이용하여 5초∼180초간 세정한 후 증류수를 이용하여 다시 세정하면 루테늄이 모두 제거된다.Next, after dipping in a CAN solution, using dilute HF (HF: H 2 O = 1: 50) to wash for 5 seconds to 180 seconds and then again with distilled water to remove all ruthenium.
이 때, 희석된 HF 세정은 습식식각을 통해 형성된 식각부산물을 제거하기 위한 것이며, 짧은 시간동안 딥핑하기 때문에 층간절연막의 어택을 방지할 수 있다.At this time, the diluted HF cleaning is for removing the etch by-product formed through the wet etching, and can prevent the attack of the interlayer insulating film because it is dipped for a short time.
아울러, CAN 용액내에서 루테늄은 가용성(soluble)이기 때문에 쉽게 제거되지만, SiON(34), 층간절연막(SiO2)(33) 및 확산방지막인 티타늄나이트라이드(37)는 불용성(insoluble)이므로 루테늄 습식식각시 제거되지 않는다.In addition, ruthenium is easily removed in the CAN solution because it is soluble, but SiON (34), interlayer dielectric (SiO 2 ) 33 and titanium nitride (37), a diffusion barrier, are insoluble and therefore ruthenium wet. It is not removed during etching.
후속 공정으로, 루테늄_보호막(41)이 제거된 백금_스토리지노드(40)를 따라 전면에 BST(42), 상부전극(43)을 증착한다.In a subsequent process, the BST 42 and the upper electrode 43 are deposited on the entire surface of the platinum_storage node 40 from which the ruthenium_protective film 41 is removed.
여기서, BST(43)은 400℃∼600℃의 온도에서 화학적기상증착법(CVD)으로 150Å∼500Å의 두께로 증착한 후, 500℃∼700℃의 질소분위기에서 30초∼180초동안 급속열처리(RTP)하여 결정화시킨다.Here, the BST 43 is deposited by a chemical vapor deposition (CVD) at a temperature of 400 ° C. to 600 ° C. to a thickness of 150 ° to 500 ° C., followed by rapid thermal treatment for 30 seconds to 180 seconds in a nitrogen atmosphere of 500 ° C. to 700 ° C. RTP) to crystallize.
본 발명의 실시예에서는 전기도금법을 위한 시드층으로 백금을 이용하였으나, 백금외에 루테늄(Ru), 이리듐(Ir), 오스뮴(Os), 텅스텐(W), 몰리브덴(Mo), 코발트(Co), 니켈(Ni), 금(Au), 은(Ag) 등을 이용할 수 있다.In the embodiment of the present invention, platinum was used as a seed layer for the electroplating method, but in addition to platinum, ruthenium (Ru), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), Nickel (Ni), gold (Au), silver (Ag) and the like can be used.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 전기도금법을 이용하므로 식각이 아닌 적층으로 스토리지노드를 형성할 수 있으며, 0.1㎛이하의 소자에서 셀당 요구되는 캐패시턴스를 만족하기 위한 표면적을 확보함과 동시에 균일한 높이의 스토리지노드를 형성할 수 있어 백금 스토리지노드 사용에 따른 우수한 BST 캐패시터를 구현할 수 있는 효과가 있다.As described above, the present invention uses the electroplating method, so that the storage nodes can be formed by stacking rather than etching, while ensuring a surface area for satisfying the capacitance required per cell in a device having a thickness of 0.1 μm or less, and having a uniform storage height. Since nodes can be formed, it is possible to realize excellent BST capacitors by using platinum storage nodes.
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| KR970063711A (en) * | 1996-02-13 | 1997-09-12 | 가네꼬 히사시 | A method of manufacturing a semiconductor device in which capacitors are stacked |
| KR20000007540A (en) * | 1998-07-03 | 2000-02-07 | 윤종용 | Capacitor and fabrication method thereof |
| KR20000044893A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Fabrication method of capacitor for semiconductor device |
| US6184074B1 (en) * | 1997-12-17 | 2001-02-06 | Texas Instruments Incorporated | Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS |
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| KR970063711A (en) * | 1996-02-13 | 1997-09-12 | 가네꼬 히사시 | A method of manufacturing a semiconductor device in which capacitors are stacked |
| US6184074B1 (en) * | 1997-12-17 | 2001-02-06 | Texas Instruments Incorporated | Method of fabrication a self-aligned polysilicon/diffusion barrier/oxygen stable sidewall bottom electrode structure for high-K DRAMS |
| KR20000007540A (en) * | 1998-07-03 | 2000-02-07 | 윤종용 | Capacitor and fabrication method thereof |
| KR20000044893A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Fabrication method of capacitor for semiconductor device |
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