KR20030002103A - Method for fabricating capacitor - Google Patents
Method for fabricating capacitor Download PDFInfo
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- KR20030002103A KR20030002103A KR1020010038843A KR20010038843A KR20030002103A KR 20030002103 A KR20030002103 A KR 20030002103A KR 1020010038843 A KR1020010038843 A KR 1020010038843A KR 20010038843 A KR20010038843 A KR 20010038843A KR 20030002103 A KR20030002103 A KR 20030002103A
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- Prior art keywords
- lower electrode
- capacitor
- film
- photoresist pattern
- oxide film
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- 239000003990 capacitor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 21
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 22
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000001039 wet etching Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 5
- 239000010936 titanium Substances 0.000 claims abstract description 5
- JMGZEFIQIZZSBH-UHFFFAOYSA-N Bioquercetin Natural products CC1OC(OCC(O)C2OC(OC3=C(Oc4cc(O)cc(O)c4C3=O)c5ccc(O)c(O)c5)C(O)C2O)C(O)C(O)C1O JMGZEFIQIZZSBH-UHFFFAOYSA-N 0.000 claims description 11
- IVTMALDHFAHOGL-UHFFFAOYSA-N eriodictyol 7-O-rutinoside Natural products OC1C(O)C(O)C(C)OC1OCC1C(O)C(O)C(O)C(OC=2C=C3C(C(C(O)=C(O3)C=3C=C(O)C(O)=CC=3)=O)=C(O)C=2)O1 IVTMALDHFAHOGL-UHFFFAOYSA-N 0.000 claims description 11
- FDRQPMVGJOQVTL-UHFFFAOYSA-N quercetin rutinoside Natural products OC1C(O)C(O)C(CO)OC1OCC1C(O)C(O)C(O)C(OC=2C(C3=C(O)C=C(O)C=C3OC=2C=2C=C(O)C(O)=CC=2)=O)O1 FDRQPMVGJOQVTL-UHFFFAOYSA-N 0.000 claims description 11
- IKGXIBQEEMLURG-BKUODXTLSA-N rutin Chemical compound O[C@H]1[C@H](O)[C@@H](O)[C@H](C)O[C@@H]1OC[C@H]1[C@H](O)[C@@H](O)[C@H](O)[C@@H](OC=2C(C3=C(O)C=C(O)C=C3OC=2C=2C=C(O)C(O)=CC=2)=O)O1 IKGXIBQEEMLURG-BKUODXTLSA-N 0.000 claims description 11
- ALABRVAAKCSLSC-UHFFFAOYSA-N rutin Natural products CC1OC(OCC2OC(O)C(O)C(O)C2O)C(O)C(O)C1OC3=C(Oc4cc(O)cc(O)c4C3=O)c5ccc(O)c(O)c5 ALABRVAAKCSLSC-UHFFFAOYSA-N 0.000 claims description 11
- 235000005493 rutin Nutrition 0.000 claims description 11
- 229960004555 rutoside Drugs 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 5
- HKVFISRIUUGTIB-UHFFFAOYSA-O azanium;cerium;nitrate Chemical compound [NH4+].[Ce].[O-][N+]([O-])=O HKVFISRIUUGTIB-UHFFFAOYSA-O 0.000 claims description 5
- 239000012153 distilled water Substances 0.000 claims description 5
- 229910017604 nitric acid Inorganic materials 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000007598 dipping method Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 238000005406 washing Methods 0.000 claims 3
- 239000010408 film Substances 0.000 description 49
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 32
- 229920005591 polysilicon Polymers 0.000 description 32
- 239000011229 interlayer Substances 0.000 description 19
- 230000004888 barrier function Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 7
- 229910021341 titanium silicide Inorganic materials 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000006227 byproduct Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910000667 (NH4)2Ce(NO3)6 Inorganic materials 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 3
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052741 iridium Inorganic materials 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 230000003301 hydrolyzing effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로서, 특히 캐패시터의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.
최근에 메모리 소자의 집적도가 증가하면서 보다 높은 캐패시턴스와 작은 누설전류 특성이 요구됨에 따라 ONO, MIS(Metal Insulator Silicon)구조에서 누설전류가 작은 MIM(Metal-Insulator-Metal) 구조로 변화되고 있다.Recently, as the integration of memory devices increases, higher capacitance and smaller leakage current characteristics are required, thereby changing from ONO and MIS (Metal Insulator Silicon) structures to low leakage current MIM (Metal-Insulator-Metal) structures.
다시 말하면, 집적화되면서 보다 높은 유전상수를 지니는 BLT, BST, Ta2O5등의 고유전 상수를 갖는 유전막이 요구됨과 동시에 누설전류를 감소시키기 위해 일함수값이 큰 금속을 상부전극 및 하부전극으로 적용해야 된다.In other words, a dielectric film having a high dielectric constant such as BLT, BST, Ta 2 O 5, etc. having a higher dielectric constant while being integrated is required, and a metal having a large work function is used as the upper electrode and the lower electrode to reduce leakage current. Should apply.
전극으로 적용되는 금속은 백금(Pt), 이리듐(Ir), 루테늄(Ru), 산화이리듐막(IrO), 산화루테늄막(RuO), 백금합금(Pt-alloy) 등이 있다.Metals applied as electrodes include platinum (Pt), iridium (Ir), ruthenium (Ru), iridium oxide film (IrO), ruthenium oxide film (RuO), platinum alloys (Pt-alloy), and the like.
최근에 고밀도(High density) 반도체소자에서는 하부전극 하부에 폴리실리콘플러그를 형성하는 PP(Polysilicon Plug) 구조를 주로 적용하고 있다.Recently, a high density semiconductor device mainly uses a PP (Polysilicon Plug) structure for forming a polysilicon plug under a lower electrode.
도 1은 종래기술에 따라 제조된 캐패시터를 도시한 도면이다.1 is a view showing a capacitor manufactured according to the prior art.
도 1을 참조하면, 먼저 트랜지스터 제조 공정을 실시하는데, 반도체기판(11)상에 워드라인(도시 생략)을 형성하고, 반도체기판(11)내에 소스/드레인(12)을 형성한 후, 트랜지스터를 포함한 전면에 제 1 층간절연막(13)을 형성한다. 그리고, 제 1 층간절연막(13)을 선택적으로 식각하여 소스/드레인(12)의 어느 한 부분이 노출되는 콘택홀을 형성하고, 콘택홀에 폴리실리콘플러그(14)를 부분 매립시킨다.Referring to FIG. 1, a transistor manufacturing process is first performed. A word line (not shown) is formed on a semiconductor substrate 11, a source / drain 12 is formed in the semiconductor substrate 11, and then a transistor is formed. The first interlayer insulating film 13 is formed on the entire surface thereof. The first interlayer insulating layer 13 is selectively etched to form a contact hole in which any part of the source / drain 12 is exposed, and the polysilicon plug 14 is partially embedded in the contact hole.
상술한 콘택홀에 폴리실리콘플러그(14)를 매립시키는 방법은, 콘택홀을 포함한 제 1 층간절연막(13)상에 폴리실리콘을 증착한 후, 제 1 층간절연막(13)상의 폴리실리콘이 제거될때까지 에치백(Etch back) 또는 화학적기계적연마(Chemical Mechanical Polishing; CMP)한다.The method of embedding the polysilicon plug 14 in the above-mentioned contact hole is performed when polysilicon is deposited on the first interlayer insulating film 13 including the contact hole, and then the polysilicon on the first interlayer insulating film 13 is removed. Etch back or Chemical Mechanical Polishing (CMP).
다음으로, 폴리실리콘플러그(14)를 콘택홀에 부분 매립시킨 후, 전면에 티타늄을 증착하고 열처리하여 폴리실리콘플러그(14)상에 티타늄실리사이드(15)를 형성한다. 그리고, 티타늄실리사이드(15)상에 티타늄나이트라이드(16)를 증착한 후, 에치백이나 화학적기계적연마를 통해 콘택홀에만 티타늄나이트라이드(16)를 잔류시킨다.Next, after partially filling the polysilicon plug 14 in the contact hole, titanium is deposited on the front surface and heat-treated to form the titanium silicide 15 on the polysilicon plug 14. After the titanium nitride 16 is deposited on the titanium silicide 15, the titanium nitride 16 remains only in the contact hole through etch back or chemical mechanical polishing.
여기서, 티타늄실리사이드(15)는 폴리실리콘플러그(14)와 후속 하부전극간의 오믹콘택을 형성시켜주며, 티타늄나이트라이드(16)는 하부전극으로부터 폴리실리콘플러그(14)로 산소가 확산하는 것을 방지하는 확산방지막이다.Here, the titanium silicide 15 forms an ohmic contact between the polysilicon plug 14 and the subsequent lower electrode, and the titanium nitride 16 prevents the diffusion of oxygen from the lower electrode to the polysilicon plug 14. It is a diffusion barrier.
계속해서, 폴리실리콘플러그(14)가 매립된 제 1 층간절연막(13)상에 하부전극의 높이는 결정짓는 캐패시터산화막(17)을 증착한 후, 캐패시터산화막(17)을 스토리지노드마스크를 이용하여 식각하여 폴리실리콘플러그(14)와 정렬되는 하부전극이 형성될 영역(이하 '오목부(Concave pattern)'라 약칭함)을 형성한다.Subsequently, after depositing the capacitor oxide film 17 which determines the height of the lower electrode on the first interlayer insulating film 13 in which the polysilicon plug 14 is embedded, the capacitor oxide film 17 is etched using the storage node mask. As a result, a region (hereinafter, referred to as a “concave pattern”) in which the lower electrode aligned with the polysilicon plug 14 is to be formed is formed.
다음으로, 오목부를 포함한 캐패시터산화막(17)상에 루테늄을 이용하여 하부전극(18)을 증착한 후, 캐패시터산화막(17)의 표면이 드러날때까지 에치백 또는 화학적기계적연마하므로써 이웃한 셀간 격리되는 하부전극(18)을 형성한다.Next, after depositing the lower electrode 18 using ruthenium on the capacitor oxide film 17 including the concave portion, it is isolated between neighboring cells by etching back or chemical mechanical polishing until the surface of the capacitor oxide film 17 is exposed. The lower electrode 18 is formed.
상술한 종래기술에 나타난 바와 같이, 루테늄을 하부전극으로 도입할 경우, 하부전극의 막질에 따라 누설전류 특성을 개선시킬 수 있는데, 특히 루테늄막을 하부전극으로 사용할 경우 증착방법으로는 저압화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD)이 주로 적용되고 있다.As shown in the above-mentioned prior art, when ruthenium is introduced into the lower electrode, the leakage current characteristic can be improved according to the film quality of the lower electrode. Particularly, when the ruthenium film is used as the lower electrode, a low pressure chemical vapor deposition method is used. Low Pressure Chemical Vapor Deposition (LPCVD) is mainly applied.
그러나, 저압화학기상증착법으로 루테늄막을 증착할 경우, 반응가스로서 산소를 이용하는데, 이로 인해 증착후 루테늄막내에 산소가 존재하게 된다. 루테늄막내에 존재하는 산소가 후속 유전막 증착후 이루어지는 열공정을 거치면서 배리어막인 티타늄나이트라이드를 산화시켜 이중 캐패시터를 형성하거나, 루테늄막이 캐패시터산화막과의 접착력이 약하므로 리프팅되는 문제점이 있다.However, when the ruthenium film is deposited by low pressure chemical vapor deposition, oxygen is used as the reaction gas, which causes oxygen to exist in the ruthenium film after deposition. Oxygen present in the ruthenium film is oxidized to form a double capacitor by oxidizing titanium nitride, which is a barrier film, through a thermal process performed after the subsequent deposition of the dielectric film, or the ruthenium film has a weak adhesive strength with the capacitor oxide film.
이러한 문제점을 해결하기 위해 고온 열처리에 대해 산화의 저항력이 큰 RTN(RuTiN), RTO(RuTiO)를 적용하려는 연구가 진행되고 있다.In order to solve this problem, studies are being conducted to apply RTN (RuTiN) and RTO (RuTiO), which are highly resistant to oxidation, for high temperature heat treatment.
그러나, RTN, RTO를 하부전극으로 사용시 이를 격리시키기 위한 기술이 아직 개발되어 있지 않으며, 루테늄과 동일하게 건식식각 또는 건식에치백을 통해 셀간 하부전극을 격리시키는 경우, 에치백후 하부전극의 끝부분이 평탄하지 않아 소자동작시 전계 집중으로 인해 누설전류가 증가하거나, 또는 식각부산물이 잔류하므로 캐패시터의 전기적 특성을 저하시키는 문제점이 있다.However, when RTN and RTO are used as the lower electrodes, a technique for isolating them has not yet been developed. In the case of isolating the lower electrodes between cells through dry etching or dry etch back like ruthenium, the ends of the lower electrodes after etch back Since the device is not flat, leakage current increases due to electric field concentration during operation, or etching byproducts remain, thereby degrading the electrical characteristics of the capacitor.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 하부전극의 건식식각시 발생되는 식각부산물 및 하부전극의 끝부분에서 전계가 집중되는 것을 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and provides an etching by-product generated during dry etching of the lower electrode and a capacitor manufacturing method suitable for preventing the electric field from being concentrated at the end of the lower electrode. There is a purpose.
본 발명의 다른 목적은 하부전극으로부터 폴리실리콘플러그로 산소가 확산하는 것을 방지하는데 적합한 캐패시터의 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a capacitor suitable for preventing the diffusion of oxygen from the lower electrode to the polysilicon plug.
도 1은 종래기술에 따라 제조된 캐패시터를 도시한 도면,1 is a view showing a capacitor manufactured according to the prior art,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐패시터의 제조 방법을 도시한 도면,2a to 2d is a view showing a manufacturing method of a capacitor according to an embodiment of the present invention,
도 3은 본 발명의 다른 실시예에 따라 제조된 캐패시터를 도시한 도면.3 illustrates a capacitor manufactured according to another embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 소스/드레인21: semiconductor substrate 22: source / drain
23 : 층간절연막 24 : 폴리실리콘 플러그23 interlayer insulating film 24 polysilicon plug
25 : 티타늄실리사이드 26 : 티타늄나이트라이드25: titanium silicide 26: titanium nitride
27 : 캐패시터산화막 28 : 하부전극27: capacitor oxide film 28: lower electrode
29 : 감광막패턴29: photosensitive film pattern
상기의 목적을 달성하기 위한 본 발명의 캐패시터의 제조 방법은 반도체기판상에 하부전극의 높이를 결정짓는 캐패시터산화막을 형성하는 단계, 상기 캐패시터산화막을 선택적으로 식각하여 상기 반도체기판의 소정 표면을 노출시키는 오목부를 형성하는 단계, 상기 오목부를 포함한 상기 캐패시터산화막상에 루테늄과 티타늄이 함유된 하부전극을 증착하는 단계, 상기 하부전극상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 상기 오목부내에만 감광막패턴을 잔류시키는 단계, 상기 감광막패턴을 마스크로 상기 캐패시터산화막상의 상기 하부전극을 습식식각하는 단계, 상기 감광막패턴을 제거하는 단계, 및 상기 오목부내에 잔류하는 하부전극을 포함한 전면에 유전막, 상부전극을 순차적으로 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a capacitor of the present invention for achieving the above object is to form a capacitor oxide film that determines the height of the lower electrode on the semiconductor substrate, selectively etching the capacitor oxide film to expose a predetermined surface of the semiconductor substrate Forming a recess, depositing a lower electrode containing ruthenium and titanium on the capacitor oxide film including the recess, applying a photoresist on the lower electrode, and patterning the photoresist pattern by exposure and development to form a photoresist pattern only in the recess. Remaining, wet etching the lower electrode on the capacitor oxide film using the photoresist pattern as a mask, removing the photoresist pattern, and sequentially depositing a dielectric film and an upper electrode on the entire surface including the lower electrode remaining in the recess. Characterized in that it comprises a step of forming The.
또한 본 발명의 캐패시터의 제조 방법은 반도체기판상에 층간절연막을 증착하는 단계, 상기 층간절연막을 선택적으로 식각하여 상기 반도체기판의 표면을 노출시키는 콘택홀을 형성하는 단계, 상기 콘택홀에 폴리실리콘플러그를 부분 매립시키는 단계, 상기 폴리실리콘플러그를 포함한 전면에 루테늄이 함유된 확산방지막을 증착하는 단계, 및 상기 확산방지막을 선택적으로 습식식각하여 상기 콘택홀에만 상기 확산방지막을 잔류시키는 단계를 포함하여 이루어짐을 특징으로 한다.In addition, the method of manufacturing a capacitor of the present invention comprises the steps of depositing an interlayer insulating film on a semiconductor substrate, selectively etching the interlayer insulating film to form a contact hole exposing the surface of the semiconductor substrate, the polysilicon plug in the contact hole Partially buried a, depositing a ruthenium-containing diffusion barrier on the entire surface including the polysilicon plug, and selectively wet etching the diffusion barrier to leave the diffusion barrier only in the contact hole. It is characterized by.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 캐패시터의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 트랜지스터 제조 공정을 실시하는데, 반도체기판(21)상에 워드라인(도시 생략)을 형성하고, 반도체기판(21)내에 소스/드레인(22)을 형성한 후, 트랜지스터를 포함한 전면에 제 1 층간절연막(23)을 형성한다.As shown in FIG. 2A, a transistor fabrication process is performed. After forming a word line (not shown) on the semiconductor substrate 21 and forming a source / drain 22 in the semiconductor substrate 21, the transistor is formed. A first interlayer insulating film 23 is formed on the entire surface including the film.
그리고, 제 1 층간절연막(23)을 선택적으로 식각하여 소스/드레인(22)의 어느 한 부분이 노출되는 콘택홀을 형성하고, 콘택홀에 폴리실리콘플러그(24)를 부분 매립시킨다.The first interlayer insulating film 23 is selectively etched to form a contact hole through which any portion of the source / drain 22 is exposed, and the polysilicon plug 24 is partially embedded in the contact hole.
상술한 콘택홀에 폴리실리콘플러그(24)를 매립시키는 방법은, 콘택홀을 포함한 제 1 층간절연막(23)상에 폴리실리콘을 증착한 후, 제 1 층간절연막(23)상의 폴리실리콘이 제거될때까지 에치백 또는 화학적기계적연마(CMP)한다.The method of embedding the polysilicon plug 24 in the above-described contact hole is performed when polysilicon is deposited on the first interlayer insulating film 23 including the contact hole, and then the polysilicon on the first interlayer insulating film 23 is removed. Etch back or chemical mechanical polishing (CMP).
다음으로, 폴리실리콘플러그(24)를 콘택홀에 부분 매립시킨 후, 전면에 티타늄을 증착하고 열처리하여 폴리실리콘플러그(24)상에 티타늄실리사이드(25)를 형성한다. 그리고, 티타늄실리사이드(25)상에 티타늄나이트라이드(26)를 증착하되, 에치백이나 화학적기계적연마를 통해 콘택홀에만 잔류시킨다.Next, after partially filling the polysilicon plug 24 in the contact hole, titanium is deposited on the front surface and heat-treated to form the titanium silicide 25 on the polysilicon plug 24. Then, the titanium nitride 26 is deposited on the titanium silicide 25, but remains only in the contact hole through etch back or chemical mechanical polishing.
여기서, 티타늄실리사이드(25)는 폴리실리콘플러그(24)와 후속 하부전극간의 오믹콘택을 형성시켜주며, 티타늄나이트라이드(26)는 하부전극으로부터 폴리실리콘플러그(24)로 산소가 확산하는 것을 방지하는 확산방지막이다.Here, the titanium silicide 25 forms an ohmic contact between the polysilicon plug 24 and the subsequent lower electrode, and the titanium nitride 26 prevents the diffusion of oxygen from the lower electrode to the polysilicon plug 24. It is a diffusion barrier.
계속해서, 폴리실리콘플러그(24)가 매립된 제 1 층간절연막(23)상에 하부전극의 높이는 결정짓는 캐패시터산화막(27)을 증착한 후, 캐패시터산화막(27)을 스토리지노드마스크를 이용하여 식각하여 폴리실리콘플러그(24)와 정렬되는 오목부를 형성한다.Subsequently, after depositing the capacitor oxide film 27 to determine the height of the lower electrode on the first interlayer insulating film 23 in which the polysilicon plug 24 is embedded, the capacitor oxide film 27 is etched using a storage node mask. To form a recess aligned with the polysilicon plug 24.
다음으로, 오목부를 포함한 캐패시터산화막(27)상에 하부전극(28)으로서 RTN(RuTiN) 또는 RTO(RuTiO) 중 어느 하나를 증착한다.Next, either the RTN (RuTiN) or the RTO (RuTiO) is deposited as the lower electrode 28 on the capacitor oxide film 27 including the concave portion.
도 2b에 도시된 바와 같이, 하부전극(28)을 포함한 전면에 감광막을 도포한 후, 노광 및 현상으로 패터닝하여 하부전극(28)이 형성될 부분에만 식각배리어막으로서 감광막패턴(29)을 잔류시킨다.As shown in FIG. 2B, the photoresist film is applied to the entire surface including the lower electrode 28, and then patterned by exposure and development to leave the photoresist pattern 29 as an etching barrier film only at a portion where the lower electrode 28 is to be formed. Let's do it.
도 2c에 도시된 바와 같이, 잔류하는 감광막패턴(29)을 식각배리어막으로 하부전극(28)을 습식식각하여 이웃한 셀간 하부전극(28)을 격리시킨다. 이 때, 하부전극(28)의 습식식각을 위한 식각제로는 CAN 용액[(NH4)2Ce(NO3)6]에 증류수를 섞은 혼합용액을 이용하되, 이 혼합용액에 질산(HNO3)을 첨가한다.As shown in FIG. 2C, the lower electrode 28 is wet-etched using the remaining photoresist pattern 29 as an etch barrier film to isolate adjacent lower electrode 28 between cells. At this time, the etching agent for wet etching of the lower electrode 28 is CAN solution of nitric acid to [(NH 4) 2 Ce ( NO 3) 6] but using a mixed solution of a mixture of distilled water, the mixture solution in the (HNO 3) Add.
여기서, CAN 용액내 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6]의 중량%를 1%∼40%로 하고, 질산(HNO3)의 중량%를 0.5%∼30%로 한다. 그리고, CAN 용액을 이용한 하부전극(28)의 식각 공정은 실온∼200℃에서 진행되고, 반도체기판(21)을 스핀 회전시키면서 진행된다.Here, the weight percent of ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ] in the CAN solution is 1% to 40%, and the weight percent of nitric acid (HNO 3 ) is 0.5% to 30%. . In addition, the etching process of the lower electrode 28 using the CAN solution proceeds at room temperature to 200 ° C., while spin-rotating the semiconductor substrate 21.
상술한 조건에 의해 CAN 용액을 이용하여 하부전극(28)을 식각하는 경우, 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6]의 세륨(Ce)이 6(Ⅵ)가에서 3(Ⅲ)가로 변화하면서 RTN, RTO와 같은 하부전극(28)내 루테늄(Ru)을 산화시켜 Ru(OH)x형태로 만들어 하부전극(28)을 식각한다.When the lower electrode 28 is etched using the CAN solution under the above-described conditions, cerium (Ce) of ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ] is 3 (6) at 3 While changing (III), ruthenium (Ru) in the lower electrode 28 such as RTN and RTO is oxidized to form Ru (OH) x to etch the lower electrode 28.
이 때, 질산(HNO3)은 암모늄세륨나이트레이트[(NH4)2Ce(NO3)6])가 증류수에서 가수분해(hydrolyze)되는 것을 억제시킨다.At this time, nitric acid (HNO 3 ) prevents ammonium cerium nitrate [(NH 4 ) 2 Ce (NO 3 ) 6 ]) from hydrolyzing in distilled water.
다음으로, CAN 용액에 딥핑한 후, 희석된 HF(HF:H2O=1:50)을 이용하여 5초∼180초간 세정한 후 증류수를 이용하여 다시 세정하면 루테늄이 모두 제거된다.Next, after dipping in a CAN solution, using dilute HF (HF: H 2 O = 1: 50) to wash for 5 seconds to 180 seconds and then again with distilled water to remove all ruthenium.
이 때, 희석된 HF 세정은 습식식각을 통해 형성된 식각부산물을 제거하기 위한 것이며, HF를 섞어주면서 웨이퍼를 회전시켜 이루어진다. 또한, 짧은 시간동안 딥핑하기 때문에 층간절연막(23)의 어택을 방지할 수 있다.At this time, the diluted HF cleaning is to remove the etch by-product formed through wet etching, and is made by rotating the wafer while mixing HF. In addition, since dipping is performed for a short time, the attack of the interlayer insulating film 23 can be prevented.
아울러, CAN 용액내에서 루테늄은 가용성(soluble)이기 때문에 쉽게 제거되지만, 층간절연막(23) 및 티타늄나이트라이드(26)는 불용성(insoluble)이므로 하부전극의 습식식각시 제거되지 않는다.In addition, ruthenium is easily removed in the CAN solution because it is soluble, but the interlayer insulating film 23 and the titanium nitride 26 are insoluble and thus are not removed during wet etching of the lower electrode.
다음으로, 감광막패턴(29)을 스트립하여 하부전극(28)을 노출시킨다.Next, the photoresist pattern 29 is stripped to expose the lower electrode 28.
도 2d에 도시된 바와 같이, 하부전극(28)을 포함한 전면에 유전막(30), 상부전극(31)을 순차적으로 증착한다.As shown in FIG. 2D, the dielectric film 30 and the upper electrode 31 are sequentially deposited on the entire surface including the lower electrode 28.
도 3은 본 발명의 다른 실시예에 따라 제조된 캐패시터를 도시한 도면이다.3 is a view showing a capacitor manufactured according to another embodiment of the present invention.
도 3을 참조하면, 트랜지스터 제조 공정을 실시하는데, 반도체기판(41)상에워드라인(도시 생략)을 형성하고, 반도체기판(41)내에 소스/드레인(42)을 형성한 후, 트랜지스터를 포함한 전면에 층간절연막(43)을 형성한다.Referring to FIG. 3, a transistor fabrication process is performed. A word line (not shown) is formed on a semiconductor substrate 41, a source / drain 42 is formed in the semiconductor substrate 41, and then a transistor is included. An interlayer insulating film 43 is formed on the entire surface.
그리고, 층간절연막(43)을 선택적으로 식각하여 소스/드레인(42)의 어느 한 부분이 노출되는 콘택홀을 형성하고, 콘택홀에 폴리실리콘플러그(44)를 부분 매립시킨다.Then, the interlayer insulating layer 43 is selectively etched to form a contact hole through which any portion of the source / drain 42 is exposed, and the polysilicon plug 44 is partially embedded in the contact hole.
상술한 콘택홀에 폴리실리콘플러그(44)를 매립시키는 방법은, 콘택홀을 포함한 층간절연막(43)상에 폴리실리콘을 증착한 후, 층간절연막(43)상의 폴리실리콘이 제거될때까지 에치백 또는 화학적기계적연마(CMP)한다.In the method of embedding the polysilicon plug 44 in the above-mentioned contact hole, the polysilicon is deposited on the interlayer insulating film 43 including the contact hole and then etched back or removed until the polysilicon on the interlayer insulating film 43 is removed. Chemical mechanical polishing (CMP).
다음으로, 폴리실리콘플러그(44)를 콘택홀에 부분 매립시킨 후, 전면에 RTO 또는 RTN 중 어느 하나의 루테늄계 확산방지막(45)을 증착한 후, 루테늄계 확산방지막(45)을 선택적으로 습식식각하여 폴리실리콘플러그(44)상에만 잔류시킨다.Next, after partially filling the polysilicon plug 44 in the contact hole, the ruthenium-based diffusion barrier 45 of either RTO or RTN is deposited on the front surface, and then the ruthenium-based diffusion barrier 45 is selectively wetted. It is etched and remains only on the polysilicon plug 44.
여기서, 루테늄계 확산방지막(45)의 습식식각은 전술한 바와 같은 본 발명의 일실시예와 동일하게 진행된다.Here, the wet etching of the ruthenium-based diffusion barrier 45 proceeds in the same manner as in the embodiment of the present invention as described above.
후속 공정으로 캐패시터산화막(46) 증착, 오목부 형성, 하부전극(47) 증착 공정을 진행한다. 이 때, 하부전극(47)으로는 RTN, RTO, Ru, Pt, Ir증의 귀금속 및 귀금속함유 화합물을 이용할 수 있으며, 특히 RTN, RTO를 이용하는 경우, 습식식각을 통해 이웃한 셀간 격리시킨다.Subsequently, the capacitor oxide film 46 is deposited, the recess is formed, and the lower electrode 47 is deposited. At this time, the lower electrode 47 may be a RTN, RTO, Ru, Pt, Ir noble metal and noble metal-containing compounds, in particular, in the case of using RTN, RTO, it is isolated between the neighboring cells by wet etching.
상술한 바와 같이, 본 발명은 습식식각을 통해 하부전극을 형성하므로 식각부산물이 발생되지 않고, 하부전극의 끝부분이 평탄하다. 또한, 습식식각을 통해 셀간 하부전극을 격리시키므로 동시에 여러장의 웨이퍼를 한번에 처리할 수 있다.As described above, since the present invention forms the lower electrode through wet etching, no etching by-product is generated and the end of the lower electrode is flat. In addition, since the lower electrode between the cells is isolated through wet etching, several wafers can be processed at the same time.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 습식식각을 이용하여 루테늄이 함유된 금속박막을 식각하여 하부전극을 형성하므로써 여러장의 웨이퍼를 한번에 처리할 수 있어 공정 진행시간을 단축시킬 수 있는 효과가 있다.As described above, the present invention is capable of treating several wafers at once by forming a lower electrode by etching a metal thin film containing ruthenium using wet etching, thereby reducing the process progress time.
또한, 고온 열처리에 대해 산화의 저항력이 우수한 RTN, RTO를 하부전극으로 이용할 수 있는 효과가 있으며, 아울러 습식식각을 이용하므로 식각부산물을 형성시키지 않아 캐패시터의 전기적 특성을 향상시킬 수 있는 효과가 있다.In addition, there is an effect that can be used as a lower electrode RTN, RTO excellent in the oxidation resistance against high temperature heat treatment, and also by using the wet etching has the effect of improving the electrical characteristics of the capacitor does not form an etching by-product.
Claims (7)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030047077A (en) * | 2001-12-07 | 2003-06-18 | 삼성전자주식회사 | Method for manufacturing metal - Insulator - Metal capacitor |
| KR100902102B1 (en) * | 2006-05-31 | 2009-06-09 | 주식회사 하이닉스반도체 | Semiconductor device in capacitor and method for fabricating the same |
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2001
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030047077A (en) * | 2001-12-07 | 2003-06-18 | 삼성전자주식회사 | Method for manufacturing metal - Insulator - Metal capacitor |
| KR100902102B1 (en) * | 2006-05-31 | 2009-06-09 | 주식회사 하이닉스반도체 | Semiconductor device in capacitor and method for fabricating the same |
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