KR20010038942A - Capacitor forming method - Google Patents
Capacitor forming method Download PDFInfo
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- KR20010038942A KR20010038942A KR1019990047132A KR19990047132A KR20010038942A KR 20010038942 A KR20010038942 A KR 20010038942A KR 1019990047132 A KR1019990047132 A KR 1019990047132A KR 19990047132 A KR19990047132 A KR 19990047132A KR 20010038942 A KR20010038942 A KR 20010038942A
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- film
- conductive film
- bit line
- insulating film
- layer
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- 239000003990 capacitor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000006227 byproduct Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 229910052741 iridium Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 커패시터 형성방법에 관한 것으로, 특히 고집적 메모리소자의 커패시터 하부전극으로 사용하는 물질 중에서 식각 시 불휘발성의 부산물을 생성하는 도전막을 부산물 없이 깨끗하게 가공할 수 있도록 하여 안정적인 하부전극을 형성하기에 적당하도록 한 커패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and in particular, to form a stable lower electrode by cleanly processing a conductive film without by-products that generates non-volatile by-products during etching among materials used as capacitor lower electrodes of a highly integrated memory device. The present invention relates to a capacitor forming method.
종래 커패시터 형성방법을 도 1a 내지 도 1d의 수순단면도를 참고로 하여 설명하면 다음과 같다.A method of forming a conventional capacitor will now be described with reference to the procedure cross-sectional view of FIGS. 1A to 1D.
소자가 형성된 반도체기판(1) 상부에 제 1층간절연막(2)을 증착하고 상기 소자의 특정부분에 접속되도록 폴리플러그(3)를 형성한 후 그 상부전면에 차례로 제 2층간절연막(4), 비트라인 도전막(5)을 증착하고, 이 비트라인 도전막(5)을 패터닝하여 비트라인을 형성한 후 상기 구조물 상부전면에 제 3층간절연막(6)을 증착하는 공정과; 상기 폴리플러그(3)가 형성된 영역과 연결되도록 노드컨택(7)을 형성한 후 그 상부전면에 질화막(8)을 증착하는 공정과; 상기 질화막(8) 상부에 산화막(9)을 형성하고, 이를 커패시터가 형성될 위치에 맞도록 차례로 산화막(9), 질화막(8)을 식각하여 노드컨택(7)이 드러나도록 한 다음 형성된 구조물 상부전면에 차례로 배리어막(10), 제 1도전막(11), 절연막(12)을 형성하고 그 절연막(12)을 에치백하는 공정과; 상기 절연막(12)을 이용하여 그 상부에 위치한 제 1도전막(11) 및 배리어막(10)을 식각한 후 잔류하는 절연막(12)을 제거하고, 이를 통해 형성된 구조물 상부전면에 차례로 유전막(13), 제 2도전막(14)을 형성하는 공정으로 이루어진다.The first interlayer insulating film 2 is deposited on the semiconductor substrate 1 on which the device is formed, and the poly plug 3 is formed so as to be connected to a specific portion of the device, and the second interlayer insulating film 4 is sequentially formed on the upper surface thereof. Depositing a bit line conductive film (5), patterning the bit line conductive film (5) to form a bit line, and then depositing a third interlayer insulating film (6) on the upper surface of the structure; Forming a node contact (7) so as to be connected to a region where the poly plug (3) is formed, and then depositing a nitride film (8) on the upper surface thereof; The oxide layer 9 is formed on the nitride layer 8, and the oxide layer 9 and the nitride layer 8 are sequentially etched to match the position where the capacitor is to be formed so that the node contact 7 is exposed, and then the upper portion of the structure Forming a barrier film (10), a first conductive film (11), and an insulating film (12) on the entire surface in turn and etching back the insulating film (12); After the first conductive layer 11 and the barrier layer 10 are etched using the insulating layer 12, the remaining insulating layer 12 is removed, and the dielectric layer 13 is sequentially formed on the upper surface of the structure formed through the insulating layer 12. ), And the second conductive film 14 is formed.
먼저, 도 1a에 도시한 바와같이 소자가 형성된 반도체기판(1) 상부에 제 1층간절연막(2)을 증착하고 상기 소자의 특정부분에 접속되도록 폴리플러그(3)를 형성한 후 그 상부전면에 차례로 제 2층간절연막(4), 비트라인 도전막(5)을 증착한다.First, as shown in FIG. 1A, a first interlayer insulating film 2 is deposited on the semiconductor substrate 1 on which the device is formed, and a polyplug 3 is formed to be connected to a specific portion of the device. In turn, a second interlayer insulating film 4 and a bit line conductive film 5 are deposited.
그리고, 상기 비트라인 도전막(5)을 패터닝하여 비트라인을 형성하고, 그 구조물 상부전면에 제 3층간절연막(6)을 증착한다.The bit line conductive film 5 is patterned to form a bit line, and a third interlayer insulating film 6 is deposited on the upper surface of the structure.
그 다음 도 1b에 도시한 바와같이 상기 폴리플러그(3)가 형성된 영역이 드러나도록 제 3층간절연막(6), 제 2층간절연막(4)을 식각하여 노드컨택홀을 형성하고, 그 구조물 상부전면에 폴리실리콘을 증착하고 제 3층간절연막(6)이 드러나도록 평탄화하여 노드컨택(7)을 형성한 후 그 상부전면에 Si3N4를 이용한 질화막(8)을 증착한다.Next, as shown in FIG. 1B, a node contact hole is formed by etching the third interlayer insulating film 6 and the second interlayer insulating film 4 so that the region where the poly plug 3 is formed is exposed. Polysilicon is deposited on the substrate and planarized to expose the third interlayer insulating film 6 to form a node contact 7, and then a nitride film 8 using Si 3 N 4 is deposited on the upper surface thereof.
그 다음 도 1c에 도시한 바와같이 상기 질화막(8) 상부에 산화막(9)을 형성하고, 이를 커패시터가 형성될 위치에 맞도록 차례로 산화막(9), 질화막(8)을 식각하여 노드컨택(7)이 드러나도록 패터닝한다.Next, as shown in FIG. 1C, an oxide film 9 is formed on the nitride film 8, and the oxide film 9 and the nitride film 8 are sequentially etched to match the position where the capacitor is to be formed. ) To reveal.
그리고, 상기 형성된 구조물 상부전면에 차례로 배리어막(10), 제 1도전막(11), 절연막(12)을 형성하고 그 절연막(12)을 에치백하여 상기 형성한 패턴의 상부가 드러나도록 한다.In addition, the barrier layer 10, the first conductive layer 11, and the insulating layer 12 are sequentially formed on the upper surface of the formed structure, and the insulating layer 12 is etched back to expose the upper portion of the formed pattern.
이때, 상기 제 1도전막(11)은 백금(Pt), 이리듐(Ir), 루테늄(Ru)등의 금속 또는 그 산화막을 이용한다.In this case, the first conductive film 11 may be formed of a metal such as platinum (Pt), iridium (Ir), ruthenium (Ru), or an oxide film thereof.
그 다음, 도 1d에 도시한 바와같이 상기 절연막(12)을 식각방지막으로 이용하여 그 상부에 위치한 제 1도전막(11) 및 배리어막(10)을 식각하여 커패시터 하부전극을 형성한다.Next, as shown in FIG. 1D, the first conductive layer 11 and the barrier layer 10 positioned thereon are etched using the insulating layer 12 as an etch stop layer to form a capacitor lower electrode.
그리고, 상기 잔류하는 절연막(12)을 제거하고, 이를 통해 형성된 구조물 상부전면에 유전막(13)을 형성하고, 커패시터 상부전극으로 제 2도전막(14)을 형성한다.In addition, the remaining insulating layer 12 is removed, the dielectric layer 13 is formed on the upper surface of the structure formed through the formation, and the second conductive layer 14 is formed as the capacitor upper electrode.
그러나, 상기한 바와같은 종래 커패시터 형성방법은 커패시터 하부전극인 제 1도전막이 Pt, Ir, Ru등의 금속 혹은 그 산화물로 이루어진 경우 이를 식각하는 과정에서 상기 금속 도전막과 동시에 배리어막, 절연막도 같이 식각되므로 그 부산물이 절연막의 굴곡진 부분에 쌓여 이후 잔류하는 절연막 제거 시 완전히 제거되지 않으며, 이 부산물들이 그 상부에 형성되는 유전막과 반응하여 특성을 열화시키는 문제점이 있었다.However, in the conventional capacitor forming method as described above, when the first conductive film, which is the lower electrode of the capacitor, is formed of a metal such as Pt, Ir, Ru, or an oxide thereof, in the process of etching the same, the barrier film and the insulating film may be used together with the metal conductive film. As the by-products are etched, the by-products are accumulated in the curved portion of the insulating film, and thus are not completely removed when the remaining insulating film is removed, and these by-products react with the dielectric film formed on the upper part, thereby deteriorating characteristics.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 금속으로 형성되어 보통의 플라즈마 식각으로는 패터닝이 쉽지 않으며 부산물의 처리가 곤란한 커패시터 하부전극을 부산물 없이 깨끗이 형성할 수 있는 커패시터 형성방법을 제공하는데 있다.The present invention was devised to solve the conventional problems as described above, and an object of the present invention is to form a metal without any by-products, which is not easy to pattern by normal plasma etching and difficult to process by-products. It is to provide a method of forming a capacitor that can be.
도 1은 종래 커패시터 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional capacitor forming method.
도 2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 제 1층간절연막21 semiconductor substrate 22 first interlayer insulating film
23 : 폴리플러그 24 : 제 2층간절연막23 poly plug 24 second interlayer insulating film
25 : 비트라인 도전막 26 : 제 3층간절연막25 bit line conductive film 26 third interlayer insulating film
27 : 노드컨택 28 : 질화막27: node contact 28: nitride film
29 : 배리어막 30 : 제 1도전막29 barrier film 30 first conductive film
31 : 절연막 32 : 폴리실리콘31: insulating film 32: polysilicon
33 : 실리사이드 34 : 유전막33: silicide 34: dielectric film
35 : 제 2도전막35: second conductive film
상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 형성방법은 소자가 형성된 반도체기판 상부에 제 1층간절연막을 증착하고, 상기 소자의 특정부분에 접속되도록 폴리플러그를 형성한 후 그 상부전면에 차례로 제 2층간절연막, 비트라인 도전막을 증착하는 공정과; 상기 비트라인 도전막을 패터닝하여 비트라인을 형성하고, 그 구조물 상부전면에 제 3층간절연막을 증착하는 공정과; 상기 폴리플러그가 형성된 영역과 연결되도록 노드컨택을 형성하는 공정과; 상기 구조물 상부에 질화막을 형성하고, 이를 커패시터가 형성될 위치에 맞도록 식각하여 노드컨택이 드러나도록 한 다음 형성된 구조물 상부전면에 차례로 배리어막, 제 1도전막, 절연막을 형성하고 그 절연막을 평탄화한 후 그 상부에 폴리실리콘을 증착하는 공정과; 상기 제 1도전막과 접촉하고 있는 폴리실리콘을 열처리하여 실리사이드를 형성하는 공정과; 상기 형성된 실리사이드 및 폴리실리콘을 습식각으로 제거하고 절연막을 에치백하면서 질화막 상부에 위치한 배리어막을 제거한 후 잔류하는 절연막을 제거하는 공정과; 상기 구조물 상부전면에 차례로 유전막, 제 2도전막을 형성하는 공정으로 이루어지는 것을 특징으로한다.A capacitor forming method for achieving the object of the present invention as described above is to deposit a first interlayer insulating film on the semiconductor substrate on which the device is formed, and to form a polyplug to be connected to a specific portion of the device, and then in turn on the upper surface of the device. Depositing a second interlayer insulating film and a bit line conductive film; Patterning the bit line conductive film to form a bit line, and depositing a third interlayer insulating film over the entire surface of the structure; Forming a node contact to be connected to an area where the polyplug is formed; A nitride film is formed on the structure and the node contact is exposed by etching the same to the position where the capacitor is to be formed. Then, the barrier film, the first conductive film, and the insulating film are sequentially formed on the upper surface of the formed structure, and the insulating film is planarized. Then depositing polysilicon on the top; Heat-treating the polysilicon in contact with the first conductive film to form silicide; Removing the formed silicide and the polysilicon by wet etching, removing the barrier layer positioned on the nitride layer while etching back the insulating layer, and then removing the remaining insulating layer; And forming a dielectric film and a second conductive film in order on the upper surface of the structure.
상기한 바와같은 본 발명에 의한 커패시터 형성방법을 첨부한 도 2a내지 도 2e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 2a to 2e with the method of forming a capacitor according to the present invention as described above in detail as an embodiment as follows.
먼저, 도 2a에 도시한 바와같이 소자가 형성된 반도체기판(21) 상부에 제 1층간절연막(22)을 증착하고 상기 소자의 특정부분에 접속되도록 폴리플러그(23)를 형성한 후 그 상부전면에 차례로 제 2층간절연막(24), 비트라인 도전막(25)을 증착한다.First, as shown in FIG. 2A, a first interlayer insulating film 22 is deposited on the semiconductor substrate 21 on which the device is formed, and a polyplug 23 is formed to be connected to a specific portion of the device. In turn, a second interlayer insulating film 24 and a bit line conductive film 25 are deposited.
그리고, 상기 비트라인 도전막(25)을 패터닝하여 비트라인을 형성하고, 그 구조물 상부전면에 제 3층간절연막(26)을 증착한다.The bit line conductive layer 25 is patterned to form a bit line, and a third interlayer dielectric layer 26 is deposited on the upper surface of the structure.
그 다음, 도 2b에 도시한 바와같이 상기 폴리플러그(23)가 형성된 영역이 드러나도록 제 3층간절연막(26), 제 2층간절연막(24)을 식각하여 노드컨택홀을 형성하고, 그 구조물 상부전면에 폴리실리콘을 증착하고 제 3층간절연막(26)이 드러나도록 평탄화하여 노드컨택(7)을 형성한다.Next, as shown in FIG. 2B, the third interlayer insulating layer 26 and the second interlayer insulating layer 24 are etched to expose the region where the poly plug 23 is formed, thereby forming a node contact hole, and the upper portion of the structure. Polysilicon is deposited on the entire surface and planarized so that the third interlayer insulating film 26 is exposed to form the node contact 7.
그 다음, 도 2c에 도시한 바와같이 상기 구조물 상부에 질화막(28)을 형성하고, 이를 커패시터가 형성될 위치에 맞도록 식각하여 노드컨택(27)이 드러나도록 패터닝한다.Next, as illustrated in FIG. 2C, the nitride layer 28 is formed on the structure, and the nitride layer 28 is etched to match the position at which the capacitor is to be formed and patterned so that the node contact 27 is exposed.
그리고, 상기 형성된 구조물 상부전면에 차례로 배리어막(29), 제 1도전막(30), 절연막(31)을 형성하고 그 절연막(31)을 평탄화한 후 그 상부에 폴리실리콘(32)을 증착하여 제 1도전막(30)과 폴리실리콘(32)이 특정부분에서 접촉하도록 형성한다.The barrier layer 29, the first conductive layer 30, and the insulating layer 31 are sequentially formed on the upper surface of the formed structure, the insulating layer 31 is planarized, and polysilicon 32 is deposited thereon. The first conductive film 30 and the polysilicon 32 are formed to contact each other at a specific portion.
이때, 상기 제 1도전막(30)은 Pt, Ir, Ru등의 금속 또는 그 산화막을 이용하며, 상기 절연막(31)은 스핀 온 글라스를 이용한다.In this case, the first conductive layer 30 may be formed of a metal such as Pt, Ir, Ru, or an oxide thereof, and the insulating layer 31 may be formed of spin on glass.
그 다음, 도 2d에 도시한 바와같이 상기 제 1도전막(30)은 금속 또는 그 산화물이므로 이와 접촉하고 있는 폴리실리콘(32)을 열처리하여 그 접촉부분의 제 1도전막(30)이 모두 실리사이드(33)가 되도록한다.Next, as shown in FIG. 2D, since the first conductive film 30 is a metal or an oxide thereof, the polysilicon 32 in contact with it is heat treated so that all of the first conductive film 30 in the contact portion is silicided. (33).
그 다음, 도 2e에 도시한 바와같이 상기 형성된 실리사이드(33) 및 폴리실리콘(32)은 화학처리로 쉽게 제거되므로 습식각으로 제거하고, 그 하부의 절연막(31)을 에치백하면서 질화막(28) 상부에 위치한 배리어막(29)을 제거하여 개별로 분리된 커패시터 하부전극을 형성한다.Next, as shown in FIG. 2E, the formed silicide 33 and polysilicon 32 are easily removed by chemical treatment, and are thus removed by wet etching, and the nitride layer 28 is etched back while the insulating layer 31 is etched back. The barrier layer 29 disposed on the upper side is removed to form a capacitor capacitor electrode separately separated.
그리고, 상기 잔류하는 절연막(31)을 제거하는 공정과; 상기 구조물 상부전면에 차례로 유전막(34), 제 2도전막(35)을 형성한다.And removing the remaining insulating film 31; The dielectric layer 34 and the second conductive layer 35 are sequentially formed on the upper surface of the structure.
상기한 바와같은 본 발명에 의한 커패시터 형성방법은 금속또는 그 산화물로 형성되어 보통의 플라즈마 식각으로는 패터닝이 쉽지 않고 식각 시 부산물의 처리가 곤란한 커패시터 하부전극용 도전막을 그 식각될 부분을 폴리실리콘과 반응시켜 화학적 처리로 쉽게 제거되는 실리사이드를 형성시킴으로써 부산물 없이 깨끗한 커패시터 하부전극을 형성할 수 있는 효과가 있다.The method for forming a capacitor according to the present invention as described above is formed of a metal or an oxide thereof, which is difficult to pattern by normal plasma etching and difficult to process by-products during etching. By reacting to form silicide which is easily removed by chemical treatment, there is an effect that a clean capacitor lower electrode can be formed without by-products.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418579B1 (en) * | 2001-06-30 | 2004-02-11 | 주식회사 하이닉스반도체 | Method for forming capacitor |
| KR100720235B1 (en) * | 2001-12-26 | 2007-05-22 | 주식회사 하이닉스반도체 | A capacitor of semiconductor device and manufacturing the same |
| KR101026372B1 (en) * | 2003-12-24 | 2011-04-07 | 주식회사 하이닉스반도체 | manufacturing method for bit-line in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0170308B1 (en) * | 1995-12-05 | 1999-02-01 | 김광호 | High dielectronics capacitor fabrication method |
| KR100259039B1 (en) * | 1997-02-17 | 2000-06-15 | 윤종용 | Capacitor maunfacturing method of semi-conductor device |
| KR100243283B1 (en) * | 1997-02-19 | 2000-02-01 | 윤종용 | Manufacturing method of a capacitor in a semiconductor device |
| KR20000015036A (en) * | 1998-08-26 | 2000-03-15 | 김영환 | Forming method of capacitor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100418579B1 (en) * | 2001-06-30 | 2004-02-11 | 주식회사 하이닉스반도체 | Method for forming capacitor |
| KR100720235B1 (en) * | 2001-12-26 | 2007-05-22 | 주식회사 하이닉스반도체 | A capacitor of semiconductor device and manufacturing the same |
| KR101026372B1 (en) * | 2003-12-24 | 2011-04-07 | 주식회사 하이닉스반도체 | manufacturing method for bit-line in semiconductor device |
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