KR20020010308A - Method for forming a metal electrode of a semiconductor device - Google Patents

Method for forming a metal electrode of a semiconductor device Download PDF

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Publication number
KR20020010308A
KR20020010308A KR1020000043958A KR20000043958A KR20020010308A KR 20020010308 A KR20020010308 A KR 20020010308A KR 1020000043958 A KR1020000043958 A KR 1020000043958A KR 20000043958 A KR20000043958 A KR 20000043958A KR 20020010308 A KR20020010308 A KR 20020010308A
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South Korea
Prior art keywords
metal
layer
forming
seed layer
semiconductor device
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KR1020000043958A
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Korean (ko)
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최형복
홍권
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박종섭
주식회사 하이닉스반도체
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Priority to KR1020000043958A priority Critical patent/KR20020010308A/en
Priority to US09/735,528 priority patent/US6451666B2/en
Priority to JP2000396570A priority patent/JP2001210806A/en
Priority to DE10065350A priority patent/DE10065350B4/en
Publication of KR20020010308A publication Critical patent/KR20020010308A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

Abstract

PURPOSE: A method for forming a metal electrode of a semiconductor device is provided to stably maintain an effective surface area and to form a capacitor of an integrated device having a design rule not greater than 0.10 micrometer, by forming a seed layer and by using H2SO4 solution to eliminate contaminant or particles on the seed layer. CONSTITUTION: An insulation layer and an anti-reflective coating(ARC) are sequentially formed on a semiconductor substrate having a junction part. The ARC and the insulation layer are patterned to form a contact hole so that the junction part is exposed. After a plug is formed in the contact hole, a metal silicide layer is formed on the plug. After a barrier metal layer is formed on the metal silicide layer, a metal seed layer(9) is formed on the entire surface. An insulation layer pattern is formed on the seed layer to expose the seed layer on the plug. After the organic contaminant or particles(14) on the exposed seed layer is removed, metal is deposited on the exposed seed layer. After the insulation layer pattern is eliminated, the seed layer in the exposed portion is removed.

Description

반도체 소자의 금속전극 형성 방법 {Method for forming a metal electrode of a semiconductor device}Method for forming a metal electrode of a semiconductor device

본 발명은 반도체 소자의 금속전극 형성 방법에 관한 것으로, 특히 금속으로 이루어지는 캐패시터(Capacitor)의 하부전극 형성시 금속의 증착 속도 및 두께가 균일하게 될 수 있도록 한 반도체 소자의 금속전극 형성 방법에 관한 것이다.The present invention relates to a method of forming a metal electrode of a semiconductor device, and more particularly, to a method of forming a metal electrode of a semiconductor device such that the deposition rate and thickness of the metal can be made uniform when forming a lower electrode of a metal capacitor. .

디램(DRAM)과 같은 반도체 메모리 소자의 집적도가 증가됨에 따라 칩(Chip)에서 단위 셀당 캐패시터가 차지하는 면적은 급격하게 축소된다. 그러나 메모리 소자의 동작을 위해서는 단위 메모리 셀당 일정량 이상의 정전용량 (Capacitance)이 확보되어야 하는데, 이를 위해 메모리 셀의 동작에 필요한 정전용량은 그대로 유지시키면서 캐패시터가 차지하는 면적을 최소화시킬 수 있는 새로운 공정기술이 개발되고 있다.As the degree of integration of semiconductor memory devices, such as DRAMs, increases, the area occupied by capacitors per unit cell in a chip is rapidly reduced. However, a certain amount of capacitance per unit memory cell must be secured for the operation of the memory device. A new process technology is developed to minimize the area occupied by the capacitor while maintaining the capacitance required for the operation of the memory cell. It is becoming.

제한된 면적내에서 소자의 동작에 필요한 정전용량을 확보하기 위한 방법으로 하부전극의 유효 표면적을 증가시키거나 유전특성이 향상된 유전체를 사용하며, 백금(Pt)과 같은 귀금속으로 전극을 형성한다.As a method for securing the capacitance necessary for the operation of the device within a limited area to increase the effective surface area of the lower electrode or to use a dielectric with improved dielectric properties, the electrode is formed of a precious metal such as platinum (Pt).

백금(Pt)을 이용한 금속전극은 대개 스퍼터링(Sputtering), 화학기상증착(CVD) 또는 전기 도금(ElectroChemical Deposition)법으로 형성된다. 전기 도금법으로 백금(Pt)층을 형성하기 위해서는 백금(Pt) 시드층(Seed Layer)을 형성한 후 시드층상에 백금(Pt)을 증착하는데, 이때, 시드층의 표면 상태에 따라 백금(Pt)의 증착 속도 및 양상이 달라진다. 즉, 시드층의 표면에 유기질의 오염물이나 파티클(Particle)이 존재하면 백금(Pt)이 증착되지 않거나 증착 속도가 감소되는데, 웨이퍼의 표면에 국부적으로 오염물이나 파티클이 존재하는 경우 백금(Pt)층의 두께가 불균일해져 캐패시터의 하부전극으로 사용될 수 없게 된다.Metal electrodes using platinum (Pt) are usually formed by sputtering, chemical vapor deposition (CVD) or electroplating (ElectroChemical Deposition). In order to form a platinum (Pt) layer by electroplating, a platinum (Pt) seed layer is formed and then platinum (Pt) is deposited on the seed layer. At this time, platinum (Pt) depends on the surface state of the seed layer. The deposition rate and aspect of the are different. That is, if organic contaminants or particles are present on the surface of the seed layer, platinum (Pt) is not deposited or the deposition rate is reduced.In the case of locally contaminants or particles on the surface of the wafer, the platinum (Pt) layer is present. The thickness of the substrate becomes uneven so that it cannot be used as the lower electrode of the capacitor.

또한, 전기 도금법으로 백금(Pt)층을 형성하기 위해서는 시드층을 형성한 후 선택된 부분의 시드층이 노출되도록 절연막 패턴(Dummy Pattern)을 형성하고, 노출된 시드층상에 백금(Pt)을 증착한다. 그런데 이때, 오염물이나 파티클이 존재하는 부분에서는 국부적으로 전기장의 강도가 약해지기 때문에 도금 개시 시점이 늦어지는 등 백금(Pt)의 증착 속도가 현저하게 저하되어 막의 두께가 얇아진다. 그러므로 0.10㎛ 이하의 디자인 룰(Design Rule)을 갖는 소자의 제조시 종래의 방법을 적용하면 셀당 요구되는 충분한 정전용량을 확보할 수 없게 된다.In addition, to form a platinum (Pt) layer by electroplating, after forming a seed layer, a dummy pattern is formed to expose a seed layer of a selected portion, and platinum (Pt) is deposited on the exposed seed layer. . However, at this time, since the strength of the electric field is weakened locally in the presence of contaminants and particles, the deposition rate of platinum (Pt) is remarkably lowered and the thickness of the film becomes thinner. Therefore, if a conventional method is applied in manufacturing a device having a design rule of 0.10 μm or less, sufficient capacitance required per cell may not be secured.

따라서 본 발명은 시드층을 형성한 후 표면에 존재하는 오염물이나 파티클을 제거하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속전극 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal electrode of a semiconductor device capable of solving the above-mentioned disadvantages by removing contaminants or particles present on the surface after forming the seed layer.

도 1a 내지 도 1h는 본 발명을 이용한 캐패시터 제조 방법을 설명하기 위한 단면도.1A to 1H are cross-sectional views illustrating a method of manufacturing a capacitor using the present invention.

도 2a 및 도 2b는 도 1f를 설명하기 위한 확대 단면도.2A and 2B are enlarged cross-sectional views for explaining FIG. 1F.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

1: 반도체 기판 2: 접합부1: Semiconductor Substrate 2: Junction

3: 절연막 4: 반사 방지막3: insulating film 4: antireflection film

5: 콘택홀 6: 플러그5: contact hole 6: plug

7: 금속 실리사이드층 8: 베리어 금속층7: metal silicide layer 8: barrier metal layer

9: 시드층 10: 절연막 패턴9: seed layer 10: insulating film pattern

11: 금속 12: 유전체막11: metal 12: dielectric film

13: 상부전극 14: 오염물 또는 파티클13: upper electrode 14: contaminant or particle

본 발명에 따른 반도체 소자의 금속전극 형성 방법은 접합부가 형성된 반도체 기판상에 절연막 및 반사 방지막을 순차적으로 형성한 후 접합부가 노출되도록 반사 방지막 및 절연막을 패터닝하여 콘택홀을 형성하는 단계와, 콘택홀내에 플러그를 형성한 후 플러그상에 금속 실리사이드층을 형성하는 단계와, 금속 실리사이드층상에 베리어 금속층을 형성한 후 전체 상부면에 금속 시드층을 형성하고 플러그 상부의 시드층이 노출되도록 시드층상에 절연막 패턴을 형성하는 단계와, 노출된 부분의 시드층 표면에 존재하는 유기질의 오염물 및 파티클을 제거한 후 노출된 드층상에 금속을 증착하는 단계와, 절연막 패턴을 제거한 후 노출된 부분의 시드층을 제거하는 단계로 이루어진다.In the method of forming a metal electrode of a semiconductor device according to the present invention, the method may include forming a contact hole by sequentially forming an insulating film and an antireflection film on a semiconductor substrate on which a junction is formed, and then patterning the antireflection film and the insulating film to expose the junction, and forming a contact hole. Forming a metal silicide layer on the plug after forming the plug therein; forming a barrier metal layer on the metal silicide layer, forming a metal seed layer on the entire top surface thereof, and forming an insulating layer on the seed layer to expose the seed layer on the plug. Forming a pattern, removing organic contaminants and particles on the exposed seed layer surface, depositing a metal on the exposed de-layer, removing the insulating layer pattern, and then removing the exposed seed layer It consists of steps.

상기 플러그는 도프트 폴리실리콘으로 이루어지며, 리세스 구조로 형성되고, 상기 금속 실리사이드층은 상기 플러그를 형성한 후 세정 공정을 실시하는 단계와, 전체 상부면에 금속을 증착한 후 열처리하여 상기 플러그와의 반응에 의해 금속 실리사이드층이 형성되도록 하는 단계와, 반응되지 않고 잔류된 금속을 제거하는 단계에 의해 형성된다.The plug is made of doped polysilicon, is formed of a recess structure, the metal silicide layer is formed by the step of performing a cleaning process after forming the plug, depositing the metal on the entire upper surface and heat-treated the plug Forming a metal silicide layer by a reaction with and removing a metal remaining unreacted.

상기 금속 시드층은 백금(Pt), 루테늄(Ru), 이리듐(Ir), 오스미움(Os), 텅스텐(W), 몰리브데늄(Mo), 코발트(Co), 니켈(Ni), 금(Au) 또는 은(Ag)을 이용한 단일막 또는 합금막으로 이루어지며, 상기 유기질의 오염물 및 파티클은 H2SO4, H2SO4/H2O2, HF/H2O 또는 HF/HN4F의 혼합용액으로 제거된다.The metal seed layer is platinum (Pt), ruthenium (Ru), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), gold ( Au) or a single layer or an alloy layer using silver (Ag), and the organic contaminants and particles are H 2 SO 4 , H 2 SO 4 / H 2 O 2 , HF / H 2 O or HF / HN 4 It is removed by the mixed solution of F.

또한, 상기 금속은 전기 도금법으로 증착되며, 백금(Pt)으로 이루어진다.In addition, the metal is deposited by electroplating and is made of platinum (Pt).

그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Next, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1h는 본 발명을 이용한 캐패시터 제조 방법을 설명하기 위한 단면도로서, 도 2a 및 도 2b를 참조하여 설명하면 다음과 같다.1A to 1H are cross-sectional views illustrating a capacitor manufacturing method using the present invention, which will be described below with reference to FIGS. 2A and 2B.

도 1a는 접합부(2)가 형성된 반도체 기판(1)상에 절연막(3) 및 반사방지막(4)을 순차적으로 형성한 후 상기 접합부(2)가 노출되도록 상기 반사 방지막(4) 및 절연막(3)을 패터닝하여 콘택홀(5)을 형성한 상태의 단면도로서, 상기 절연막(2)은 실리콘 산화물(SiO2)로 형성하며, 상기 반사 방지막(4)은 실리콘 산화물(SiO2)과의 식각 선택비가 우수한 질화물(SiON)을 이용하여 300 내지 1000Å의 두께로 형성한다.FIG. 1A illustrates that the insulating film 3 and the antireflection film 4 are sequentially formed on the semiconductor substrate 1 on which the junction part 2 is formed, and then the antireflection film 4 and the insulating film 3 are exposed so that the junction part 2 is exposed. Is a cross-sectional view of the contact hole 5 formed by patterning the insulating film 2, and the insulating film 2 is formed of silicon oxide (SiO 2 ), and the anti-reflection film 4 is selected for etching with silicon oxide (SiO 2 ). It is formed to a thickness of 300 to 1000 하여 using a nitride (SiON) excellent ratio.

도 1b는 화학기상증착(CVD)법으로 상기 콘택홀(5)이 매립되도록 전체 상부면에 도프트(Doped) 폴리실리콘을 500 내지 3000Å의 두께로 증착한 후 소정 두께, 예를들어 250 내지 1500Å 정도를 에치백(Etch Back)하여 상기 콘택홀(5)내에 리세스(Recess) 구조의 플러그(Plug; 6)가 형성되도록 한 상태의 단면도이다.Figure 1b is a predetermined thickness, for example 250 to 1500Å after depositing a doped polysilicon to a thickness of 500 to 3000Å over the entire upper surface so that the contact hole (5) is buried by chemical vapor deposition (CVD) method It is sectional drawing of the state which etched back and the recess 6 formed in the contact hole 5 is formed.

도 1c는 세정 공정을 실시한 후 전체 상부면에 티타늄(Ti)과 같은 금속을 100 내지 300Å의 두께로 증착하고 열처리하여 상기 플러그(6)를 이루는 폴리실리콘과 금속의 반응에 의해 상기 플러그(6)상에 티타늄 실리사이드(TiSix)와 같은 금속 실리사이드층(7)이 형성되도록 한 다음 반응되지 않고 잔류되는 금속을 습식 방법으로 제거한 상태의 단면도로서, 상기 금속 실리사이드층(7)에 의해 상기 플러그(6)와 상부에 형성될 베리어 금속층과의 접촉저항이 감소된다.FIG. 1C illustrates that the plug 6 is formed by a reaction between polysilicon and a metal forming the plug 6 by depositing and heat-treating a metal such as titanium (Ti) to a thickness of 100 to 300 kPa on the entire upper surface after the cleaning process. A cross-sectional view showing a metal silicide layer 7 such as titanium silicide (TiSix) formed on the surface, and then removing the metal that remains unreacted by a wet method, wherein the plug 6 is formed by the metal silicide layer 7. And the contact resistance with the barrier metal layer to be formed on top is reduced.

도 1d는 전체 상부면에 베리어 금속층(8)을 형성한 후 화학적 기계적 연마(CMP) 방법으로 상기 반사 방지막(4)이 노출될 때까지 상기 베리어 금속층(8)을 연마하여 상기 금속 실리사이드층(7)상에만 소정 두께의 베리어 금속층(8)이 잔류되도록 한 상태의 단면도로서, 상기 베리어 금속층(8)은 TiSiN, TiAlN, TaSiN 또는 TaAlN으로 이루어지며, 물리기상증착(PVD) 또는 화학기상증착(CVD)법으로 형성된다.1D shows that the barrier metal layer 8 is formed by forming the barrier metal layer 8 on the entire upper surface, and then polishing the barrier metal layer 8 until the antireflection film 4 is exposed by chemical mechanical polishing (CMP). Is a cross-sectional view of the barrier metal layer 8 having a predetermined thickness remaining only on the top surface), wherein the barrier metal layer 8 is formed of TiSiN, TiAlN, TaSiN, or TaAlN, and physical vapor deposition (PVD) or chemical vapor deposition (CVD). It is formed by the method.

도 1e는 백금(Pt), 루테늄(Ru), 이리듐(Ir), 오스미움(Os), 텅스텐(W), 몰리브데늄(Mo), 코발트(Co), 니켈(Ni), 금(Au) 또는 은(Ag)과 같은 금속을 이용하여 전체 상부면에 시드층(9)을 50 내지 1000Å의 두께로 형성한 후 상기 플러그(6) 상부의 시드층(9)이 노출되도록 상기 시드층(9)상에 절연막 패턴(10)을 형성한 상태의 단면도로서, 상기 절연막 패턴(10)은 감광막, PSG 또는 USG 산화막으로 형성되며, 5000 내지 10000Å의 두께로 형성된다.1E shows platinum (Pt), ruthenium (Ru), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), and gold (Au) Alternatively, the seed layer 9 may be formed on the entire upper surface by using a metal such as silver (Ag) to a thickness of 50 to 1000 mm 3, and then the seed layer 9 may be exposed to expose the seed layer 9 on the plug 6. ) Is a cross-sectional view of the insulating film pattern 10 formed thereon, wherein the insulating film pattern 10 is formed of a photosensitive film, a PSG or USG oxide film, and has a thickness of 5000 to 10000 kPa.

도 1f는 4 내지 100℃의 온도 및 0.1 내지 90%의 농도를 갖는 황산(H2SO4), H2SO4/H2O2의 혼합용액, HF/H2O의 혼합용액 또는 HF/HN4F의 혼합용액에 2 내지 3600초(Sec)동안 디핑(Dipping)하거나, 상기 혼합용액에 순차적으로 디핑하여 노출된 부분의 시드층(9) 표면에 존재하는 유기질의 오염물이나 파티클을 제거한 후 전기 도금법으로 노출된 상기 시드층(9)상에 백금(Pt)과 같은 금속(11)을 3000 내지 10000Å의 두께로 증착한 상태의 단면도로서, 황산(H2SO4) 용액을 이용한 표면처리에 의해 도 2a에 도시된 바와 같이 오염물이나 파티클(14)의 제거 또는 크기 감소가 이루어져 시드층(9)과의 접촉 각도(θ2)가 현저하게 감소되고, 이에 따라 금속의 증착 두께 및 속도가 균일해 진다. 도 2a에는 오염물이나 파티클(14)이 존재하는 상태에서 시드층(9)과의 접촉 각도(θ1)가 도시된다.1F shows sulfuric acid (H 2 SO 4 ), a mixed solution of H 2 SO 4 / H 2 O 2 , a mixed solution of HF / H 2 O or HF / having a temperature of 4 to 100 ° C. and a concentration of 0.1 to 90%. Dipping for 2 to 3600 seconds (Sec) in the mixed solution of HN 4 F or sequentially dipping in the mixed solution to remove organic contaminants or particles on the surface of the exposed seed layer (9) A cross-sectional view of a metal 11 such as platinum (Pt) deposited at a thickness of 3000 to 10000 kPa on the seed layer 9 exposed by the electroplating method, for surface treatment using a sulfuric acid (H 2 SO 4 ) solution. As a result, as shown in FIG. 2A, contaminants or particles 14 are removed or reduced in size, thereby significantly reducing the contact angle θ2 with the seed layer 9, thereby making the deposition thickness and speed of the metal uniform. Lose. 2A shows the contact angle θ1 with the seed layer 9 in the presence of contaminants or particles 14.

상기 전기 도금법을 이용한 금속 증착시 직류(DC), 펄스(Pulse) 또는 펄스리버스(Pulse Reverse) 방식의 전압이 인가되며, 전류밀도는 0.1 내지 10㎃/㎠가 되도록 한다.When the metal is deposited using the electroplating method, a DC, pulse, or pulse reverse type voltage is applied, and the current density is 0.1 to 10 mA / cm 2.

도 1g는 습식 식각 방법으로 상기 절연막 패턴(10)을 제거한 후 하부전극간의 절연을 위하여 노출된 시드층(9)을 전면 식각(Blanket Etch Back)하여 제거한 상태의 단면도로서, 상기 플러그(6)상에 금속 실리사이드층(7), 베리어 금속층(8), 시드층(9) 및 금속(11)이 적층된 구조의 하부전극이 완성된다.FIG. 1G is a cross-sectional view of the seed layer 9 exposed through a blanket etching process to remove the insulating layer pattern 10 by a wet etching method and to remove the exposed seed layer 9 for insulation between lower electrodes. The lower electrode of the structure in which the metal silicide layer 7, the barrier metal layer 8, the seed layer 9 and the metal 11 are laminated is completed.

도 1h는 400 내지 600℃의 온도에서 전체 상부면에 유전체막(12)을 150 내지 500Å의 두께로 형성한 후 결정화시키기 위하여 500 내지 700℃의 온도 및 질소 분위기에서 30 내지 180초(Sec)동안 급속 열처리(RTP)하고 상기 유전체막(12)상에 상부전극(13)을 형성한 상태의 단면도로서, 상기 유전체막(12)은 BST 등과 같은 고유전체로 형성하며, 상기 상부전극(13)은 백금(Pt)과 같은 금속을 이용하여 화학기상증착(CVD)법으로 형성한다.FIG. 1H shows that the dielectric film 12 is formed on the entire upper surface at a temperature of 400 to 600 ° C. to a thickness of 150 to 500 μs, and then 30 to 180 seconds (Sec) at a temperature of 500 to 700 ° C. and a nitrogen atmosphere to crystallize A cross-sectional view of a state in which the upper electrode 13 is formed on the dielectric film 12 after rapid heat treatment (RTP), wherein the dielectric film 12 is formed of a high dielectric material such as BST, and the upper electrode 13 is It is formed by chemical vapor deposition (CVD) using a metal such as platinum (Pt).

상술한 바와 같이 본 발명은 시드층을 형성한 후 황산(H2SO4) 용액을 이용하여 표면에 존재하는 오염물이나 파티클을 제거하고 금속을 도금하므로써 금속의 도금 속도 및 두께가 균일해 진다. 그러므로 하부전극의 두께가 균일해져 유효 표면적이 안정적으로 유지되며, 이에 따라 0.10㎛ 이하의 디자인 룰을 갖는 고집적 소자의 캐패시터 제조가 가능해 진다.As described above, the present invention forms a seed layer and removes contaminants or particles on the surface using a sulfuric acid (H 2 SO 4 ) solution and plate the metal to uniform the plating speed and thickness of the metal. Therefore, the thickness of the lower electrode is uniform, so that the effective surface area is stably maintained, thereby enabling the manufacture of a capacitor of a highly integrated device having a design rule of 0.10 μm or less.

Claims (11)

접합부가 형성된 반도체 기판상에 절연막 및 반사 방지막을 순차적으로 형성한 후 상기 접합부가 노출되도록 상기 반사 방지막 및 절연막을 패터닝하여 콘택홀을 형성하는 단계와,Forming a contact hole by sequentially forming an insulating film and an anti-reflection film on the semiconductor substrate on which the junction is formed, and then patterning the anti-reflection film and the insulating film to expose the junction; 상기 콘택홀내에 플러그를 형성한 후 상기 플러그상에 금속 실리사이드층을 형성하는 단계와,Forming a metal silicide layer on the plug after forming the plug in the contact hole; 상기 금속 실리사이드층상에 베리어 금속층을 형성한 후 전체 상부면에 금속 시드층을 형성하고 상기 플러그 상부의 시드층이 노출되도록 상기 시드층상에 절연막 패턴을 형성하는 단계와,Forming a barrier metal layer on the metal silicide layer, forming a metal seed layer on an entire top surface thereof, and forming an insulating layer pattern on the seed layer to expose the seed layer on the plug; 노출된 부분의 시드층 표면에 존재하는 유기질의 오염물 및 파티클을 제거한 후 노출된 상기 시드층상에 금속을 증착하는 단계와,Depositing a metal on the exposed seed layer after removing organic contaminants and particles present on the surface of the exposed seed layer; 상기 절연막 패턴을 제거한 후 노출된 부분의 상기 시드층을 제거하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.And removing the seed layer of the exposed portion after removing the insulating film pattern. 제 1 항에 있어서,The method of claim 1, 상기 플러그는 도프트 폴리실리콘으로 이루어지며, 리세스 구조로 형성된 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The plug is made of doped polysilicon, the metal electrode forming method of a semiconductor device, characterized in that formed in the recess structure. 제 1 항에 있어서,The method of claim 1, 상기 금속 실리사이드층은 상기 플러그를 형성한 후 세정 공정을 실시하는 단계와,The metal silicide layer may be subjected to a cleaning process after forming the plug; 전체 상부면에 금속을 증착한 후 열처리하여 상기 플러그와의 반응에 의해 금속 실리사이드층이 형성되도록 하는 단계와,Depositing a metal on the entire upper surface and then performing heat treatment to form a metal silicide layer by reaction with the plug; 반응되지 않고 잔류된 금속을 제거하는 단계에 의해 형성되는 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.Forming a metal electrode of a semiconductor device, characterized in that formed by the step of removing the metal remaining unreacted. 제 3 항에 있어서,The method of claim 3, wherein 상기 금속은 티타늄인 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The metal is a metal electrode forming method of a semiconductor device, characterized in that the titanium. 제 1 항에 있어서,The method of claim 1, 상기 베리어 금속층은 TiSiN, TiAlN, TaSiN 및 TaAlN중 어느 하나의 금속으로 이루어진 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The barrier metal layer is a metal electrode forming method of a semiconductor device, characterized in that made of any one of TiSiN, TiAlN, TaSiN and TaAlN metal. 제 1 항에 있어서,The method of claim 1, 상기 금속 시드층은 백금(Pt), 루테늄(Ru), 이리듐(Ir), 오스미움(Os), 텅스텐(W), 몰리브데늄(Mo), 코발트(Co), 니켈(Ni), 금(Au) 및 은(Ag)중 어느 하나의 금속으로 이루어지며, 단일막 및 합금막중 어느 하나의 형태로 형성된 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The metal seed layer is platinum (Pt), ruthenium (Ru), iridium (Ir), osmium (Os), tungsten (W), molybdenum (Mo), cobalt (Co), nickel (Ni), gold ( Au) and silver (Ag), the metal electrode forming method of a semiconductor device, characterized in that formed in any one of a single film and an alloy film. 제 1 항에 있어서,The method of claim 1, 상기 절연막 패턴은 감광막 및 산화막중 어느 하나의 물질로 이루어진 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The insulating layer pattern is a metal electrode forming method of a semiconductor device, characterized in that made of any one material of the photosensitive film and the oxide film. 제 1 항에 있어서,The method of claim 1, 상기 유기질의 오염물 및 파티클은 H2SO4, H2SO4/H2O2, HF/H2O 및 HF/HN4F중 어느 하나의 화학용액으로 제거되는 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The organic contaminants and particles of the semiconductor device, characterized in that removed by the chemical solution of any one of H 2 SO 4 , H 2 SO 4 / H 2 O 2 , HF / H 2 O and HF / HN 4 F Electrode formation method. 제 8 항에 있어서,The method of claim 8, 상기 화학용액은 4 내지 100℃의 온도로 유지되며, 0.1 내지 90%의 농도를 갖는 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The chemical solution is maintained at a temperature of 4 to 100 ℃, the metal electrode forming method of a semiconductor device, characterized in that having a concentration of 0.1 to 90%. 제 1 항에 있어서,The method of claim 1, 상기 금속은 전기 도금법으로 증착되는 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The metal is a metal electrode forming method of a semiconductor device, characterized in that the deposition by electroplating method. 제 10 항에 있어서,The method of claim 10, 상기 금속은 백금(Pt)인 것을 특징으로 하는 반도체 소자의 금속전극 형성 방법.The metal is a metal electrode forming method of a semiconductor device, characterized in that the platinum (Pt).
KR1020000043958A 1999-12-27 2000-07-29 Method for forming a metal electrode of a semiconductor device KR20020010308A (en)

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US09/735,528 US6451666B2 (en) 1999-12-27 2000-12-14 Method for forming a lower electrode by using an electroplating method
JP2000396570A JP2001210806A (en) 1999-12-27 2000-12-27 Method for forming lower electrode by utilizing electroplating
DE10065350A DE10065350B4 (en) 1999-12-27 2000-12-27 A method of manufacturing a semiconductor device with a capacitor using an electroplating method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669663B1 (en) * 2005-06-27 2007-01-15 동부일렉트로닉스 주식회사 Method for forming contact hole of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669663B1 (en) * 2005-06-27 2007-01-15 동부일렉트로닉스 주식회사 Method for forming contact hole of semiconductor device

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