JPH11233732A - Thin film capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture, while maintaining the good film quantity and crystal conduction on a Si substrate, a ferroelectric thin film which has generated ferroelectric property utilizing the epitaxial effect and a capacitor using a high dielectric coefficient film which has increased dielectric coefficient with the epitaxial effect. SOLUTION: In a thin film capacitor 7, a metal silicide layer 2 consisting of silicide of at least one element selected from Ni, Co, Mn, Ru, Pd, Cr, Y, Er and Ir is directly grown on the Si substrate 1 by the epitaxial growth method and a barrier layer 6 consisting of TiN or solid-solution of TiN and Mn (M: Al, V, Mo, Nb, Ta) or a fist electrode layer 3 is grown by the epitaxial growth method on the metal silicide layer 2. Moreover, on the first electrode layer 3, a dielectric material film 4 consisting of dielectric material having the Perovskite type crystal structure is grown by the epitaxial growth method and moreover the second electrode layer 5 is formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor having a dielectric film made of a dielectric material having a perovskite crystal structure.

[0002]

2. Description of the Related Art Recently, a storage device (ferroelectric memory (FRAM)) using a ferroelectric thin film as a storage medium has been developed, and a part thereof has already been put to practical use. A ferroelectric memory is non-volatile, so that its memory contents are not lost even after the power is turned off.Furthermore, when the ferroelectric thin film is thin enough, the spontaneous polarization inversion is fast, and writing and writing can be performed at a high speed like DRAM. It has features such as being readable. In addition, since a 1-bit memory cell can be manufactured using one transistor and one ferroelectric capacitor, it is suitable for increasing the capacity.

Here, the ferroelectric film used for the ferroelectric memory has characteristics such as a large remanent polarization, a small temperature dependence of the remanent polarization, and a capability of maintaining the remanent polarization for a long time (retention). It is required to have.

At present, as a ferroelectric material, mainly lead zirconate titanate (Pb (Zr, Ti) O ₃ (PZ
T)) is used. However, although PZT has a high Curie temperature (300 ° C. or higher) and a large spontaneous polarization, diffusion and evaporation of lead, which is a main component, tend to occur at relatively low temperatures (about 500 ° C.). Based on this, it is said that it is difficult to respond to miniaturization.

Other than PZT, barium titanate (BaT)
iO ₃ (BTO)) is known as a typical ferroelectric. BTO has a perovskite crystal structure like PZT, and has a Curie temperature of about 393K. Compared to Pb, Ba is less likely to evaporate, and when crystallized, has the characteristic that it hardly takes a crystal structure other than the perovskite type. However, the BTO has P
Compared to ZT, it has the drawback that the remanent polarization is small and the Curie temperature is low, so that the temperature dependence of the remanent polarization is large. For these reasons, application to ferroelectric memories is being studied very much. Absent.

On the other hand, the present inventors have previously made strontium titanate (SrTiO ₃ (ST
O)) A single crystal, for example, strontium ruthenate (SrRuO ₃ (SRO)) as a lower electrode, and barium strontium titanate (Ba _x Sr _1-x TiO) having a lattice constant slightly larger than SRO as a dielectric.
₃ It has been found that the c-axis length of BSTO can be artificially controlled by selecting (BSTO) and epitaxially growing all of them (see JP-A-8-139292).

As a result, by using the BSTO having a Ba-rich composition, the ferroelectric Curie temperature is shifted to a high temperature side, a large remanent polarization is exhibited in a room temperature region, and 85 ° C.
It has been confirmed that a ferroelectric film suitable for FRAM, which can maintain a sufficiently large remanent polarization even when the temperature is raised to a certain degree, can be realized. Similarly, by using BSTO having a Sr-rich composition, a thin film having a dielectric constant of 800 or more, which is several times the dielectric constant of approximately 200 at a film thickness of 20 nm, for example, when a capacitor is manufactured using a polycrystalline film. It has been experimentally confirmed that a capacitor can be manufactured and dielectric characteristics suitable for a DRAM can be realized. A semiconductor memory such as an FRAM or a DRAM can be formed by using a thin film capacitor having a dielectric film grown epitaxially as described above, and their practical application is expected.

[0008]

By the way, in order to put it to practical use as a semiconductor memory, it is necessary to manufacture an epitaxial capacitor on a Si substrate instead of an STO substrate which can only obtain a substrate having a diameter of at most about 20 mm. Is required. However, Si substrate (a ₀ = 0.543 nm) and SRO
And BSTO (a ₀ = 0.39 to 0.40 nm) have a large lattice mismatch, and the Si substrate is easily oxidized. Therefore, it is not possible to produce an epitaxial film with good film quality on a Si substrate. Very difficult.

The present inventors have reported the application of a (Ti, Al) N epitaxial barrier layer in which AIN is dissolved in TiN to solve the above problem (IE
EE-IEDM 1996 Technical Digest pp.695-698). TiN
Has a lattice constant of 0.423 nm, and the lattice constant when AlN is dissolved in 30% as a solid solution is about 0.421 nm, which has a large lattice mismatch with Si, but causes epitaxial growth in the same orientation.

However, at the interface between Si and (Ti, Al) N, one dislocation having a density of approximately one is introduced into the Si3 lattice, which corresponds to lattice mismatch. For this reason, even when the film is formed under optimum conditions, the half width of the rocking curve in X-ray diffraction of (Ti, Al) N becomes as large as 1 ° or more, and the half width of SRO or BSTO grown thereon also becomes 1%.゜ or more. Such disorder in crystallinity causes deterioration of dielectric properties.

The present invention has been made to address such a problem, and has been made in view of a ferroelectric thin film exhibiting ferroelectricity by utilizing an epitaxial effect, or a high dielectric constant in which a dielectric constant is increased by an epitaxial effect. It is an object of the present invention to provide a thin film capacitor capable of manufacturing a capacitor using a dielectric constant thin film on a Si substrate, which is indispensable for practical use as a semiconductor memory, while maintaining good film quality and crystalline state. .

[0012]

According to a first aspect of the present invention, there is provided a thin film capacitor comprising: a silicon substrate;
i, Co, Mn, Ru, Pd, Cr, Y, Er and I
and a silicide of at least one element selected from the group consisting of: a metal silicide layer directly epitaxially grown on the silicon substrate; a first electrode layer epitaxially grown on the metal silicide layer; It is characterized by comprising a dielectric film epitaxially grown thereon and a second electrode layer formed on the dielectric film.

According to a second aspect of the present invention, in the thin film capacitor, the metal silicide layer and the first
TiN or TiN and MN
(Where M represents at least one element selected from the group consisting of Al, V, Mo, Nb and Ta), and the barrier layer is epitaxially grown on the metal silicide layer. It is characterized by:

The thin film capacitor of the present invention is particularly effective when the dielectric film is made of a dielectric material having a perovskite type crystal structure, for example, as described in claim 3.

In the thin film capacitor of the present invention, first, a metal silicide layer is epitaxially grown on a silicon substrate. Since metal silicide has substantially the same lattice constant as silicon, a high-quality epitaxial film can be formed on a silicon substrate. As described above, once an epitaxial metal film (metal silicide layer) having good film quality can be formed on a silicon substrate, an epitaxial metal film having a different lattice constant can be formed thereon with good film quality. That is, even if there is a difference in lattice constant between the metal silicide layer and the first electrode layer or the barrier layer, a high-quality epitaxial film can be formed as the first electrode layer or the barrier layer.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing the configuration of an embodiment of the thin film capacitor of the present invention. In FIG. 1, reference numeral 1 denotes a silicon (Si) substrate, and this Si substrate 1 may have a plug made of polysilicon, tungsten, or the like.

On the Si substrate 1, nickel (Ni), cobalt (Co), manganese (Mn), ruthenium (R)
u), palladium (Pd), chromium (Cr), yttrium (Y), erbium (Er) and iridium (I
A metal silicide layer 2 made of a silicide of one or more elements selected from r) is formed. This metal silicide layer 2 is formed by direct epitaxial growth on the Si substrate 1. The thickness of the metal silicide layer 2 is preferably, for example, about 5 to 20 nm.

On the metal silicide layer 2, a first electrode layer (lower electrode) 3 having a thickness of about 5 to 20 nm is formed as shown in FIG. 1, for example. This first electrode layer 3
Is epitaxially grown on the metal silicide layer 2, and a dielectric film 4 having a thickness of about 20 to 100 nm, which is epitaxially grown on the first electrode layer 3, is formed thereon. On this dielectric film 4, a second electrode layer (upper electrode) 5 having a thickness of about 10 to 30 nm is formed. Preferably, the second electrode layer 5 is also epitaxially grown on the dielectric film 4 to form an all-epitaxial capacitor.

Between the metal silicide layer 2 and the first electrode layer 3, for example, as shown in FIG.
TiN and MN such as _1-x Al _x N (where M is Al,
And at least one element selected from V, Mo, Nb and Ta). In this case, the barrier layer 6 is epitaxially grown on the metal silicide layer 2, and the first electrode layer 3 is epitaxially grown on the barrier layer 6.

As a constituent material of the dielectric film 4, a dielectric material having a perovskite crystal structure is preferable. As such a dielectric material, a perovskite-type oxide represented by ABO ₃ may be mentioned. In particular, BaTiO ₃ (B
TO) as a main component, and part of the A-site element (Ba) is replaced by an element such as Sr or Ca, and part of the B-site element (Ti) is replaced by an element such as Zr, Hf, or Sn. The perovskite oxide described above is preferably used. S
A-site substitution with r, Ca, or the like contributes to improvement of ferroelectricity and dielectric constant, improvement of Curie temperature, and the like. The substitution amount of the A-site element is preferably set to 95 mol% or less. B-site substitution with Zr, Hf, Sn, or the like contributes to a reduction in coercive electric field and the like. The substitution amount of the B site element is preferably set to 90 mol% or less.

A perovskite oxide containing BTO as a main component and partially substituting a B-site element and an A-site element is as follows:
It becomes a ferroelectric or paraelectric depending on the substitution amount of the B-site element and the A-site element, and furthermore, the strain amount. Therefore, by appropriately setting the composition and strain amount of the perovskite oxide, a dielectric film suitable for the intended use of the thin film capacitor can be obtained. For example, Ba _x Sr _1-x TiO
_In the case of ₃ (BSTO), ferroelectricity is exhibited when the molar fraction x of Ba is in the range of 0.30 to 1. On the other hand, the molar fraction of Ba x
Is paraelectric in the range of 0 to 0.3. These are B
It changes depending on the substitution amount of the site element.

The B site element is Ti, Sn, Zr,
Hf and a perovskite-type oxide composed of a solid solution thereof, and further, Mg _1/3 Ta _2/3 , Mg _1/3 Nb _2/3 ,
Complex oxides such as Zn _1/3 Nb _2/3 and Zn _1/3 Ta _2/3 and perovskite-type oxides composed of a solid solution thereof may be used. At this time, as the A-site element, Ba and a part thereof replaced with an element such as Sr or Ca are applied.

The dielectric film 4 is not limited to the above-mentioned BSTO or the like, and various perovskite oxides having a function as a ferroelectric or paraelectric may be used according to the purpose of use of the thin film capacitor. Can be. For example, when applied to FRAM, Pb (Zr, Ti)
O ₃ (PZT), (Pb, La) (Zr, Ti) O
₃ (PLZT), Bi-Sr-Ta-O, Bi-Sr-
A ferroelectric perovskite oxide such as Ti—O can be used. When applied to a capacitor of a DRAM, a high dielectric perovskite oxide such as SrTiO ₃ (STO) can be used.

The lower electrode 2 has various lattice constants similar to those of a dielectric material having a perovskite type crystal structure as described above, for example, and can be epitaxially grown on the metal silicide layer 2 and the barrier layer 6. Conductive materials such as SrRuO ₃ , CaRuO ₃ , BaRu
O ₃ and their solid solution systems, SrΜO ₃ , BaΜO
₃ , CaΜOO ₃ and their solid solution system, LaSrCu
A conductive perovskite oxide such as O ₃ is used. Further, Pt, Au, Pd, Ir, Rh, Re, R
It is also possible to form the lower electrode 2 from a noble metal such as u, or an alloy or oxide thereof.

The upper electrode 5 is not particularly limited, but is preferably made of the same conductive perovskite oxide or noble metal (including alloys and oxides) as the lower electrode 2.

The components described above constitute the thin film capacitor 7 of this embodiment. The thin film capacitor 7 is used, for example, as a charge storage unit (storage medium) of an FRAM (ferroelectric memory (non-volatile memory)) or a charge storage unit (storage medium) of a DRAM having an increased dielectric constant. It should be noted that the specific device structure of the thin film capacitor 7 is not particularly limited, and may be any structure such as a planar type, a stack type, and an internal trench type.

Here, in order to form a perovskite-based epitaxial capacitor having excellent dielectric properties on the Si substrate 1, the lattice constant of perovskite (about 0.40 nm) and the lattice constant of Si (0.543 nm) are required. It is important to overcome large differences and improve the film quality of epitaxial capacitors. Therefore, in the present invention, a metal silicide layer 2 having a lattice constant substantially equal to that of Si is first epitaxially grown, and an oxide layer or a noble metal layer (3), which is a lattice mismatch system between metals, is formed on the metal silicide layer 2 or It is characterized in that the nitride layer (6) is epitaxially grown.

This is because Si, which is a semiconductor, has directionality in bonding and has a bond called dangling bond on the surface, so that the interface of Si is very sensitive to lattice matching. Therefore, when a material that does not lattice match is formed on the Si substrate 1, it is very difficult to obtain a film having good crystallinity even if epitaxial growth occurs. This is because Si bonds are too large depending on the degree of lattice mismatch to form dislocations having a large energy at the interface, thereby disturbing the crystallinity of the epitaxial layer.

For example, TiN (lattice constant =
When an epitaxial film (0.423 nm) is formed, almost one dislocation per Si 3 lattice is observed at the interface with Si. For this reason, it is very difficult for the half width of the rocking curve in XRD measurement, which is one index indicating disorder of crystallinity, to fall below 1 ° even when epitaxial growth is performed. On the other hand, some of the metal silicides have a lattice constant almost identical to that of Si, and a high-quality epitaxial film can be formed. Table 1 shows examples of metal silicides that can form an epitaxial film on a Si substrate.

[0031]

[Table 1] By using a metal silicide as shown in Table 1, it is possible to form a flat epitaxial film having excellent crystallinity and a flat quality on the Si substrate 1 such as a rocking curve having a half width of 0.1 ° or less. Becomes possible. Here, the metal silicide to be used preferably has a lattice mismatch with Si of 10% or less, and more preferably a metal silicide with a lattice mismatch of 5% or less with Si. For this reason, silicide such as Ni, Co, Mn, and Ru, Si (111)
Ni, Co, Cr, Ir, Pd, Y, Er
It is preferable to use a silicide such as Metal silicide is not limited to those having a stoichiometric composition, such as MSi _2, but can be used as long as it can be expressed by MSi _x,
In particular, it is preferable to use a stoichiometric metal silicide.

As described above, once an epitaxial metal film of good film quality (metal silicide layer 2) can be formed on the Si substrate 1, an epitaxial metal film having a different lattice constant is formed thereon with good film quality. It is possible to do. This is because there is no direction in metal bonding,
Since the interface is much flatter electronically than a semiconductor, the interface energy and interface dislocation energy are small.
For this reason, in the case of a metal film, an epitaxial film having much better film quality can be formed even if a lattice constant mismatch exists, as compared with that between a semiconductor and a metal.

On the metal silicide layer 2, a barrier made of nitride such as TiN is used as a material that can be epitaxially grown thereon and can withstand an oxidizing atmosphere when an oxide-based epitaxial capacitor is manufactured. Preferably, layer 6 is formed. The first electrode layer 3 made of a conductive perovskite oxide or the like can be directly formed on the metal silicide 2. However, in order to prevent the metal silicide layer 2 from being oxidized, a barrier layer made of a nitride is used. 6 is preferably formed.

Another advantage of using the Si / epitaxial silicide / epitaxial nitride film structure instead of the Si / epitaxial nitride film structure is that the contact resistance with the Si substrate 1 is extremely small. No. This is because the height of the Schottky barrier between Si substrate 1 and metal silicide layer 2 is reduced.

As a method of forming the metal silicide layer 2 grown epitaxially, for example, the following method can be mentioned.

(A) Using a material having a silicide composition and heating S by a method such as thermal evaporation, laser evaporation, or sputtering.
An epitaxial film is formed directly on the i-substrate.

(B) Using a material of a metal component of silicide, S is deposited by a method such as thermal evaporation, laser evaporation, or sputtering.
After a metal film is once formed on the i-substrate, it is reacted with Si of the substrate by heat treatment to form an epitaxial silicide film. Alternatively, a metal film is formed and reacted on a heated Si substrate to form an epitaxial silicide film.

(C) After the material of the metal component of silicide is implanted into Si by ion implantation, it reacts with Si of the substrate by heat treatment to form an epitaxial silicide film.

The above three methods have their respective advantages, and it is preferable to select and use them appropriately according to the type of the metal silicide, the constituent material of the other layers, the element structure, and the like.

As a method of forming a nitride film epitaxially grown, for example, the following method can be mentioned, and any film forming method may be used.

(1) Using a nitride composition material, thermal evaporation,
An epitaxial film is formed directly on the silicide layer heated by a method such as laser deposition or sputtering.

(2) Using a metal component material of nitride, an epitaxial film is formed directly on the silicide layer which is heated while reacting with the atmosphere in a nitrogen atmosphere or an ammonia atmosphere by a method such as thermal evaporation, laser evaporation, or sputtering. To form

(3) An epitaxial film is formed directly on the heated silicide layer by thermal CVD or MOCVD.

As described above, according to the present invention, a capacitor using a ferroelectric film or a high dielectric constant film induced by strain introduced during epitaxial growth can be manufactured on a Si substrate with good film quality. it can. Therefore, by highly integrating such a thin film capacitor and a transistor of the present invention on a Si substrate, a highly practical and highly reliable semiconductor memory such as a highly integrated FRAM or DRAM is manufactured. It becomes possible.

[0045]

EXAMPLES Hereinafter, specific examples of the present invention and evaluation results thereof will be described.

COMPARATIVE EXAMPLE 1 First, the surface temperature of the SrTiO ₃ (100) substrate (lattice constant: 0.3905 nm) was measured by RF magnetron sputtering.
At 00 ° C., a 20 nm thick SrRuO ₃ lower electrode (lattice constant 0.391 nm), a 20 nm thick Ba _0.7 Sr _0.3 TiO ₃ ferroelectric film (lattice constant 0.397 nm), and a 30 nm thick SrRuO ₃ upper electrode are sequentially placed at 00 ° C. It was epitaxially grown. SRO and BS
TO: Ar: O ₂ = 4: 1 using an oxide target
Was formed in a mixed gas atmosphere of

X-ray diffraction of the obtained thin film capacitor showed that both SRO and BSTO
It was confirmed that the epitaxial growth was in the (001) orientation. BSTO forms a strained lattice due to a slight difference in lattice constant from the lower electrode, and the c-axis length in the direction perpendicular to the substrate is 0.4
At 12nm, it was 3.8% longer than the bulk. When the rocking curve of the (002) peak of each growth layer was measured to measure the half width, the SRO was 0.11% and the BSTO was 0.12%.

As described above, when the lattice-matching lower electrode and the dielectric film were all formed on the substrate, a multilayer epitaxial film having extremely excellent crystallinity could be obtained. In addition, when the dielectric properties were measured between the upper and lower electrodes, BS
The remanent polarization corresponding to the c-axis length of TO is 25μC /
cm ² was obtained, which was an excellent ferroelectric film.

However, the lattice matching type thin film capacitor using the STO substrate is inferior in practicality as compared with the thin film capacitor of the embodiment using the Si substrate described below.

Example 1 First, as shown in FIG. 2, a 20 nm-thick CoSi ₂ layer 2 (with a lattice constant of 0.5376) was sequentially formed on the surface of a Si (100) substrate 1 (with a lattice constant of 0.543 nm) by RF magnetron sputtering. n
m) a (Ti _0.9 Al _0.1 ) N barrier layer 6 with a thickness of 20 nm
(Lattice constant 0.422 nm), SrRuO ₃ electrode layer (lower electrode) 3 with 20 nm thickness (lattice constant 0.391 nm), Ba with 20 nm thickness
_0.7 Sr _0.3 TiO ₃ ferroelectric film 4 (lattice constant 0.397n
m) An SrRuO ₃ electrode layer (upper electrode) 5 having a thickness of 30 nm was epitaxially grown.

The substrate temperature during film formation was 600 ° C. C
The oSi ₂ layer 2 uses a silicide target and (T
The i, Al) N barrier layer 6 is formed by using a nitride target.
Each was formed in an Ar atmosphere. SRO and B
STO uses an oxide target, and Ar: O ₂ = 4:
Film formation was performed in the mixed gas atmosphere of No. 1.

X-ray diffraction of the obtained thin film capacitor showed that CoSi ₂ , (Ti, Al) N, SRO and BSTO were all epitaxially grown in the (001) direction on the Si substrate surface. confirmed. BSTO
Was 0.411 nm, which was almost the same as the c-axis length on the STO substrate. Further, when the rocking curve of the (002) peak of each growth layer was measured to measure the half width, Co
Si ₂ 0.08 °, (Ti, Al) N is 0.17 °, SRO is
0.21% and BSTO were 0.22%.

As described above, first, a CoSi ₂ film, which is a lattice-matching metal, is directly formed on a Si substrate, which is a semiconductor, to obtain an epitaxial film having good crystallinity. By producing a (Ti, Al) N film as a matching system, it has become possible for the first time to minimize the deterioration of the crystallinity of the epitaxial (Ti, Al) N film. The crystallinity of the SRO and BSTO dielectric films laminated thereon was also very close to that produced on the STO substrate (Comparative Example 1) when all were produced by a lattice matching system. When the dielectric properties were measured between the upper and lower electrodes, a residual polarization of 23 μC / cm ₂ corresponding to the extended c-axis length was obtained, indicating that the film was a good ferroelectric film.

EXAMPLE 2 A CrSi ₂ layer 2 having a thickness of 20 nm, a (Ti _0.9 Al _0.1 ) N barrier layer 6 having a thickness of 20 nm, and a 20 nm film thickness were sequentially formed on the surface of a Si (111) substrate 1 by RF magnetron sputtering. SrR
uO ₃ electrode layer 3, 20 nm thick Ba _0.7 Sr _0.3 TiO ₃
A ferroelectric film 4 and a 30 nm thick SrRuO ₃ electrode layer 5 were epitaxially grown in this order. For the epitaxial silicide film, a (0001) plane of CrSi ₂ having a hexagonal crystal lattice-matched to Si (111) was used.

The substrate temperatures during film formation were all set at 600 ° C. C
The rSi ₂ layer 2 uses a silicide target, and (T
The i, Al) N barrier layer 6 is formed by using a nitride target.
Both films were formed in an Ar atmosphere. SRO and BST
O was formed using an oxide target in a mixed gas atmosphere of Ar: O ₂ = 4: 1.

X-ray diffraction of the obtained thin film capacitor showed that CrSi ₂ was hexagonal (0001) with respect to the substrate surface.
It was confirmed that the orientation, (Ti, Al) N, SRO and BSTO were epitaxially grown in the (111) orientation with respect to the substrate surface. In addition, the BSTO perpendicular to the substrate surface (11
1) The plane spacing was 0.707nm, which was about 2% longer than the bulk value. When the rocking curve of the (111) or (0002) peak perpendicular to the substrate surface of each growth layer was measured to measure the half width, CrSi ₂ was 0.06 ° and (Ti, Al) N
Was 0.13%, SRO was 0.17%, and BSTO was 0.21%.

As described above, also on a Si (111) substrate, a lattice-matched CrSi ₂ film is directly formed to obtain an epitaxial film having good crystallinity, and then a metal-based lattice-matched system is formed on the Si (111) substrate. It can be seen that the fabrication of the (Ti, Al) N film makes it possible to minimize the deterioration of the crystallinity of the epitaxial (Ti, Al) N film.
The SRO and BSTO dielectric (111) films stacked thereon also have very good crystallinity. When the dielectric properties were measured between the upper and lower electrodes, 19 μC / cm ₂ was obtained as the amount of residual polarization corresponding to the length of the extended (111) axis, which was also a good ferroelectric film.

COMPARATIVE EXAMPLE 2 The surface of a Si (100) substrate (lattice constant: 0.543 nm)
At a substrate temperature of 600 ° C. by a magnetron sputtering method, a (Ti _0.9 Al _0.1 ) N barrier layer (lattice constant 0.422 nm)
SrRuO ₃ lower electrode (lattice constant 0.391 nm), Ba _0.7 S
r _0.3 TiO ₃ ferroelectric film (lattice constant 0.397 nm), SrR
The uO ₃ upper electrode was grown epitaxially. (Ti,
Al) N is an S atmosphere in an Ar atmosphere using a nitride target.
RO and BSTO are prepared by using an oxide target to form Ar:
Film formation was performed in a mixed gas atmosphere of O ₂ = 4: 1.

When the obtained thin film capacitor was subjected to X-ray diffraction, (Ti, Al) N, SRO and BSTO were all epitaxially grown in the (001) direction with respect to the substrate surface. The c-axis length of BSTO is 0.407 nm,
The value was smaller than the c-axis value on the substrate. (00
2) When the half-width was measured by measuring the rocking curve of the peak, (Ti, Al) N was 1.2 °, SRO was 1.4 °,
BSTO was 1.5 ゜.

As described above, on a Si substrate which is a semiconductor,
When a lattice-mismatched (Ti, Al) N film is directly formed, crystallinity is limited even when epitaxial growth is performed under optimum conditions, and the rocking curve cannot have a half-width of less than 1.0 °. The crystallinity of the SRO or BSTO dielectric film laminated thereon was also inferior to that of the STO substrate.
Also, when the dielectric properties were measured between the upper and lower electrodes, only a remanent polarization of 8 μC / cm ² was obtained.
It was considerably inferior to that on the substrate.

Embodiment 3 Next, an embodiment of an FRAM will be described as an example of a semiconductor memory device manufactured by combining an epitaxial capacitor and a transistor according to the present invention. 3 and 4 are cross-sectional views schematically showing manufacturing steps of the FRAM manufactured in the third embodiment.

First, as shown in FIG.
0) After forming an impurity diffusion layer 102 having a depth of about 0.1 μm on the first surface of the substrate 101, a 10 nm-thick CoSi ₂ layer and a barrier layer 10 are formed as an epitaxial silicide layer 103.
4 as a (Ti, Al) N layer having a thickness of 10 nm; SrRuO ₃ layer having a thickness of 20 nm as the first electrode layer 105;
BSTO having a Ba mole fraction of 70% and a thickness of 20 nm
SrRu having a thickness of 20 nm as a film and a second electrode 107
The O ₃ layer was continuously grown epitaxially at a substrate temperature of 600 ° C. by RF or DC sputtering without being taken out into the atmosphere.

Next, a groove for separating adjacent capacitors and a groove for element isolation are formed by lithography and RI.
It was formed by etching such as E. After the groove is etched by RIE, the first and second electrodes 105 and 105 are used to prevent leakage at the end face of the dielectric film 106.
The 107 SrRuO ₃ layer was selectively wet-etched and lightly etched back.

Next, after the buried insulating films 108 and 109 were formed, they were planarized by CMP or the like. In addition,
At this time, in order to protect the surface of the second electrode 107, a method in which a TiN film or the like is formed in advance as a polishing stopper layer, and etching is removed after CMP can be used.

Next, as shown in FIG. 3B, a 200-nm-thick TiN film was formed as a drive line 110 at room temperature and patterned. Further, a BPSG layer 111 having a thickness of, for example, about 500 nm was formed as a bonding insulating film, and then planarized by, for example, a CMP method.

On the other hand, as shown in FIG. 4A, a support substrate 12 having a flattened BPSG layer 122
1 was prepared, and the flattened BPSG layers 111 and 122 were abutted and bonded. Bonding is performed by a known method, for example, 9
The heat treatment was performed at about 00 ° C. Next, the Si substrate 101
Then, a thin silicon layer having a thickness of, for example, about 150 nm was formed using the buried insulating film 109 for element isolation as a stop layer.

It is to be noted that a method of forming an SOI layer by bonding or polishing other than the above-described method, such as smart cut, may be used. Needless to say, the surface of the thin film silicon layer is mirror-polished so as to withstand the subsequent transistor formation process.
The transistor formation region is isolated by the buried insulating film 109 for element isolation formed from the first surface side.

Next, as shown in FIG. 4B, a connection hole 131 is opened by using ordinary photolithography and plasma etching such as RIE. As an etching condition at this time, it is preferable to selectively stop using any of the metal silicide layer 103, the barrier layer 104, and the first electrode layer 105 as a stopper.

Next, a poly-Si film containing, for example, N ⁺ -type impurities is deposited to a thickness of about 200 nm on the entire surface, and
The connection hole 1 is formed by etching and packing by MP or other method.
A buried layer 132 made of an N ⁺ poly Si layer was formed on 31. After this, 800A by RTA (Rapid Thermal Anneal) method
Annealing is performed in a nitrogen atmosphere at about 20 ° C. for about 20 seconds to form an N ⁺ sidewall diffusion layer 133. Next, the impurity diffusion layer 134 and the gate oxide film 13 are formed by using a known process.
5 and a word line 136 and a bit line 137 were formed.

As a result, a strong ferroelectric film was obtained as the capacitor film, and the remanent polarization 2Pr was as large as 80 μC / cm ² . The operation of the FRAM was confirmed by the capacitor using the ferroelectric film.

Embodiment 4 Next, an embodiment of a DRAM will be described as an example of a semiconductor memory device manufactured by combining an epitaxial capacitor and a transistor according to the present invention. FIGS. 5, 6 and 7 are cross-sectional views schematically showing manufacturing steps of the DRAM manufactured in the fourth embodiment.

First, as shown in FIG. 5A, Si (10
0) After forming an impurity diffusion layer 102 having a depth of about 0.1 μm on the first surface of the substrate 101, a 10 nm thick NiSi ₂ layer and a barrier layer 10 are formed as an epitaxial silicide layer 103.
4 as a (Ti, Al) N layer having a thickness of 10 nm; SrRuO ₃ layer having a thickness of 20 nm as the first electrode layer 105;
BSTO having a Ba mole fraction of 30% and a thickness of 20 nm
SrR having a thickness of 20 nm as the film and the second electrode layer 107
The uO ₃ layer was continuously epitaxially grown at a substrate temperature of 600 ° C. by RF or DC sputtering without being taken out into the atmosphere.

Next, a 200 nm-thick TiN film was formed at room temperature as the plate electrode 112, and a BPSG layer 110 was formed as a bonding insulating film at a thickness of, for example, about 500 nm, and then flattened by, for example, a CMP method. . Then, as shown in FIG. 5B, a BPSG layer 1 is separately formed on the surface.
A support substrate 121 having a flattened and formed 22 was prepared, and the flattened BPSG layers 110 and 122 were abutted and bonded. Bonding was performed by a known method, for example, a heat treatment at about 900 ° C.

Next, as shown in FIG. 5C, polishing is performed from the second surface of the Si substrate 101 to form a thin silicon layer having a thickness of, for example, about 150 nm. Note that other methods of forming the SOI by bonding and polishing such as smart cut may be used. Needless to say, the surface of the thin film silicon layer is mirror-polished so as to withstand the subsequent transistor formation process.

Next, trenches for separating adjacent capacitors were formed by lithography and etching such as RIE. At this time, the first electrode layer 105 of the adjacent capacitor was separated by using the dielectric film 106 of the capacitor as an etching stop layer. Next, after the buried insulating film 108 was formed, it was planarized by CMP or the like. After the buried insulating film 108 was selectively etched back to a shallow depth by RIE or the like, a single-crystal silicon electrode 113 was formed and flattened again.

At this time, the single-crystal silicon electrode 113 may be formed by forming an amorphous silicon layer in a conformal manner, and then crystallizing the side wall portion by a heat treatment such as RTA to form a single crystal, a selective growth CVD method, or the like. There is a method of selectively embedding single crystal silicon. In some cases, polysilicon may be embedded.

Further, as shown in FIG. 6A, a groove for separating the elements was formed by lithography and etching such as RIE. At this time, isolation between the elements of the first electrode layer 105 of the capacitor was performed by using the dielectric film 106 of the capacitor as an etching stop layer. Next, after the buried insulating film 109 was formed, it was planarized by CMP or the like.

As an example of a method for forming two types of buried insulating films, first, patterning is performed using a capacitor separating mask 141 as shown in FIG.
After burying the insulating film, flattening, selective etching back, burying and flattening the selectively grown single crystal silicon,
By using a method of patterning the silicon layer by selective etching using the element isolation mask 142 to bury the oxide film and flatten it, a mask alignment error when producing both buried insulating films is reduced. be able to.

Next, as shown in FIG. 7A, a connection hole 131 is opened by using ordinary photolithography and plasma etching such as RIE. As the etching conditions at this time, the silicide layer 103, the barrier layer 1
It is preferable to selectively stop using the 04 to the first electrode layer 105 as a stopper. Next, a poly-Si film containing, for example, an N ⁺ -type impurity is deposited to a thickness of about 200 nm on the entire surface, and the entire surface is etched back by a method such as CMP to form the N ⁺ poly-Si layer in the connection hole 131. A buried layer 132 is formed. After this, 8
Annealing in a nitrogen atmosphere at about 00 ° C. for 20 seconds forms the N ⁺ side wall diffusion layer 133.

Thereafter, as shown in FIG. 7B, a transistor including an impurity diffusion layer 134, a gate oxide film 135 and a word line 136, and a bit line 137 are formed by using a known process.

As a result, a paraelectric film having a very high dielectric constant was obtained as the capacitor film, and the dielectric constant was as large as 920. The operation of the DRAM was confirmed by the capacitor using the dielectric film.

[0082]

As described above, according to the present invention, an epitaxial capacitor having excellent dielectric properties can be manufactured on a silicon substrate. Therefore, it is possible to realize a highly practical and highly reliable ultra-highly integrated DRAM or FRAM.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating a configuration of an embodiment of a thin film capacitor of the present invention.

FIG. 2 is a cross-sectional view schematically showing a configuration of another embodiment of the thin film capacitor of the present invention.

FIG. 3 is a cross-sectional view schematically showing a manufacturing process of the FRAM manufactured in Example 3 of the present invention.

FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the FRAM following FIG. 3;

FIG. 5 is a cross-sectional view schematically showing a manufacturing process of the DRAM manufactured in Example 4 of the present invention.

FIG. 6 is a cross-sectional view schematically showing a DRAM manufacturing process following FIG. 5;

FIG. 7 is a cross-sectional view schematically showing a DRAM manufacturing process following FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si board | substrate 2 ... Metal silicide layer 3 ... First electrode layer (lower electrode) 4 ... Dielectric film 5 ... Second electrode layer (upper electrode) 6 ... Barrier layer 7 ... Thin film Capacitor

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8247 29/788 29/792

Claims (3)

[Claims] A metal silicide, comprising: a silicon substrate; and a silicide of at least one element selected from the group consisting of Ni, Co, Mn, Ru, Pd, Cr, Y, Er, and Ir. A first electrode layer epitaxially grown on the metal silicide layer, a dielectric film epitaxially grown on the first electrode layer, and a second electrode layer formed on the dielectric film. A thin film capacitor comprising: 2. The thin film capacitor according to claim 1, further comprising TiN or TiN and MN (MN) disposed between said metal silicide layer and said first electrode layer.
Represents at least one element selected from the group consisting of Al, V, Mo, Nb and Ta), wherein the barrier layer is epitaxially grown on the metal silicide layer. Thin film capacitors. 3. The thin film capacitor according to claim 1, wherein the dielectric film is made of a dielectric material having a perovskite crystal structure.