JP3604253B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device using a thin film capacitor provided with a dielectric film made of a dielectric material having a perovskite crystal structure or the like.
[0002]
[Prior art]
Recently, storage devices (ferroelectric memories) using a ferroelectric thin film as a storage medium have been developed, and some of them have already been put to practical use. Ferroelectric memory is non-volatile, and its memory contents are not lost even after the power is turned off. In addition, when the film thickness is sufficiently small, spontaneous polarization inversion is fast, and writing and reading can be performed as fast as DRAM. There are features such as. Further, since a 1-bit memory cell can be formed with one transistor and one ferroelectric capacitor, it is suitable for increasing the capacity.
[0003]
A ferroelectric thin film suitable for a ferroelectric memory needs to have a large remanent polarization, a small temperature dependence of the remanent polarization, and a capability of retaining the remanent polarization for a long time (retention).
[0004]
At present, lead zirconate titanate (PZT) is mainly used as a ferroelectric material. PZT is a solid solution of lead zirconate and lead titanate. A solid solution having a molar ratio of about 1: 1 has a large spontaneous polarization, can be inverted even in a low electric field, and is excellent as a storage medium. It is considered. Since PZT has a relatively high transition temperature (Curie temperature) between the ferroelectric phase and the paraelectric layer of 300 ° C. or higher, the stored content is not higher than the temperature range in which ordinary electronic circuits are used (120 ° C. or lower). Is less likely to be lost by heat.
[0005]
However, it is known that it is difficult to produce a high quality thin film of PZT. First, lead, which is a main component of PZT, tends to evaporate at 500 ° C. or higher, and thus it is difficult to accurately control the composition. Second, ferroelectricity appears only when PZT forms a perovskite crystal structure. However, PZT having this perovskite crystal is difficult to obtain, and a crystal structure called pyrochlore is more easily obtained. is there. Further, when applied to a silicon device, there is also a problem that it is difficult to prevent lead, which is a main component, from diffusing into silicon.
[0006]
Other than PZT, barium titanate (BaTiO ₃ ) is known as a typical ferroelectric. Barium titanate has a perovskite crystal similar to PZT, and its Curie temperature is known to be about 120 ° C. Since Ba is less likely to evaporate than Pb, control of the composition is relatively easy in forming a barium titanate thin film. Also, when barium titanate is crystallized, it hardly takes a crystal structure other than the perovskite type.
[0007]
Despite these advantages, barium titanate thin film capacitors have not been studied as much as a storage medium for ferroelectric memories because of their small remanent polarization and large temperature dependence of remanent polarization compared to PZT. Is mentioned. The cause is that the Curie temperature of barium titanate is low (120 ° C.). For this reason, when a ferroelectric memory is manufactured, stored contents may be lost when exposed to a high temperature of 100 ° C. or more. Not only that, even in a temperature range where electronic circuits are usually used (85 ° C. or lower), the temperature dependence of remanent polarization is large, and the operation is unstable. Therefore, it has been considered that a thin film capacitor using a ferroelectric thin film made of barium titanate is not suitable for use as a storage medium of a ferroelectric memory.
[0008]
[Problems to be solved by the invention]
The present inventors have proposed a new ferroelectric thin film having a dielectric constant relatively close to and slightly larger than the lattice constant of a lower electrode (for example, the (100) plane of strontium ruthenate (SrRuO ₃ , hereinafter referred to as SRO)). A material (for example, Ba _x Sr _1-x TiO ₃ ) is selected, and a film forming method called a RF magnetron sputtering method, in which misfit dislocations are relatively unlikely to be formed, is adopted. By epitaxial growth in the axial direction, even in a thin film having a relatively large film thickness of 200 nm or more, the lattice constant extends in the film thickness direction (c-axis) beyond the lattice constant of the original dielectric due to the epitaxial effect, and It has been found that the lattice constant in the inward direction (a-axis) can be kept reduced.
[0009]
As a result, it is possible to realize a ferroelectric thin film that shifts the ferroelectric Curie temperature to a higher temperature side, exhibits large remanent polarization in a room temperature region, and can maintain a sufficiently large remanent polarization even when the temperature is increased to about 85 ° C. Have confirmed.
[0010]
For example, a conductive perovskite crystal as a lower electrode SRO (lattice constant a: 0.393). Using the barium strontium titanate as a dielectric _{(Ba x Sr 1-x TiO} 3, hereinafter referred to as BST composition region 0 .30 ≦ x ≦ 0.90), ferroelectricity is exhibited even in a composition region (x ≦ 0.7) which should not originally exhibit ferroelectricity at room temperature, and originally ferroelectricity at room temperature. It has been experimentally confirmed that, in a composition region (x> 0.7), a practically preferable ferroelectric characteristic in which the Curie temperature originally higher than room temperature is further increased can be realized.
[0011]
A nonvolatile semiconductor memory can be formed by using a thin film capacitor using the ferroelectric thin film grown epitaxially. Epitaxial thin film capacitors can be manufactured in various structures as described below.
(1) A method in which a single crystal Si plug is formed on a transistor electrode by selective epitaxial growth or solid phase epitaxial growth, and an epitaxial thin film capacitor is formed thereon (Japanese Patent Application No. Hei 7-082091).
(2) On the interlayer insulating film covering the transistor, a single crystal SOI (Silicon On Insulator) layer is formed by growing from a seed portion having one end in contact with the Si substrate, and an epitaxial thin film capacitor is formed thereon. A method in which one of the electrodes of a transistor is connected to a capacitor by a contact plug formed under the SOI layer (Japanese Patent Application No. H7-22509).
(3) On the interlayer insulating film covering the transistor, a single-crystal Si layer is formed by the graphoepitaxy method, an epitaxial thin-film capacitor is formed thereon, and further, a contact plug is formed to form one of the electrode of the transistor and the capacitor. A method of connecting one of the electrodes (Japanese Patent Application No. Hei 7-22509).
(4) A method in which an epitaxial thin film capacitor is formed on a Si substrate and connected by wiring to electrodes of transistors separately arranged in parallel (Japanese Patent Application No. 8-034867).
[0012]
Among them, the method (1) is most suitable for high integration in terms of structure because a thin film capacitor can be manufactured by laminating it directly above the transistor, but the process window for manufacturing a single crystal Si plug is narrow. Considering the yield of fabricating tens of mega or more plugs in one memory device, there is a great technical problem to be cleared.
[0013]
In the methods (2) and (3), the SOI method and the grapho-epitaxial method are used for forming a single-crystal Si layer serving as a base for manufacturing a capacitor. It is not a technically established method, including a high-temperature heat treatment process, and there are still many technical issues to be cleared.
[0014]
In the method (4), although there are few technical problems, the space efficiency is deteriorated because the capacitor and the transistor are separately arranged on the Si substrate, and it is difficult to manufacture a highly integrated memory element. There is another problem.
[0015]
In the above description, a ferroelectric dielectric thin film has been described. However, a paraelectric dielectric thin film having a high dielectric constant has a similar problem.
The present invention is easy to fabricate in a semiconductor memory using a dielectric thin film exhibiting ferroelectricity by utilizing the epitaxial effect or a dielectric thin film in which ferroelectricity or paraelectricity is enhanced by the epitaxial effect. The purpose of the present invention is to provide a capacitor cell capable of relatively high integration.
[0016]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a semiconductor memory device having a memory cell array in which memory cells each including a transistor and a capacitor are arranged in a matrix on a semiconductor substrate, wherein a gate electrode wiring of the transistor is provided. An insulating film is formed on the side and upper part of the transistor so as to cover the gate electrode wiring, and the gate electrode wiring is formed on the source or drain electrode of the transistor from above the insulating film on the side of the gate electrode wiring of the transistor. A lower electrode layer of the capacitor formed continuously on the insulating film on the side of the gate electrode wiring disposed adjacent to the substrate; and a dielectric of the capacitor provided on the lower electrode layer. A film and an upper electrode layer of the capacitor provided on the dielectric film, wherein the lower electrode layer and the dielectric film are at least In the source or drain electrode, to provide a semiconductor memory device, characterized in that the epitaxially grown or oriented growth inheriting the crystal orientation of the source or drain electrode.
[0017]
In this invention, the following embodiments are preferable.
(1) A barrier metal layer is formed between the source or drain electrode and the lower electrode layer, and the barrier metal layer is epitaxially grown or oriented while taking over the crystal orientation of the source or drain electrode. .
[0018]
(2) The upper electrode layer of the capacitor is in contact with only the portion of the dielectric film that is epitaxially or orientedly grown on the source or drain electrode.
[0019]
(3) In a region other than a portion where the upper electrode layer is in contact with the dielectric film, a buried insulating film is formed separately from the dielectric film so as to fill a space between the upper electrode layer and the lower electrode layer. That
[0020]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a semiconductor memory device having a memory cell array in which memory cells each including a transistor and a capacitor are arranged in a matrix on a semiconductor substrate, wherein a gate electrode wiring of the transistor is provided. An insulating film is formed on the side and upper part of the transistor so as to cover the gate electrode wiring, and the gate electrode wiring is formed on the source or drain electrode of the transistor from above the insulating film on the side of the gate electrode wiring of the transistor. A lower electrode layer of the capacitor formed continuously on the insulating film on the side of the gate electrode wiring disposed adjacent to the substrate; and a dielectric of the capacitor provided on the lower electrode layer. A film and an upper electrode layer of the capacitor provided on the dielectric film, wherein the lower electrode layer and the dielectric film are at least On the source or drain electrode, the crystal orientation of the source or drain electrode is inherited and epitaxial growth or orientation growth is performed, and the upper electrode layer of the capacitor is epitaxially grown or oriented on the source or drain electrode. A method of manufacturing a semiconductor memory device, wherein the method is in contact with only the portion of the dielectric film .
[0021]
(6) The semiconductor memory device according to any one of claims 1 to 6, wherein the original Curie temperature of the dielectric film is 200 ° C or lower.
The above-described present invention has the following advantageous effects.
[0022]
That is, Pb (Zr, Ti) O ₃ (PZT) containing lead having a low melting point and SrBi ₂ Ta ₂ O ₉ (SBT) containing bismuth used as a conventional ferroelectric film are introduced into a Si substrate. Because of the severe diffusion problem, it was necessary to form the transistor far from the transistor. However, in the capacitor using the epitaxial BST dielectric film according to the present invention, it is necessary to use a low-melting-point metal-free diffusion rate and a barrier metal having a high barrier property without a grain boundary. For the first time, it has become possible for the first time to form a ferroelectric capacitor or a capacitor with a high dielectric constant directly on one electrode of a transistor or an Si electrode extending from the electrode.
[0023]
According to the present invention, for example, a single crystal Si plug formed by a selective epitaxial CVD growth method or the like is not required as compared with the above-described conventional example (1), and a barrier metal, a lower electrode, a dielectric film and the like can be conformally formed simply by a sputtering method. Since epitaxial growth is sufficient, it is technically much easier.
[0024]
Also, in order to form a capacitor by conformal epitaxial growth by sputtering in a contact hole formed in an insulating film formed on one electrode of the transistor or an extension thereof, the height of the contact hole is larger than the height of the contact hole. It is desirable that the width be sufficiently wide and the aspect ratio be 0.5 or less.
[0025]
Further, the portion of the capacitor formed in contact with the Si substrate on the bottom surface in the contact hole is epitaxially grown to have ferroelectricity, while the portion of the capacitor formed in contact with the insulating film on the side surface in the contact hole is always formed. Since it is dielectric or weakly ferroelectric, it is desirable that the upper electrode of the capacitor be in contact with only the portion of the dielectric film facing the substrate or the portion of the dielectric film that is being oriented and grown.
[0026]
Also, the reason that the Curie temperature specific to the dielectric material is specified to be 200 ° C. or lower is that those having a high Curie temperature of 200 ° C. or higher include lead or bismuth, which are low-melting metals, as elements constituting perovskite crystals. This is because the dielectric is not suitable for the process of the present invention.
[0027]
According to the present invention, avoiding the inclusion of lead and bismuth, which are low-melting metals difficult to adapt to the silicon process, the ferroelectric film induced by the strain introduced during epitaxial growth is used as one electrode of a transistor. Or, it can be easily formed on the extension thereof, and a highly reliable and highly integrated semiconductor memory element can be manufactured.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a process sectional view showing a process according to an embodiment of the present invention. 1 is a first conductivity type semiconductor substrate, 2 is an element isolation oxide film, 3 is a gate oxide film, 4 is a word line (gate electrode wiring), 5a is an insulating film surrounding the gate electrode wiring, 5b, 10a, 10b Is an interlayer insulating film, 6 is a second conductivity type impurity diffusion layer, 8 is a bit line, 9 is a contact plug of a bit line, 11 is a contact hole bottom region, 12 is a barrier metal, 13 is a lower electrode, and 14 is a dielectric thin film. , 15a and 15b are upper electrodes, and 16 is a drive line.
[0029]
FIG. 1A shows that a transistor portion of a memory cell and an interlayer insulating film 5b are formed and planarized by a chemical mechanical polishing (CMP) method, and then a contact hole 11 is formed in one electrode of the transistor and an extension thereof. It has just opened. At this time, the aspect ratio of the depth and width of the contact hole was set to 0.4 so that the electrode and the dielectric film could be epitaxially grown on the Si substrate by the subsequent sputtering. The contact hole opening was etched to a depth of about 80% by RIE, and then a clean Si surface was exposed by wet selective etching using hydrofluoric acid.
[0030]
Next, as shown in FIG. 2B, TiN was deposited at 600 ° C. as a barrier metal 12 by a reactive sputtering method (using a Ti target) or a normal sputtering method (using a TiN target), and a mask was used. Unnecessary portions other than the contact hole and its periphery were removed by RIE. The atmosphere in both sputtering methods was, for example, a mixed gas atmosphere of Ar and N ₂ , the mixing ratio was, for example, Ar: N ₂ = 10: 1, and the total pressure was, for example, several milliTorr. At this time, the portion in contact with the Si substrate at the bottom of the contact hole was single crystal TiN oriented in the (001) direction, but the portion in contact with the insulating film on the side wall was polycrystalline TiN.
[0031]
Next, as shown in FIG. 3C, a platinum thin film, a conductive perovskite film, for example, an SRO film, and a BST thin film 14 having a Ba mole fraction of 70% are further formed by sputtering at 600 ° C. as the lower electrode 13. It was grown to a thickness of 40 nm at 600 ° C. by a sputtering method. An Ar gas atmosphere was used for forming the platinum thin film, and a mixed gas atmosphere of Ar and O ₂ (for example, Ar: O ₂ = 4: 1) was used for forming the SRO film and the BST thin film. At this time, the lower electrode made of platinum and SRO and the BST dielectric film were all epitaxially grown in the (001) orientation on the single-crystal TiN at the bottom of the contact hole, but all were grown on the side portions and on the insulating film. It was a polycrystalline film. Further, the whole was covered with an interlayer insulating film 7.
[0032]
Then, as shown in FIG. 2A, the lower electrode and the dielectric film other than the inside of the contact hole were removed by a CMP method using the TiN film 12 formed above the word line as a stopper. .
[0033]
Next, as shown in FIG. 2B, the interlayer insulating film 7 in the contact hole is patterned by photolithography and RIE, and an SRO film is formed as an upper electrode 15a by a sputtering method at a film forming temperature of 600 ° C. After the Al electrode 15b was formed at room temperature by a sputtering method, the upper electrode except for the inside of the contact hole was removed by a CMP method. Further, a contact plug 9 for a bit line made of polysilicon was formed on the other electrode not connected to the capacitor of the transistor by a known method.
[0034]
Next, as shown in FIG. 2C, drive lines 16 and bit lines 8 were formed.
When the characteristics of the ferroelectric thin film capacitor thus formed were measured, a large value of 0.42 C / m ² was obtained as the amount of remanent polarization, confirming that the capacitor functions as a ferroelectric capacitor.
[0035]
Note that the present invention is not limited to the above embodiment. As the sputtering method, a magnetron sputtering method can be used.
For example, as a method of patterning the interlayer insulating film 7, a method using lithography has been described. However, the interlayer insulating film 7 formed on the entire surface is etched back by anisotropic etching on the entire surface, so that the side wall of the contact hole (the gate electrode wiring) is formed. A method of selectively leaving the interlayer insulating film 7 on the side wall portion of the insulating film 5a surrounding the periphery may be used.
[0036]
Further, as the process of manufacturing the dielectric film, a method of forming the dielectric film in advance before patterning the interlayer insulating film 7 has been described. A method may be adopted in which a first layer is formed in advance before patterning, and a second layer is further formed after patterning the film 7.
[0037]
Further, for example, when a damaged layer is formed on an electrode made of a conductive perovskite such as SRO by an etching process such as RIE or a CMP process, the damaged layer is formed using a mixed solution containing cerium ammonium nitrate and perchloric acid. It is possible to remove the layer. When the damaged layer is formed on the dielectric layer made of perovskite such as BST by the above process, the damaged layer is removed by using a mixed solution containing EDTA (ethylenediaminetetraacetate), hydrogen peroxide, and ammonia. It is possible to do.
[0038]
As the barrier insulating film, a TiAlN film may be used in addition to the TiN film, or may be omitted in some cases.
The conditions for forming the TiAlN film are as follows: first, a Si substrate is etched with a 1% HF solution for 3 minutes, and then rinsed with ultrapure water for 30 minutes. Here, it is also possible to use a method of adding the mixed solution of HCl and H ₂ O for 1 minute after the HF cleaning. Next, the film is heated to 850 ° C. at 1 × 10 ⁻⁷ Torr or less. Further, the substrate temperature was set to 600 ° C., and a TiAlN film was formed by ion beam reactive film formation at a film formation rate of about 0.03 nm / min. As the evaporation source, EB was used for Ti, and K-cell (Knundsencell) was used for Al. The substrate was irradiated with N ₂ ⁺ ions accelerated to 100 eV.
[0039]
Furthermore, in the above embodiment, a method of forming a ferroelectric film to form an FRAM has been described. However, a method of forming a high dielectric constant paraelectric film to form a DRAM, and a memory device in which FRAM and DRAM are mixed. Can be applied to the method of forming. In this case, when BST is used as the insulating film of the DRAM, it is possible to use a material having a high strontium content (for example, strontium 80% and barium 20%).
In addition, various modifications can be made without departing from the spirit of the present invention.
[0040]
【The invention's effect】
As described in detail above, according to the present invention, avoiding the inclusion of lead and bismuth, which are low-melting metals difficult to adapt to the silicon process, avoiding the ferroelectric film or the ferroelectric film induced by the strain introduced during epitaxial growth. A paraelectric film can be formed on a semiconductor substrate by an easy process, and a highly reliable and highly integrated semiconductor memory element can be realized. The industrial value of the present invention is extremely large.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view showing a process of manufacturing a memory cell according to an embodiment of the present invention.
FIG. 2 is a process cross-sectional view showing a process of manufacturing the memory cell according to the embodiment of the present invention following FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... First conductivity type semiconductor substrate 2 ... Element isolation oxide film 3 ... Gate oxide film 4 ... Word line (gate electrode wiring)
5a ... Insulating films 5b, 10a, 10b surrounding the periphery of the gate electrode wiring ... Interlayer insulating film 6 ... Second conductivity type impurity diffusion layer 7 ... Interlayer insulating film 8 ... Bit line 9 ... Bit line contact plug 11 ... Contact hole bottom Region 12 Barrier metal 13 Lower electrode 14 Dielectric thin films 15a and 15b Upper electrode 16 Drive line

Claims (3)

A semiconductor memory device having a memory cell array in which memory cells each including a transistor and a capacitor are arranged in a matrix on a semiconductor substrate, wherein the gate electrode wiring is provided on a side portion and an upper portion of a gate electrode wiring of the transistor. An insulating film is formed so as to cover the gate electrode wiring side disposed on the source or drain electrode of the transistor, from the insulating film on the side of the gate electrode wiring of the transistor, adjacent to the gate electrode wiring. A lower electrode layer of the capacitor formed continuously over the insulating film of the portion, a dielectric film of the capacitor provided on the lower electrode layer, and provided on the dielectric film An upper electrode layer of the capacitor, wherein the lower electrode layer and the dielectric film are formed on at least the source or drain electrode. Te, part of the source or are epitaxially grown or oriented growth inheriting the crystal orientation of the drain electrode, and an upper electrode layer of the capacitor, the dielectric film is epitaxially grown or oriented growth in the source or drain electrode on the A semiconductor memory device which is in contact only with the semiconductor memory device. In a region other than a portion where the upper electrode layer is in contact with the dielectric film, a buried insulating film is formed separately from the dielectric film so as to fill a space between the upper electrode layer and the lower electrode layer. 2. The semiconductor memory device according to claim 1, wherein: The upper end of the lower electrode layer and the upper end of the upper electrode layer on the insulating film on the side of the gate electrode wiring are substantially in the same plane. 13. The semiconductor memory device according to claim 1.

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