JP3400218B2 - Dielectric capacitor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric capacitor having an epitaxial dielectric thin film used for a semiconductor memory device. 2. Description of the Related Art Recently, a storage device (ferroelectric memory) using a ferroelectric capacitor having a ferroelectric thin film as a storage medium has been developed. It has been done. Ferroelectric memory is non-volatile, and its contents are not lost even after power is turned off. In addition, when the film thickness is thin, the spontaneous polarization is reversed quickly, enabling writing and reading as fast as DRAM. It has excellent features such as In addition, since a 1-bit memory cell can be formed with one transistor and one ferroelectric capacitor, it is suitable for increasing the capacity. The characteristics required for a ferroelectric thin film suitable for a ferroelectric memory include a large remanent polarization, a small temperature dependence of the remanent polarization, and a capability of maintaining the remanent polarization for a long time (retention). ). At present, lead zirconate titanate (PZT) is mainly used as a ferroelectric material. PZT
Is a solid solution of lead zirconate and lead titanate. A solid solution having a molar ratio of about 1: 1 has a large spontaneous polarization, can be inverted even in a low electric field, and is excellent as a storage medium. It is considered. PZT has a relatively high transition temperature (Curie temperature) between the ferroelectric phase and the paraelectric layer of 300 ° C. or higher. Therefore, PZT is stored in a temperature range where normal electronic circuits are used (120 ° C. or lower). There is little worry that the contents will be lost due to heat. [0005] However, it is known that it is difficult to produce a high quality thin film of PZT. First, lead, which is a main component of PZT, tends to evaporate at 500 ° C. or higher, so that it is difficult to accurately control the composition. Second, ferroelectricity appears only when PZT forms a perovskite-type crystal structure. However, it is difficult to obtain PZT having this perovskite-type crystal and a crystal structure called pyrochlore is more easily obtained. . In addition, when applied to a silicon device, there is a problem that it is difficult to prevent lead, which is a main component, from diffusing into silicon. Other than PZT, barium titanate (BaT)
iO ₃ ) is known as a typical ferroelectric. Barium titanate has a perovskite crystal similar to PZT, and is known to have a Curie temperature of about 120 ° C. Since Ba is less likely to evaporate than Pb, it is relatively easy to control the composition in forming a barium titanate thin film. Further, when barium titanate is crystallized, it hardly takes a crystal structure other than the perovskite type. [0007] Despite these advantages, barium titanate thin film capacitors have not been studied so much as storage media for ferroelectric memories because barium titanate has a small remanent polarization compared to PZT and a remanent polarization. Is highly temperature-dependent. The cause is that the Curie temperature of barium titanate is low (120
Therefore, when a ferroelectric memory is manufactured, not only may the stored contents be lost when exposed to a high temperature of 100 ° C. or more, but also the temperature range in which electronic circuits are usually used ( (85 ° C. or less), the temperature dependence of remanent polarization is large and the operation is unstable. Therefore, it is considered that a thin film capacitor using a ferroelectric thin film made of barium titanate is not suitable for use as a storage medium of a ferroelectric memory. SUMMARY OF THE INVENTION The present inventors have proposed a new ferroelectric thin film as a lower electrode (for example, Pt (10
A dielectric material (for example, Ba _x Sr _{1 -x} TiO ₃ ) having a lattice constant relatively close to the lattice constant of the (0) plane) is selected, and misfit dislocations are formed in a film forming process called RF magnetron sputtering. By adopting a film formation method that is relatively hard to enter, and by epitaxially growing in the c-axis direction, which is the polarization axis, even a thin film having a relatively thick film thickness of 200 nm or more can have an original dielectric material due to the epitaxial effect. It has been found that the lattice constant is longer in the film thickness direction (c-axis) than in the lattice constant, and the lattice constant in the in-plane direction (a-axis) can be kept reduced. As a result, the ferroelectric Curie temperature is shifted to a higher temperature, a large remanent polarization is exhibited in a room temperature region, and
It has been confirmed that a ferroelectric thin film capable of maintaining a sufficiently large remanent polarization even when the temperature is raised to about 5 ° C. is feasible.
For example, Pt (lattice constant a: 0.39231), which is hardly oxidized, is used as the lower electrode, and barium strontium titanate (Ba _x Sr) in a predetermined composition region is used as the dielectric.
_1-x TiO ₃ , x = 0.30-0.90 (hereinafter referred to as BST), so that ferroelectricity can be obtained even in a composition region (x ≦ 0.7) which should not exhibit ferroelectricity at room temperature. And a composition region (x
> 0.7), it has been experimentally confirmed that a practically preferable ferroelectric characteristic in which the Curie temperature originally higher than room temperature is further increased can be realized. However, the use of platinum for the lower electrode is excellent in that it has excellent insulation properties as a capacitor and obtains a large ferroelectricity. However, the platinum halide has a low vapor pressure, and the reactive ion There is a disadvantage that dry etching by etching or the like is very difficult. For this reason, when trying to create a submicron-sized capacitor cell, there is a problem in that the processing of the platinum lower electrode becomes an obstacle, making it extremely difficult to produce the capacitor cell. Also, instead of the platinum lower electrode,
Similarly, even if a conductive perovskite crystal such as strontium ruthenate, which can epitaxially grow the BST film, is used, fine processing by dry etching of the lower electrode remains difficult. The present invention is highly integrated using a thin film capacitor having a ferroelectric thin film exhibiting ferroelectricity utilizing the epitaxial effect or a ferroelectric thin film having enhanced ferroelectricity by the epitaxial effect. The purpose of the present invention is to overcome the problem of microfabrication of the lower electrode, which is a problem when fabricating a nonvolatile memory. That is, an object of the present invention is to provide a dielectric capacitor which has a high ferroelectric Curie temperature, can maintain a large remanent polarization even at a high temperature, and can finely process a lower electrode. Means for Solving the Problems To solve the above problems, the present invention (claim 1) provides a hexagonal (000) on the surface.
1) A conductive substrate having a surface, and a dielectric film having a perovskite crystal structure epitaxially grown on the conductive substrate in a (111) plane orientation, wherein a hexagonal crystal on the surface of the conductive substrate is provided. a-axis lattice constant a _s (hcp)
If, to provide a dielectric capacitor in which the dielectric material natural lattice constant a _d represented by the a-axis length of the perovskite type crystal and satisfies the relationship represented by the following formula. [0014] _{1.002 ≦ a d / (a s} (hcp) × 2
^1/2 ) ≦ 1.030 The present invention (Claim 2) also provides a cubic (11)
1) A conductive substrate having a surface, and a dielectric film having a perovskite type crystal structure epitaxially grown on the conductive substrate in a (111) plane orientation, wherein a cubic crystal on the surface of the conductive substrate is provided. a-axis lattice constant a _s (cu
and b), a provide a dielectric capacitor in which the dielectric material natural lattice constant a _d represented by the a-axis length of the perovskite type crystal and satisfies the relationship represented by the following formula. [0015] _{1.002 ≦ a d / a s (} cub) ≦ 1.030 Further, the present invention (Claim 3), in the dielectric capacitor (claims 1, 2), the original of the dielectric material Provided is a dielectric capacitor having a Curie temperature of 200 ° C. or lower. Further, according to the present invention (claim 4), in the above dielectric capacitor (claims 1 and 3), the conductive substrate is a silicon (111) substrate and the silicon (1
11) An insulating layer having an opening formed on the substrate, and grown on the insulating layer through the opening.
A dielectric capacitor comprising an oriented silicon layer, wherein a dielectric film of the capacitor is epitaxially grown on the (111) oriented silicon layer. The above-mentioned hexagonal conductive substrate includes an alloy containing at least one selected from the group consisting of rhenium (Re), ruthenium (Ru), and osmium (Os). The present invention is based on the following principle. That is, the present inventors have focused on ruthenium (Ru), rhenium (Re), or osmium (Os), which can be finely processed, among noble metals that can be used as a base electrode of an oxide dielectric. However, platinum, gold, palladium, iridium, rhodium, and the like take a face-centered cubic lattice (fcc) and have a lattice constant very close to that of a cubic perovskite dielectric film. The direction of polarization on the (100) plane is (10).
The 0) plane can be epitaxially grown.
In addition, by making the lattice constant of the lower electrode slightly smaller than the lattice constant of the dielectric film, the a-axis in the growth plane of the dielectric film is contracted, and the c-axis in the growth direction is extended, so that it is in the polarization axis direction of the BST film. It is possible to dramatically improve the dielectric characteristics in the c-axis direction. In addition, the (100) plane of a platinum electrode or the like can be epitaxially grown directly or via a barrier metal or the like on a silicon (100) substrate in order to form a transistor constituting a memory cell in combination with a capacitor. On the other hand, Ru, Re, and Os all belong to a hexagonal system, which is the polarization direction of the BST crystal at room temperature (1).
It is impossible to obtain lattice matching with the (00) plane, and epitaxial growth cannot be performed. Therefore, the present inventors have proposed that the polarization axis of the barium titanate crystal is [11
1] We focused on the orientation. That is, barium titanate is tetragonal between about 130 ° C. and about 0 ° C., and about 0 ° C.
From about −90 ° C., the rhombohedral crystal is stable below, and the rhombohedral crystal is stable below.
It is said that the [111] direction has a polarization axis direction. As described above, although the stable phase changes depending on the temperature, the energy difference between the stable phases is considered to be very small. Therefore, BS on the (100) plane of platinum
The c-axis is elongated by the strain introduced when T is epitaxially grown, and the cubic crystal becomes tetragonal even in a stable composition region, and spontaneous polarization appears in the c-axis direction to form a ferroelectric substance. If strain is introduced by epitaxially growing the (111) plane of a perovskite-based dielectric film on the lower electrode composed of a hexagonal (0001) plane or a cubic (111) plane, spontaneous movement in the [111] direction occurs. Polarization occurs and ferroelectricity can be induced. For example, the hexagonal crystals of Ru, Re, and Os have lattice constants of the a-axis of 0.2704 nm and 0.2704 nm, respectively.
761 nm and 0.2735 nm, which are considered as cubic (111) planes and are converted into lattice constants.
0.3824 nm, 0.3905 nm and 0.386
8 nm. On the other hand, the lattice constant of strontium titanate is 0.3904 nm, the a-axis of tetragonal barium titanate is 0.3992 nm, the c-axis is 0.4036 nm,
The volume averaged lattice constant is 0.4007 nm. Therefore, Ru, Re, Os
Alloys (a mutual solid solution is formed, the lattice constant is Ru
The ferroelectricity in the [111] direction is increased by using the (0001) plane of (which continuously changes from Re to Re) and epitaxially growing the (111) plane of a solid solution of strontium titanate and barium titanate as a dielectric. It is possible to introduce distortion based on a lattice constant difference of 0.2% to 3.0%, which is desirable to apply. For example, rhenium is used for the base electrode, and B with a barium fraction of 80% is used for the dielectric.
By using the ST film (0.3980 nm), 1.9% strain can be given in the in-plane direction of the dielectric film. Specifically, as a dielectric material having a perovskite structure which can be used in the present invention, there is a dielectric material having a composition formula represented by ABO ₃ . A is mainly composed of Ba, part of which is replaced by at least one element of Sr or Ca, and B is Ti, Sn, Z
r, Hf, etc. and their solid solution systems, and further Mg _1/3
Ta _2/3 , Mg _1/3 Nb _2/3 , Zn _1/3 Nb _2/3 , Zn
Complex oxides such as _1/3 Ta _2/3 and their solid solution systems can be used. In the present invention, the Curie temperature inherent to the dielectric is set to 2
The reason that the temperature is specified as 00 ° C or less is that the Curie temperature is 200 ° C.
The reason for the above high values is that these dielectrics are not suitable for the silicon semiconductor process because the elements constituting the perovskite crystal include lead or bismuth, which are low melting point metals. As the base electrode, Ru, Re, Os and alloys thereof, which are relatively easy to dry-etch, are desirable. However, for the purpose of improving oxidation resistance and adjusting the lattice constant, platinum, palladium, Iridium, rhodium, or the like may be uniformly dissolved in Ru, Re, or Os or near the surface. It is also possible to use the (111) plane of a crystal having a face-centered cubic lattice, such as an alloy centered on platinum. Furthermore, a hexagonal (0001) plane such as ruthenium or rhenium and a cubic (111) plane such as platinum
It is also possible to stack the faces. Relatively thick Ru, R
e, By growing a very thin platinum layer on Os, it is also possible to achieve both workability and oxidation resistance at the dielectric interface. In the present invention, the reason that the ratio of the lattice constant between the dielectric film and the base electrode is specified to be 0.2% to 3.0% is as follows.
If the ratio is less than 0.2%, it is impossible to sufficiently increase the Curie temperature to introduce a strain for obtaining a large remanent polarization. If the ratio is more than 3.0%, the strain is too large, and the interface with the substrate or the growth. This is because lattice mismatch distortion is introduced in the middle and the distortion is alleviated. In the present invention, a hexagonal crystal (0
As a method of forming a lower electrode crystal oriented in the (001) plane or the cubic (111) plane, there is a method of using an Si (111) substrate and utilizing epitaxial or oriented growth from the Si (111) plane. . In addition, a barrier metal layer or a contact plug layer epitaxially or orientationally grown can be interposed between the silicon substrate and the lower electrode. As barrier metal, titanium, tantalum,
Among the refractory metals such as niobium, tungsten and molybdenum, and nitrides, carbides, silicides and oxides thereof, use the (0001) plane of the hexagonal crystal and the (111) plane of the cubic crystal. Can be. For example, the (111) plane of cubic titanium nitride is used. As the contact plug, in addition to the above-described barrier metal material, a silicon crystal that has been epitaxially grown or oriented can be used. As described above, the dielectric capacitor according to the present invention is a nonvolatile ferroelectric memory (FR).
AM), but can also be used for a dynamic random access memory (DRAM) using a high dielectric film. That is,
It is known that the dielectric takes the maximum value near the ferroelectric phase transition temperature (Curie temperature). However, the solid solution ratio of barium titanate and strontium titanate in the dielectric layer and the lower electrode constitute For example, by adjusting two parameters, that is, the ratio of the lattice constant to the Ru, Re, and Os alloys, it is possible to obtain a dielectric film having a larger dielectric constant than the bulk dielectric. Specifically, the mole fraction of St is 0 to 3
In a BST film of about 0%, the lattice constant ratio with respect to the lower electrode made of Re, Ru, and Os alloys is set to 1 to 3% to introduce a compressive strain in the film plane, so that the dielectric constant becomes 500 to 10%.
A dielectric film as large as 00 can be obtained. As described above, according to the present invention, a ferroelectric film which does not contain lead and bismuth, which are low melting point metals which are difficult to adapt to a silicon process, and which is induced by strain introduced during epitaxial growth, is used. Also, by using an alloy such as Ru or Re that can be dry-etched also for the lower electrode, it is possible to obtain a dielectric capacitor capable of forming a highly integrated nonvolatile semiconductor memory element. Hereinafter, the present invention will be described with reference to examples. Embodiment 1 FIGS. 1 and 2 are cross-sectional views showing a manufacturing process of a ferroelectric memory according to a first embodiment of the present invention in the order of steps. That is, this is an example in which a ferroelectric memory is formed by forming a strain-induced ferroelectric film by using mismatching strain generated when epitaxially growing. FIG. 1A shows a state in which the transistor portion of the memory cell and the interlayer insulating film 9 have been formed. FIG.
In (a), reference numeral 1 indicates a silicon substrate of the first conductivity type. An element isolation oxide film 2 is formed on the first conductivity type silicon substrate 1, and a gate oxide film 3 and a word line 4 are formed on a region of the silicon substrate 1 separated by the element isolation oxide film 2. I have. Reference numeral 5 denotes an interlayer insulating film, and reference numeral 6 denotes a second conductivity type impurity diffusion layer. Next, as shown in FIG. 1B, an interlayer insulating film was opened by photolithography and ion etching, and a contact plug 11 was formed by a selective growth technique on a single crystal silicon (111) surface. LPCVD using dichlorosilane as source gas
Single crystal silicon was selectively embedded at a growth temperature of 820 ° C. by the method. After that, as shown in FIG. 1C, the contact plug 11 is etched back by wet selective etching using hydrofluoric acid to flatten it, and then the barrier metal layer 12 is formed at 600 ° C. by a reactive sputtering method. With TiN
The film was epitaxially grown to have a (111) plane. Subsequently, a Re-10% Ru alloy thin film to be the lower electrode 13 was epitaxially grown at 600 ° C. by a sputtering method so as to have a (0001) plane. Further, a BST thin film 16 having an Sr mole fraction of 20% was epitaxially grown on the lower electrode 13 so as to have a (111) plane. Next, as shown in FIG. 2A, the dielectric layer 1 is formed by photolithography and ion etching.
6, the lower electrode layer 13 and the barrier metal layer 12 were patterned. Next, as shown in FIG. 2B, an interlayer insulating film 7 was deposited, the interlayer insulating film 7 was opened by photolithography and ion etching, and a nickel upper electrode 15 was sequentially formed. Thereafter, as shown in FIG. 2C, an interlayer insulating film 9 is further deposited, and the interlayer insulating film 9 is formed by photolithography and ion etching.
Holes 7 and 5 were formed to form bit lines 8. In the dielectric capacitor of the ferroelectric memory thus obtained, the BST film serving as the dielectric layer 16 has an original lattice constant of the a-axis of 0.3975 nm, and the lower electrode layer 13 serving as the Re-Ru alloy Has a lattice constant of 0.2755n
m, and when converted to the fcc (111) plane by doubling the square root, the lattice constant ratio was 1.020. When the dielectric properties were measured, a large value of 0.15 C / m ² was obtained as the amount of residual polarization, confirming that the ferroelectric memory was sufficient. Embodiment 2 FIGS. 3 and 4 are sectional views showing a process of manufacturing a dynamic access memory (DRAM) semiconductor memory device according to a second embodiment of the present invention in the order of steps. FIG.
FIG. 11 is a cross-sectional view after forming a transistor portion and a bit line of a memory cell on an i (111) substrate, and then forming an insulating film for planarization and a polishing stopper layer. In FIG. 3A, reference numeral 11 denotes a first conductivity type semiconductor substrate. An element isolation oxide film 12 is formed on the first conductivity type silicon substrate 11, and a gate oxide film 13 and a word line 14 are formed on a region of the silicon substrate 11 separated by the element isolation oxide film 12. I have. Reference numerals 15, 1
7 is an interlayer insulating film, 16 is a second conductivity type impurity diffusion layer, 18
Denotes a bit line, 19 denotes a planarization insulating film, and 20 denotes a polishing stopper layer. In order to planarize the insulating film 19, an etch-back method or a CMP method may be used. As the polishing stopper layer 20, an insulating film such as aluminum oxide can be used. Next, as shown in FIG. 3B, a contact hole to the second conductivity type impurity diffusion layer is formed following the opening of the polishing stopper layer 20 by known photolithography and plasma etching. An amorphous silicon layer 21 was formed by a growth technique. The film formation technology is based on LPC using disilane and diborane as source gas.
Amorphous silicon was selectively grown on a single crystal silicon substrate at a growth temperature of 450 ° C. by the VD method. Next, by heat treatment at 600 ° C. in a forming gas, single crystal silicon of (111) orientation was grown from the interface of the silicon substrate 11 by solid phase growth, and the entire amorphous layer was monocrystallized. Thereafter, as shown in FIG. 3C, the single crystal silicon formed on the polishing stopper layer 20 was removed by CMP or mechanical polishing. Thereafter, as shown in FIG. 4A, a (111) TiN barrier metal 22 is epitaxially grown by a reactive sputtering method at a substrate temperature of 600 ° C.
3, a 100 nm thick Re-50% Ru alloy thin film was formed by sputtering at a substrate temperature of 600 ° C.
Epitaxial growth was performed in the orientation. Thereafter, patterning was performed by photolithography and plasma etching. And
As shown in FIG. 4B, BS having a molar fraction of Sr of 25% was used.
The T high dielectric constant thin film 26 was epitaxially grown on the (111) plane by a sputtering method at a substrate temperature of 600 ° C. Next, as shown in FIG. 4C, an interlayer insulating film was deposited, the interlayer insulating film was opened by photolithography and ion etching, and a nickel upper electrode 25 was formed. At this time, the BST film 26 has a lattice constant of 0.1.
3931 nm, the lattice constant of the Re-Ru alloy 23 is 0.2
When converted to a fcc (111) plane by doubling the square root at 738 nm, the lattice constant ratio was 1.015. When the relative dielectric constant was measured, a large value of 650 was obtained. As described in detail above, according to the present invention,
A hexagonal (0001) -oriented conductive substrate or a cubic crystalline conductive substrate is used as the lower electrode, and a dielectric film having a perovskite-type crystal structure epitaxially grown on the (111) plane is used. As a result, it is possible to increase the amount of stored charge, induce ferroelectricity, reduce variation between charge storage elements, realize ultra-high resolution by dry etching of a lower electrode, and the like, and as a result, highly integrated semiconductor memory An element can be realized. Therefore, the industrial value of the present invention is extremely large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a manufacturing process of a memory cell according to an embodiment of the present invention in the order of steps. FIG. 2 is a sectional view showing a manufacturing process of a memory cell according to one embodiment of the present invention in the order of steps. FIG. 3 is a sectional view showing a manufacturing process of a memory cell according to another embodiment of the present invention in the order of steps. FIG. 4 is a sectional view showing a manufacturing process of a memory cell according to another embodiment of the present invention in the order of steps. [Description of Reference Numerals] 1,11: Silicon substrate of first conductivity type 2, 12: Inter-element isolation oxide film 3, 13 ... Gate oxide film 4, 14 ... Word line 5, 7, 15, 17 ... Interlayer insulating film 6 , 16... Second conductivity type impurity diffusion layers 8 and 18... Bit lines 11 and 21... Contact plugs 12 and 22 .. barrier metals 13 and 23... Lower electrode layers 15 and 25.

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/10 451 27/108 29/788 29/792 (72) Inventor Shuichi Komatsu 70 Yanagicho, Yuki-ku, Kawasaki-shi, Kanagawa Stock Company (56) References JP-A-3-262173 (JP, A) JP-A-62-154407 (JP, A) Kazushige Abe, et. a l. , Ferroelectric properties in epitaxially grown BaxSr1-xTi03 thin films, Journal of Applied Physics, Fields, USA, American Institute of Physics, June 15, 1995 Int.Cl. ⁷ , DB name) H01L 21/822 C30B 29/06 H01L 21/8242 H01L 21/8247 H01L 27/04 H01L 27/10 451 H01L 27/108 H01L 29/788 H01L 29/792

Claims (1)

(57) Claims 1. A silicon (111) substrate and a hexagonal (0) formed on the silicon (111) substrate and formed on the surface thereof.
(001) plane, a metal layer selected from the group consisting of Re, Ru, Os and alloys thereof, and a dielectric having a perovskite crystal structure epitaxially grown on the metal layer in the (111) plane orientation. And a film.