JP2002151656A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of the electrical characteristics of a PZT, used as a capacitor insulation film, and to prevent damages to a capacitor lower part due to oxygen heat treatment process by the selection of a lower electrode structure. SOLUTION: A ferroelectric memory is provided with a capacitor, having a lower electrode 20 formed on an inter-layer insulation film 15 and connected to a W plug electrode 16 which passes through the insulation film 15, a PZT film 24 as the capacitor insulation film formed on the lower electrode 20 and an upper electrode 25 formed on the PZT film 24. The lower electrode 20 is turned into a structure, for which an IrO2 film 23 is laminated on an Ir film 22 and IrO2/Ir is >=10 by X-ray diffraction intensity for the IrO2 film 23.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a thin film capacitor using a ferroelectric or a high dielectric as a capacitor insulating film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a ferroelectric memory (Ferroelectric Randam A), which is a nonvolatile memory using a ferroelectric thin film, has been developed.
ccess Memory) is under development. A ferroelectric memory is obtained by replacing a capacitor part of a DRAM with a ferroelectric capacitor, and has the following features and is expected as a next-generation memory.

[0003] Writing and erasing are performed at a high speed, and the size of the cell is reduced, so that a writing time of 100 ns or less is possible, unlike a DRAM. Unlike an SRAM, it is a non-volatile memory, and does not require a power supply. By devising a dielectric material (such as SBT) and an electrode material (such as IrO _x , RuO _x , SrRuO ₃ ), rewriting can be performed more than 10 ¹² times, high density and high integration can be achieved, and a degree of integration equivalent to that of DRAM can be achieved. It has the following features: the internal write voltage can be about 2 V, low power consumption is possible, and unlike flash memories, bit rewriting and random access are possible. By taking advantage of these advantages,
Various applications have been put to practical use or studied.

In a ferroelectric memory, P
ZT (Pb (Zr _x Ti _1-x ) O ₃ ), BIT (Bi ₄
A ferroelectric thin film such as Ti ₃ O ₁₂ ) or SBT (SrBi ₂ Ta ₂ O ₉ ) is used. Each has a crystal structure based on a perovskite structure based on an oxygen octahedron. Paraelectric BST, which is currently being studied as a capacitor material for DRAMs, has a similar structure. These materials cannot be used in an amorphous state unlike a conventional Si oxide film. Therefore, the process for crystallization,
For example, a crystallization heat treatment at a high temperature or a crystallization process during film formation at a high temperature is required. Generally, a temperature of 400 to 700 ° C. is required for crystallization, depending on the material.

Various methods such as a laser ablation method, a vacuum evaporation method, and an MBE method have been studied as a film forming method, but those which have been put to practical use include MOCVD method, sputtering method, and solution method (CSD: Chcmical method). So1ution Depositi
on). In the MOCVD method and the sputtering method, there are both a crystallization method during film formation and a crystallization method after film formation, depending on the film formation temperature.
In the following, a structure of a ferroelectric thin film capacitor and a method for producing the same will be described as an example.

[0006] Ferroelectrics have spontaneous polarization, and have the characteristic that the spontaneous polarization can be reversed by an electric field. It has a polarization value even when no electric field is applied (residual polarization), and its value (or the direction of polarization) depends on the state before the electric field is set to zero. The electric field value at which the polarization value becomes 0 in the hysteresis curve is called a coercive electric field. + And-charges can be induced on the crystal surface in the direction of the applied electric field, and this state corresponds to 0 and 1 of the memory element. The same 1T / 1C (one transistor / one capacitor) structure as a DRAM can be used in combination with a switching transistor. However, at present, a 2T / 2C structure is employed to improve reliability and is taken out to the outside. The signal volume is increasing. The following characteristics and specifications are required for ferroelectric materials.

A large amount of inversion polarization (switching charge). This depends on the device structure, switching operation, polarization value stability, etc., but is generally 10 μC / cm ^2.
Is needed. Low relative permittivity. When the relative dielectric constant is small, the non-switching current value is small with respect to the switching current, and S
/ N ratio can be suppressed. The decrease in the polarization value (fatigue deterioration) due to the rewrite cycle is small. Fatigue characteristics are SBT of ferroelectric material itself
By changing to a system or using an electrode material as an electrode material, characteristics of 10 ¹² times or more are obtained.

[0008] The polarization inversion speed is high. It is shown that the switching characteristics mainly depend on the electrode wiring resistance, stray capacitance, etc., rather than the net domain inversion speed due to the miniaturization of the capacitor. Leakage current is 10 ^-6 A / cm ² or less. Compared with a DRAM that uses the presence or absence of electric charge stored in a capacitor, a ferroelectric memory uses a residual polarization value, so that a reference leakage current value is higher than that of a DRAM, and there is no problem. It is sufficient that a reference voltage is applied to the capacitor. Data retention characteristics for more than 10 years.

The ferroelectric material actually used is P
ZT and SBT. The former has a crystallization temperature of about 600 ° C
Degree, the polarization value is large and the remanent polarization value is 30 μC /
cm ^TwoThe coercive electric field is relatively small and low voltage
Possibility of polarization reversal, changing Zr / Ti composition ratio
Crystallization temperature, grain size, grain shape
Structural characteristics such as polarization, coercive electric field, fatigue characteristics, leakage current
Control of ferroelectric properties such as flow, perovskite
Pb called A site is converted to S
Elements such as r, Ba, Ca, La, etc.
Nr, W, Mg, Co, Fe, Ni, M
can be replaced by an element such as n
Significant influence on structure, structural characteristics, ferroelectric characteristics, etc.
Is an advantage.

Originally, PZT was applied to transducers, passive components such as multilayer ceramic capacitors,
Numerous studies have been made on applications to infrared sensors, etc., as well as structural phase transitions, domain behavior, piezoelectricity, pyroelectricity, and ferroelectric properties.
One advantage is that there is a wealth of databases for suppressing structural and electrical characteristics. Since PZT has excellent piezoelectric, pyroelectric, and ferroelectric properties, thinning of the film has been studied from an early stage, and there are many examples of research on film formation by a method such as a sputtering method or a sol-gel method. From these backgrounds, PZT is a material that was first put to practical use as a ferroelectric memory. Decrease in polarization with an increase in the number of write operations is a drawback (fatigue properties) can fatigue itself to have the features that are accelerated by the electric field, the recent reduction in voltage, from Pt electrode that was originally used IrO _2, etc. The improvement has been achieved by adopting the oxide electrode.

On the other hand, the latter SBT is a material developed to improve the fatigue characteristics of PZT and achieve low voltage driving of the film. SBT is a Bi layered compound (Aurivi11ius)
Phase), which has a crystal structure in which a Bi ₂ O ₂ layer sandwiches a pseudoperovskite structure layer composed of an oxygen octahedron that is a ferroelectric origin. With this structure, the main polarization axis is in a plane perpendicular to the C-axis, and there is no polarization in the C-axis direction or a small value even if it exists. The polarization is expressed by the number of oxygen octahedra in the pseudo perovskite structure. Due to the strong anisotropy, there has been almost no research on ceramics. However, thin films can be formed by the MOD (Metalorganic Decomposition) method, and development has been made because the formed polycrystalline SBT film exhibits ferroelectricity. It has been confirmed that the battery has good fatigue characteristics and low voltage can be used, and the development is further accelerated.

The main cause of fatigue deterioration of the PZT film is oxygen vacancies formed at the Pt electrode interface. One of the reasons for the generation of oxygen vacancies is the volatility and ease of diffusion of the Pb element. Since Pb is part of the perovskite structure, Pb
When oxygen vacancies are formed due to the b-defect, dipoles are formed with nearby cation vacancies, causing a decrease in switching charge. SBT is free of Bi, which is a volatile element. Alternatively, since the formation of the oxygen vacancy for compensating the electric charge itself is formed in the Bi oxide layer between the layers, the influence of the direct perovskite structure is small. It is also considered that the absence of Ti whose valence changes easily does not cause defects.

SBT has a smaller amount of polarization than PZT, but it is possible to increase the amount of polarization by replacing part of Ta with Nb. Recently, a device in which the SBT is integrated as a capacitor has also been prototyped. SBT is formed by a sol-gel method, a sputtering method, a laser ablation method or the like in addition to the MOD method. PZT film is also MOD
It is formed by a method, a laser ablation method, an ion beam sputtering method, an MOCVD method, a laser CVD method, or the like, and a sol-gel method or a sputtering method is used as a ferroelectric memory product.

[0014] In the sputtering method, to form a crystallized perovskite PZT film directly on a substrate, a temperature of about 500 ° C.
Although the above high temperature is necessary, it is difficult to control because the low melting point element Pb is easily evaporated and re-sputtered from the substrate at a high temperature because of a high vapor pressure and a high sputtering rate. Therefore, at a crystallization temperature of 500 ° C. or higher, P
b hardly stops on the substrate and composition control is difficult. Usually, in the case of high-temperature sputtering, Pb or PbO targets are separately prepared, and at the same time, a method is devised to supply an excessive amount of Pb by sputtering, but it is not possible to form a film by controlling the composition uniformly on a large substrate. difficult. At room temperature, Pb evaporates,
Since the influence of re-sputtering is small, a PZT film having a composition close to the target can be formed relatively easily. However, even at room temperature, the substrate and the shield part are likely to be heated to a high temperature due to the impact of ions and sputter particles from the plasma, and the influence of evaporation and re-sputtering may be exerted. The composition changes because the impact of ions also differs depending on the potential of each part.

A process for forming a ferroelectric film used for an electronic component will be described with an example of a ferroelectric memory using a PZT ferroelectric film. An insulating film is formed on a Si substrate that has undergone a transistor forming process, and a 150
A Pt electrode having a thickness of nm is formed by DC magnetron sputtering. Since Pt does not have good adhesion to an oxide film, Ti (20 nm) is formed as a bonding layer by continuous sputtering before Pt film formation. Next, the PZT film is RF-coated on the underlying electrode.
It is formed by magnetron sputtering. For the above reasons, the film is formed at room temperature without increasing the substrate temperature. Sputtering is performed on a 12-inch ceramic PZT target at 1.0 to 1.5 kW. Sputtering gas is 0.5 to 2.0 Ar
The film was formed in a pressure range of Pa. With a sputtering time of about 5 minutes, a PZT amorphous film having a thickness of 250 to 300 nm can be obtained. The composition was stabilized by performing pre-sputtering for about 1 hour before forming the PZT film.

The amorphous PZT film is made of RTA (Ra
Crystallizes into a perovskite phase by the pid Themal Annea1) process. Crystallization is possible in a few seconds at a temperature of 600 ° C. or higher. Although crystallization can be performed even in a tubular furnace or the like, RTA has a smaller thermal budget, can suppress the diffusion and reaction between the base electrode and the PZT film, and is suitable for the smoothness of the interface. In addition, during the crystallization of PZT, there is a possibility that a non-ferroelectric phase pyrochlore-type oxide is formed as a different phase.
It is easily formed when the r / Ti ratio is large. When the pyrochlore phase is formed as the second phase, not only the amount of polarization is reduced, but also the reliability of the PZT film is affected.

With respect to the crystallized PZT film, a Pt film as an upper electrode is further formed by DC magnetron sputtering to form a capacitor film structure. Hereinafter, a capacitor processing process using RIE and an upper wiring process are used. Capacitor is RIE (Reactive Ion Etchi
ng) Using a device, etching is performed in a gas of Ar, chlorine and carbon fluoride to form a fine pattern. After processing the capacitor, 600 to improve the adhesion to the electrode
Annealing is performed at 1 ° C. in oxygen for 1 hour.

On the other hand, in a PZT film forming process formed by a solution method (CSD method) such as a sol-gel method or a MOD method, the characteristics, ease of handling and stability of the raw material, and the reactivity when mixed with other substances are considered. , Pb, Ti, and Zr are first selected as raw materials for PZT film constituent elements.

In the sol-gel method, lead acetate trihydrate is often used for Pb, zirconium tetrapropoxide for Zr, and titanium tetraisopropoxide for Ti in many cases. 0.2M
A solution of is first prepared. This solution can be stored for a long time by removing water sufficiently. Generally, the water component of the hydrate of lead acetate is removed. When forming a film, water is added to this solution to cause a polycondensation reaction, but an MOM crosslinked structure is formed by a dehydration reaction and a dealcoholization reaction. The amount of water added at this time, reaction time (retention time), p
This cross-linking state changes depending on H, temperature, concentration, and the like. Since an amorphous state different from amorphous sputtering is formed, the orientation, crystal grain shape, ferroelectric characteristics, leak current, fatigue characteristics, and the like change when crystallized into a PZT perovskite structure.

The same applies to the MOD method. Pb,
A MOD solution of PZT is prepared using xylene as an organic solvent using 2-ethylhexanoic acid of Zr and Ti or the like. In the case of the MOD method, a hydrolysis reaction does not occur, and the coating is performed on the substrate in that state (mixed state). After the film is formed on the substrate, drying and desolvation are carried out at a low temperature of about 250 ° C., and a PZT film in an amorphous state is obtained. In the MOD method, since the raw material has a structure containing a large amount of C, H, and O, the film shrinks greatly at the time of crystallization. To form a thick film having a thickness of several 100 nm, the coating and crystallization steps are repeated. For crystallization, RTA is often used in the same manner as sputtering. 750
A perovskite single phase is obtained by heat treatment at about 5 ° C. for about 5 minutes. A PZT film using such a solution method has a crystal grain of 10
In many cases, a granular structure which is as small as 0 to several hundred nm and does not show a columnar structure like a film formed by sputtering is observed.

On the other hand, PZT, SBT
When a film or the like is formed, by optimizing the conditions, a capacitor having good step coverage for forming a three-dimensional capacitor can be obtained. However, there are many difficulties in the MOCVD technique for these ferroelectric and dielectric materials. For example, it is difficult to control the film composition. Since Sr, Ba, and the like, which are constituent elements of the composite oxide, do not have a source material having a high vapor pressure, it is necessary to adopt a method in which liquid supply is used in combination. In addition, it is difficult to set the optimal film forming conditions because the characteristics of the source of each element are different. There are situations in which the supply amount of the raw material and the film composition are not always proportional. In addition, when adding an additive, it is necessary to further select a source, so that the difficulty increases. In the process of obtaining a crystallized film during film formation, the characteristics and characteristics of the film formed thereon change depending on the state and composition of the surface of the substrate (electrode surface). In the MOCVD technique of the PZT film, an attempt has been made to stabilize the PZT composition in a self-controlling manner by using a high vapor pressure of a Pb compound, and a crystallized film is formed on Pt and Ir at the time of film formation.

In recent years, COP (CaP) has been developed in order to produce a high-density ferroelectric memory utilizing the film forming method described above.
pacitor on plug) structure is considered. This is because the W or Si is connected from the active area of the transistor.
Since the plug structure consisting of is directly under the capacitor, the cell size can be reduced. The sputtering method, the coating method, and the MOCVD method described above can be used for a planar capacitor, and the MOCV is used for a three-dimensional capacitor structure.
The D method may be used. However, in this structure, when the ferroelectric film is crystallized or when the capacitor is integrated, RIE processing and insulating film CVD are performed.
There is a problem that the surface of the plug material immediately below is oxidized at the time of heat treatment for reversing the damage such as the contact resistance is increased, or peeling occurs in an extreme case.

In order to avoid this, TiAlN, Ti
Formation of barrier layer such as N, TaSiN, IrO ₂ , I
Attempts have been made to use lower electrode materials such as r, RuO ₂ and Ru. Also, attempts have been made to form a three-dimensional capacitor as described above. Also in the film formation by the MOCVD method, a method of forming a film at a low temperature with good composition controllability and step coverage and crystallizing a dielectric film and a ferroelectric film in a subsequent heat treatment is performed. Also, the RIE of the capacitor
For the purpose of reducing processing damage, a capacitor making process using a damascene process has also been proposed.

On the other hand, 1Tr (transistor) type ferroelectric memories for further increasing the density of ferroelectric memories are also being developed. In the past, ferroelectric materials such as Bi ₄ Ti ₃ O ₁₂ were formed directly on the gate of Tr, but research and development was carried out. However, an oxide interface layer was formed at the interface with Si, and only a specific material was crystallized. It is difficult to realize because there are obstructive factors such as inability to control the reaction at the interface, and the like. For materials such as PZT, S
It is difficult to crystallize on iO ₂ . This is RT
When a crystallization heat treatment method such as A is employed, crystallization tends to proceed from the substrate side, but Pb and SiO ₂ in PZT react first to form a deteriorated interface, on which P
This is because ZT does not crystallize. It is possible to increase the amount of Ti in PZT to lower the crystallization temperature and promote crystallization from above or inside the film, but in this case, it is difficult to control the crystallization. In addition, the reaction with the underlayer was inevitable, and it was not satisfactory for producing a 1Tr type ferroelectric memory.

[0025]

As described above, the conventional PZ
The characteristics of the ferroelectric thin film such as T are greatly affected by the lower electrode because the amorphous film is crystallized on the lower electrode. The leak characteristics, CV characteristics, polarization characteristics, retention characteristics, fatigue characteristics, imprint characteristics, etc. of the ferroelectric thin film are determined by the electrode material,
It depends on the structure, especially the lower electrode structure. Currently, Ir-based and Ru-based thin film materials are being studied for the lower electrode. However, unlike the conventionally used Pt electrode, I
For r-based and Ru-based electrodes, the crystallinity (crystal orientation and crystal microstructure) of a ferroelectric film such as a PZT film formed thereon
Are deteriorated, the reaction between Ru, Ir and Pb at the interface, and the diffusion of elements into the grain boundary portion increase the leakage current.

On the other hand, the COP structure and the 1Tr type structure require a structure that prevents oxidation at the interface with the lower plug material and a structure that does not form defect levels or impurity levels at the interface with Si. You. In a ferroelectric thin film process such as a PZT film, RTA (55
0-700 ° C.), RIE processing of a capacitor, deposition of an interlayer insulating film by CVD, passivation S
There is a step of performing recovery annealing (500 to 650 ° C.) in oxygen for the purpose of repairing damage caused by iN film formation or the like. Even after these steps, it is necessary that the plug material and the Si interface do not deteriorate due to oxidation or the like. The purpose of improving the oxygen barrier property is required for the lower electrode structure.

The above problem is not limited to the case where a ferroelectric substance is used, but also applies to the case where a high dielectric substance is used.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to reduce the electric characteristics of a ferroelectric thin film or a high-dielectric thin film, and further to perform an oxygen heat treatment step. To provide a semiconductor device having a capacitor structure that does not damage the lower portion of the capacitor, and a method of manufacturing the same.

[0029]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, the present invention is formed on an interlayer insulating film,
A lower electrode connected to a plug electrode penetrating the insulating film, a capacitor insulating film formed of a ferroelectric or high dielectric formed on the lower electrode, and an upper electrode formed on the capacitor insulating film; Wherein the lower electrode is formed of Ir on the Ir film.
A semiconductor device having a structure in which an O ₂ film is laminated, wherein the IrO ₂ film has an IrO ₂ / Ir of 10 or more in X-ray diffraction intensity.

According to the present invention, there is provided a semiconductor device comprising:
Lower electrode connected to a plug electrode penetrating the insulating film
And a ferroelectric or high dielectric formed on this lower electrode
Capacitor insulating film consisting of
Having a capacitor with an upper electrode formed on the substrate
A conductor device, wherein the lower electrode is made of a film containing Ir.
Between the lower electrode and the capacitor insulating film.
O_ThreeOr Pb_TwoIr_TwoO _7-x-Based conductive composite
It is characterized by being provided with an oxide layer.

Further, according to the present invention, there is provided a semiconductor device comprising:
A lower electrode connected to a plug electrode penetrating the insulating film, a capacitor insulating film formed of a ferroelectric or high dielectric formed on the lower electrode, and an upper electrode formed on the capacitor insulating film; Wherein the lower electrode is made of a film containing Ir, and has a thickness of 4 to 4 between the lower electrode and the capacitor insulating film.
It is characterized by having a 50 nm SRO (SrRuO ₃ ) layer.

The present invention is not limited to the case of a capacitor formed on an interlayer insulating film, but also applies to a case where a similar capacitor structure is formed directly on a gate electrode of a transistor or via an insulating film. . In that case, a similar structure utilizing the oxygen barrier property can be obtained although it is not located on the plug.

Here, preferred embodiments of the present invention include the following. (1) The IrO ₂ film has a columnar structure. (2) The lower end of the plug electrode is connected to one of the source / drain regions of the MOS transistor formed on the substrate. (3) The upper electrode has a structure containing Ru and RuO ₂ as main components or an electrode structure containing SRO. (4) The capacitor insulating film is made of PZT (Pb (Zr _x Ti
_1-x O ₃ ).

The present invention also relates to a method of manufacturing a semiconductor device having a ferroelectric capacitor using a ferroelectric or a high dielectric as a capacitor insulating film, wherein a step of forming a switching MOS transistor on a semiconductor substrate is provided. Forming an interlayer insulating film on the transistor to planarize the surface, forming a plug electrode connected to one of a source and a drain of the transistor by burying the interlayer insulating film, and connecting to the plug electrode. Forming an Ir film as a lower electrode on the interlayer insulating film, forming an IrO ₂ film on the Ir film,
_The method includes a step of forming a capacitor insulating film made of a ferroelectric or a high dielectric on the _two films, and a step of forming an upper electrode on the capacitor insulating film.

(Function) According to the present invention, by using Ir having a high barrier property against oxygen as the lower electrode, it is possible to prevent the oxidation of the plug electrode such as W located under the lower electrode and the oxidation of Si. it can. Also, Ir and P
IrO ₂ between the capacitor insulating film made of ZT like, IrO ₂ / Ir is 10 or more IrO _2, especially in the X-ray diffraction intensity
By providing the film, the film quality of the capacitor insulating film can be improved. The same effect as described above can be obtained by using a conductive composite oxide layer containing SRO (particularly, 4 to 50 nm in thickness), SrIrO ₃ or Pb ₂ Ir ₂ O _7-x as a main component instead of IrO _2. Is obtained.

Accordingly, a semiconductor device having a capacitor structure without deteriorating the electrical characteristics of a capacitor insulating film made of a ferroelectric or a high dielectric and without damaging the lower portion of the capacitor in an oxygen heat treatment step is provided. It can be realized.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIGS. 1A and 1B are diagrams for explaining a ferroelectric memory according to a first embodiment of the present invention. FIG. 1A is a sectional view showing the structure of a cell portion, and FIG. () Is an enlarged sectional view of a capacitor portion.

In this embodiment, PZT, which is a ferroelectric film, is used as the capacitor insulating film. As shown in FIG. 1A, a MOS transistor is formed on a Si substrate 10, the transistor region is flattened with an interlayer insulating film 15 such as PSG or BPSG, and a silicon oxide film (SiO ₂ ) and A silicon nitride film (SiN) (not shown in FIG. 1A) is formed. Insulating film 15 has W connected to one of the source and drain of the transistor.
The plug 16 is embedded. This plug 16
A lower electrode 20 composed of a TiAlN barrier layer, an Ir film, and an IrO ₂ film is formed thereon, a PZT film 24 as a ferroelectric is formed thereon, and an Ir film as an upper electrode 25 is formed thereon. I have. In the figure, 11 is an element isolation insulating film, 12 is a gate oxide film, 13 is a gate electrode, 14
Reference numerals a and 14b denote source / drain regions.

Next, the characteristic portion of the ferroelectric memory of this embodiment, particularly, the capacitor portion will be described in detail according to the manufacturing process.

First, a switching MOS transistor is formed on a Si substrate by a normal process. And
An insulating film such as PSG or BPSG is formed over the transistor region by a CVD method, and its surface is planarized by using a CMP method. Next, as shown in FIG. 1B, a SiO ₂ film 17 and a SiN film 18 are formed by a CVD method to form a base substrate. Here, since the connection between the capacitor and the active area (source, drain) of the transistor is made using a plug made of W or polycrystalline Si, a W plug 16 is formed in advance. As the plug material, a material in which TiN is embedded by CVD instead of W and Si may be used. The plug 16 is formed by using both a blanket CVD method and a CMP method.

Next, a barrier metal layer 21 is formed for the purpose of preventing the plug surface from being oxidized in an oxygen annealing process for forming a ferroelectric thin film or securing capacitor characteristics thereafter. The barrier layer 21 is made of Ti
AlN (Ti / Al = 0.9 / 0.1 (molar ratio)) was used. The thickness is 50 nm. Here, it is not always necessary to form the barrier layer 21 over the entire lower surface of the lower electrode, and the barrier layer 2 is formed only on the plug 16 in a state where the plug 16 is recessed.
1 may be formed, or may be formed on the entire lower surface of the lower electrode when the lower electrode is formed. Further, when the Ir layer is thick and the heat treatment of the crystallization temperature of the PZT film and the value of the capacitor processing is performed in a short time and at a low temperature (for example, crystallization at 500 ° C. and post heat treatment 500).
C.) may be made of TiN or Ti as the barrier layer of TiAlN. Thereby, the whole process will be slightly different. Specifically, the barrier layer 21 is formed on the connection surface with the plug 16 by using a DC magnetron sputtering method.

Next, a lower electrode is formed on the barrier layer 21.
Is formed by sputtering. The film thickness is 100
nm. I was sputtered with oxygen
rO _xThe film 23 is formed to a thickness of 50 nm. This spatter
The Ar / O using DC magnetron sputtering._Two
= 30/70, room temperature, 1 kW sputtering power of 300 m
The test was carried out by introducing a target having an m diameter. X-ray rotation immediately after film formation
In the figure, a structure close to the amorphous state was detected.
Characteristic grains are not visible when observing morphology
Shows a flat structure.

Prior to the formation of PZT, a process such as heat treatment at 550 ° C. using RTA is performed.
The crystallinity of rO ₂ may be increased. In this case, FIG.
As shown in (d), a columnar-grown structure is observed. When the intensity ratio of Ir and IrO _{2 in} the IrO ₂ film portion was determined by X-ray diffraction, as shown in FIG.
The peak size of the IrO ₂ peak is 10
More than double. This structure is the same when RTA crystallization is performed after forming the PZT film on the electrode. The Ir film 22 has a role of securing a barrier property to the plug in the oxygen annealing step. On the other hand, the IrO ₂ film 23 at the interface suppresses diffusion and reaction with the PZT film 24, and reduces leakage current.

On the other hand, when the oxygen amount of the sputtering gas during the IrO ₂ film formation is reduced (Ar / O ₂ = 70/30),
As shown in FIG. 3A, the intensity ratio becomes IrO ₂ / Ir <10 by X-ray diffraction after PZT crystallization, and a clear Ir peak is observed. Further, the fine structure of the Ir-based electrode film after the heat treatment has a fine granular structure or a tightly packed structure that causes bulk intragranular fracture. When the oxygen barrier property against plugs such as W was evaluated, the barrier property of Ir alone was the best.

FIGS. 2A to 2D are micrographs showing a crystal structure when an IrO ₂ film is formed by sputtering in an Ar / O ₂ gas after the formation of the Ir film.
Is Ar / O ₂ = 100/0, (b) is Ar / O ₂ = 90
/ 10, (c) is Ar / O ₂ = 70/30, (d) is A
The case where r / O ₂ = 30/70 is shown. FIG.
Is an X-ray diffraction diagram of IrO ₂ , and as shown in FIG.
When rO ₂ / Ir <10, a high quality film cannot be obtained in the later-described PZT film formation. As shown in FIG. 3 (b), IrO2 /
It has been confirmed by experiments by the present inventors that good results can be obtained in PZT film formation described below when Ir ≧ 10.

Next, a PZT film 24 is formed on the IrO ₂ film 23 by using a sputtering method. The PZT film 24 was formed by RF magnetron sputtering. Here, a PZT ceramic target whose Pb content is increased by about 10% is used. The composition of the target is Pb _1.10 La
_0.05 Zr _0.4 Ti _0.6 O ₃ . A PZT ceramic target having a high density has a high theoretical density of 98 because it has a high sputtering rate and good environmental resistance to moisture and the like.
% Ceramic sintered body was used. At the time of sputtering, since the substrate temperature rises due to plasma and there is bombardment due to flying particles, evaporation and re-sputtering of Pb from the Si substrate occur, and the amount of Pb in the film is easily lost. Excess Pb in the target has been added to compensate for it. Elements such as Zr, Ti, and La are taken into the film in substantially the same amount as the target composition, so that a material having a desired composition ratio may be used.

If the electrical characteristics are unstable due to the composition of the PZT film, a seed layer is formed on the amorphous PZT film. For example, a sputtering method in which oxygen is introduced is used to improve the structure and electrical characteristics of the PZT film to be crystallized. First, a sputter film is formed in an atmosphere in which Ar is introduced,
Later, a PZT seed layer is formed by sputtering in Ar with oxygen added. Sputtering conditions were as follows: the distance between the target and the substrate was 60 mm, and a 1.0-1.5
Sputter at kW. A film is formed for 15 to 30 seconds under the conditions that the gas pressure is 0.5 to 2.0 Pa and oxygen is introduced into Ar at 20% to form a PZT amorphous seed layer having a thickness of 2 to 5 nm. Subsequently, a gas pressure of 0.5 using only Ar gas is used.
PZT by RF magnetron sputtering for about 5 minutes at a power of 1.0 to 1.5 kW and power of 1.0 to 1.5 kW
A film is formed. The film thickness is 100 to 150 nm. Instead of the PZT film, a thin Ti film, Zr film, Nb film, Ta film or the like having a thickness of about 2 to 5 nm may be used for the seed layer.

Before forming the PZT film, pre-sputtering was performed for about 1 hour under the same sputtering conditions in order to keep the target surface state, temperature and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by the pre-sputtering. The amorphous PZT film formed on the Ir-based electrode formed on the plug via the barrier layer is subjected to crystallization of the PZT film using RTA. When the crystal structure of the obtained film was examined by X-ray diffraction, a very strong reflection from the (100) plane was obtained in the perovskite phase. Microstructure observation results show that P
ZT particles are formed on IrO ₂ having a columnar structure.

Next, an Ir film 25 was formed as an upper electrode on the PZT crystal film 24 by DC magnetron sputtering. Since the upper electrode 25 has low reactivity with the ferroelectric,
Leakage rarely occurs even through a heat treatment process such as TA. The electrode pattern was formed by etching in a mixed gas of Ar and chlorine using RIE to form a fine pattern. That is, a resist pattern or an oxide film pattern on the upper electrode 25, which upper electrode 25 as a mask, PZT films 24, IrO ₂ layer 23, Ir film 22 was selectively etched barrier layer 21.

In order to improve the adhesion to the upper electrode 25 and the coherence of the crystal, annealing was performed at 350 ° C. in nitrogen for 30 sec to obtain ferroelectric characteristics. As a result of examining the ferroelectricity by the hysteresis characteristic of the charge amount Q-applied voltage V,
Approximately 3 with a polarization amount of 2 Pr (remanent polarization x 2) when 2.5 V is applied
The PZT film showed 0 μC / cm ² and was found to be a PZT film having the same amount of polarization and coercive electric field over the entire surface of an 8-inch Si wafer. The coercive voltage was as low as about 0.6 V. The fatigue properties of this sample were evaluated. Fatigue property evaluation is 50 μm × 5
Evaluation was performed on an array corresponding to an area of 0 μm. 10 ¹²
There was no change in the amount of polarization until the polarization reversal of the cycle, and the leak current was a low value of the order of 10 ^-8 A / cm ² when 3 V was applied.

Thereafter, although not shown, the contact from the capacitor upper electrode 25 uses a normal LSI fabrication process. That is, the wiring is drawn out from the capacitor by repeating the insulating film, RIE, and wiring forming steps.

As described above, according to the present embodiment, since the Ir film 22 used as the capacitor lower electrode has a large barrier property against oxygen, the oxidation of the W plug 16 can be reliably prevented. PZT is directly formed on the Ir film 22.
When the film 24 is formed, the film quality (ferroelectric characteristics, uniformity of the film) deteriorates, and the fatigue characteristics deteriorate. On the other hand, by interposing the IrO ₂ film 23 that is a conductive oxide as in the present embodiment, the PZT film 24 can be formed with good film quality, and the fatigue characteristics can be improved. In particular, if the X-ray diffraction intensity of the IrO ₂ film 23 IrO ₂ / Ir 10 or more, IrO ₂ film 23 exhibits a columnar structure,
It has been confirmed that the PZT film 24 formed thereon becomes a very high quality film.

(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a capacitor part of the ferroelectric memory according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. This embodiment differs from the first embodiment described above in that an SRO film 33 is used instead of the IrO ₂ film 23.

First, a transistor is formed on a Si substrate by a normal process, an interlayer insulating film is formed on the transistor region, the surface is flattened, and an SiO ₂ film 17 and a SiN film 18 are formed thereon to form a base substrate. W for interlayer insulating film
The plug 16 is formed, and the barrier metal layer 21 is formed so as to be connected to the plug 16. Further, an Ir film 22 is formed on the barrier layer 21 by a sputtering method. So far,
This is the same as in the first embodiment.

Next, an SRO film 33 is formed on the Ir film 22 to a thickness of about 50 nm. This sputtering was performed by DC magnetron sputtering using an SRO ceramic target, and an Ar atmosphere, room temperature, and a sputtering power of 300 W were introduced into a target having a diameter of 300 mm. Since SRO immediately after film formation has an amorphous structure, it is crystallized by performing a heat treatment process at 650 ° C. using RTA.
The Ir film 22 plays a role in securing a barrier property to the plug in the oxygen annealing step. On the other hand, the SRO film 33 at the interface suppresses diffusion and reaction with the PZT film, and reduces leakage current. This structure is effective because the interface between SRO and PZT is good in terms of electric characteristics (polarization saturation characteristics, fatigue characteristics, retention characteristics) of the PZT capacitor.

Here, the SRO film 3 is directly formed on the Ir film 22.
3 has been described, but SRO and I
By inserting a Pt film of about 5 to 200 nm at the interface with r, the leak current can be further reduced. Accordingly, the thickness of the SRO film 33 can be reduced to about 10 nm. When the SRO film 33 is formed directly on the Ir film 22, it is necessary to increase the thickness of the SRO film 33 to about 50 nm in order to secure the barrier property of Pb and Ir by the SRO film 33, but insert Pt. SRO film 33
Good hysteresis characteristics can be obtained even if the thickness is reduced to 4 nm. That is, the thickness of the SRO film 33 used here is 4
Good hysteresis characteristics can be obtained in the range of ５０50 nm. When the interface with the SRO film is changed to IrO ₂ as an Ir / IrO ₂ laminated film instead of Ir, Pt
Good hysteresis characteristics with little leakage current can be obtained without a film.

Here, P is formed on the Ir electrode through an SRO film.
FIG. 5 shows the hysteresis characteristics when the ZT film is formed. FIG. 5A shows that the SRO10
nm, and a PZT film is formed thereon.
This is the hysteresis characteristic of the ZT capacitor, and it can be seen that the hysteresis characteristic is broken. Also, the leakage current is 1
It was as large as 0 ^-4 A / cm ² . FIG. 5 (b)
Forming a SRO10nm through Pt10nm on Ir electrode, the hysteresis characteristic of the upper PZT capacitor created by forming a PZT film, FIG. 5 (c) to form a SRO10nm through IrO ₂ film on Ir electrode And a hysteresis characteristic of a PZT capacitor formed by forming a PZT film thereon. It can be seen that (b) and (c) show good characteristics in each case. From this, SRO is 10
When the thickness is as thin as nm, it is desirable that Pt or IrO ₂ be interposed instead of forming SRO directly on Ir.

Next, a PZT film 24 was formed on the SRO film 33 by using a sputtering method. The formation of the PZT film 24
This is the same as in the first embodiment. Next, as in the first embodiment, an Ir film 25 is formed on the PZT film 24 as an upper electrode.
Was formed by DC magnetron sputtering. Pt, I
In dry etching of a noble metal such as r, etching cannot be performed because a compound having a high vapor pressure cannot be obtained, and re-deposition of an etching substance on the side wall of the capacitor becomes a problem.
In order to prevent this, a method in which a taper is used during the processing of the capacitor is usually employed. However, this method has a problem that the area of the lower electrode of the capacitor is large, and is not suitable for miniaturization.

The upper electrode 25 may be made of a Ru-based electrode such as Ru, RuO ₂ , SRO, etc., instead of an Ir-based electrode. In the case of a Ru-based electrode, RuO ₄ or the like is formed by plasma into which oxygen gas has been introduced, so that dry etching can be easily performed. In addition, the Ru-based electrode has a P
Since an oxide (such as RuO ₂ ) can be easily formed at the ZT interface, the upper electrode interface can be matched by low-temperature heat treatment at 350 ° C. to 500 ° C., and hysteresis characteristics can be obtained.

In this embodiment, the ferroelectricity is determined by the charge amount Q-
As a result of examining the hysteresis characteristics of the applied voltage V, 2.5
Approximately 30 μC with a polarization amount of 2 Pr (residual polarization × 2) when V is applied
/ Cm ² , indicating that the film is a PZT film having the same amount of polarization and coercive electric field over the entire surface of an 8-inch Si wafer.
The coercive voltage was as low as about 0.6 V. The fatigue properties of this sample were evaluated. Fatigue property evaluation is 50μm × 50μ
When the evaluation was performed on an array corresponding to an area of m, the polarization amount did not change until the polarization reversal of 10 ¹² cycles, and the leakage current was a low value of the order of 10 ^-8 A / cm ² when 3 V was applied.

Thereafter, although not shown, the contact from the capacitor upper electrode 25 uses a normal LSI fabrication process. That is, the wiring is drawn out from the capacitor by repeating the insulating film, RIE, and wiring forming steps.
Wiring is made by Al using reflow technology without using W plug.
Wiring technology is used. When a W plug is used, it is necessary to prevent the intrusion of hydrogen by covering the capacitor with an oxide film or a nitride film, and to prevent deterioration due to reduction at the interface between the ferroelectric film and the electrode film. Hereinafter, a passivation film is formed to complete a semiconductor device.

As described above, according to the present embodiment, since the Ir film 22 used as the capacitor lower electrode has a large barrier property against oxygen, the oxidation of the W plug 16 can be reliably prevented. PZT is directly formed on the Ir film 22.
When the film 24 is formed, the film quality (ferroelectric characteristics, uniformity of the film) deteriorates, and the fatigue characteristics deteriorate. On the other hand, by interposing the SRO film 33, which is a conductive oxide, as in the present embodiment, the PZT film 24 can be formed with good film quality, and the fatigue characteristics can be improved. In particular, when the thickness of the SRO film 33 is 4 to 50 nm, it has been confirmed that the PZT film 24 formed thereon has an extremely high quality.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a capacitor part of the ferroelectric memory according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. This embodiment differs from the first embodiment described above in that an SrIrO ₃ film 43 is used instead of the IrO ₂ film 23.

First, a transistor is formed on a Si substrate by a normal process, an interlayer insulating film is formed on the transistor region, the surface is flattened, and an SiO ₂ film 17 and a SiN film 18 are formed thereon to form a base substrate. W for interlayer insulating film
The plug 16 is formed, and the barrier metal layer 21 is formed so as to be connected to the plug 16. Further, an Ir film 22 is formed on the barrier layer 21 by a sputtering method. So far,
This is the same as in the first embodiment.

Next, S is formed on the Ir film 22 by sputtering.
rIrO_ThreeThe film 43 is formed with a thickness of about 50 nm. this
Sputtering is SrIrO_ThreeUsing a ceramic target
RF magnetron sputtering, Ar atmosphere, chamber
Temperature, 1kW sputtering power, 300mm diameter target
Was introduced. SrIrO immediately after film formation_ThreeIs Amorph
Heat at 650 ° C. using RTA
Crystallize with a treatment process. The Ir film 22 is made of oxygen
Role to ensure plug barrier properties
Fulfill. On the other hand, SrIrO at the interface_ThreeFilm 43 is a PZT film
To suppress the diffusion and reaction with, and reduce the leak current. This
SrIrO_ThreeInstead of Pb_TwoRu _TwoO_ThreeForm a layer
May be. The formation method using a sputtered film is the same.

A coating method such as a sol-gel method or a MOD method may be used other than the sputtering. Further, a layer containing Ru (S
An RO, RuO ₂ , Ru layer, etc.) can be formed and reacted with an amorphous PZT film. In addition, the reaction between Ir and SRO produces SrIrO ₃
It is also possible to create In that case, some Ti and Z
Although it may contain r, Sr, etc., it exhibits the same function as a mixed phase with the above-mentioned conductive phase or a partially substituted phase. When the oxygen barrier property against a plug such as W was evaluated, Ir alone had a good barrier property. here,
Although the process of forming SrIrO ₃ directly on the Ir electrode is described, the interface between SrIrO ₃ and Ir is
By inserting a Pt film of about 0 to 200 nm, the leak current can be further reduced. Accordingly, SrIr
The thickness of O ₃ can also be reduced to 10 nm or less.

Next, a PZT film 24 was formed on the SrIrO ₃ film 43 by using a sputtering method. The formation of the PZT film 24 was the same as in the first embodiment. Next, similarly to the first embodiment, Ir as an upper electrode is formed on the PZT film 24.
The film 25 was formed by DC magnetron sputtering. Since the upper electrode has low reactivity with the ferroelectric, leakage hardly occurs even through a heat treatment process such as RTA. As in the previous embodiment, Ru, RuO ₂ , SRO, or the like, which is not an Ir-based electrode but a Ru-based electrode, can be used as the upper electrode.

In this embodiment, the ferroelectricity is determined by the charge amount Q-
As a result of examining the hysteresis characteristics of the applied voltage V, 2.5
Approximately 30 μC with a polarization amount of 2 Pr (residual polarization × 2) when V is applied
/ Cm ² , indicating that the film is a PZT film having the same amount of polarization and coercive electric field over the entire surface of an 8-inch Si wafer.
The coercive voltage was as low as about 0.6 V. The fatigue properties of this sample were evaluated. Fatigue property evaluation is 50μm × 50μ
When the evaluation was performed on an array corresponding to an area of m, the polarization amount did not change until the polarization reversal of 10 ¹² cycles, and the leakage current was a low value of the order of 10 ^-8 A / cm ² when 3 V was applied.

Thereafter, although not shown, the contact from the capacitor upper electrode 25 uses a normal LSI fabrication process. That is, the wiring is drawn out from the capacitor by repeating the insulating film, RIE, and wiring forming steps.
As the wiring, an Al layer is used, and an Al wiring is formed by using a reflow technique without using a W plug. When a W plug is used, it is necessary to prevent the intrusion of hydrogen by covering the capacitor with an oxide film or a nitride film, and to prevent reduction deterioration of the interface between the ferroelectric film and the electrode film. Hereinafter, a passivation film is formed to complete a semiconductor device.

As described above, also in this embodiment, the PZT is directly formed on the Ir film 22 used as the capacitor lower electrode.
By forming the PZT film 24 via the SrIrO ₃ film 43 instead of forming the film 24, the PZT film 24
Can be formed with good film quality. Therefore, effects similar to those of the first and second embodiments can be obtained.

The present invention is not limited to the above embodiments. In the embodiment, PZT is used as the capacitor insulating film. However, the present invention is not limited to this.
And the like can be used. Further, it is not necessarily limited to ferroelectrics, and it is also possible to use high dielectric thin films such as TiO ₂ and Ta ₂ O ₅ . Further, the film thickness and the manufacturing method of each part can be appropriately changed according to the specifications.

In the embodiment, the case where the capacitor is formed on the substrate including the plug connected to the transistor has been described. However, the present capacitor structure can be applied to a one-transistor type ferroelectric memory. Specifically, an Ir lower electrode is formed via TiAlN, Ti, TiN or directly on the gate of the transistor on which the SiO ₂ gate oxide film is formed. Furthermore, as shown in the embodiment, SRO, SrIrO ₃ , Pb ₂ RuO ₇ , Ir
A film such as O ₂ is formed. A film such as Pt may be inserted at these interfaces to reduce the leak current. Further, a ferroelectric film such as a PZT film is formed thereon. An Ir-based or Ru-based upper electrode is used. The barrier layer, the lower electrode film, the ferroelectric film, and the upper electrode film are all formed by a film forming method such as a sputtering method. The details of the film forming conditions are as described in the embodiment.

By forming the above-mentioned capacitor structure on the gate film, it is possible to form the ferroelectric film without adversely affecting the gate portion such as reaction and diffusion.
By applying a voltage to the ferroelectric film, the direction of polarization is controlled, the resistance of the channel portion of the transistor is changed, and the ferroelectric film can be used as a memory.

In addition, various modifications can be made without departing from the scope of the present invention.

[0077]

As described above in detail, according to the present invention, an Ir film is used as a lower electrode of a capacitor, and an I-ray diffraction intensity between the Ir film and a capacitor insulating film such as PZT is obtained.
By providing an IrO ₂ film having an rO ₂ / Ir of 10 or more, the film quality of the capacitor insulating film can be improved. As a result, it is possible to realize a semiconductor device having a capacitor structure without deteriorating the electrical characteristics of the ferroelectric thin film or the high dielectric thin film, and without damaging the lower portion of the capacitor in the oxygen heat treatment step. Become. Also, instead of IrO ₂ , SRO (particularly, a thickness of 4 to
50 nm), the same effect as described above can be obtained by using a conductive composite oxide layer containing SrIrO ₃ or Pb ₂ Ir ₂ O _7-x as a main component.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of a cell portion and a capacitor portion of a ferroelectric memory according to a first embodiment.

FIG. 2 is a micrograph showing a crystal structure of a ferroelectric capacitor portion.

FIG. 3 is an X-ray diffraction diagram of an IrO ₂ film when the flow ratio of Ar / O ₂ is changed.

FIG. 4 is a sectional view showing the structure of a capacitor part of a ferroelectric memory according to a second embodiment.

FIG. 5 is a diagram showing hysteresis characteristics of a PZT capacitor according to the second embodiment.

FIG. 6 is a sectional view showing the structure of a capacitor part of a ferroelectric memory according to a third embodiment.

[Explanation of symbols]

10 ... Si substrate 11 ... the element isolation insulating film 12 ... gate oxide film 13 ... gate electrode 14 ... drain region 15 ... interlayer insulation film 16 ... W plugs 17 ... SiO ₂ film 18 ... SiN film 20 ... lower electrode 21 ... TiAlN Barrier layer 22 Ir film 23 IrO ₂ film 24 PZT film (ferroelectric film) 25 Ir film (upper electrode) 33 SRO film 43 SrIrO ₃ film

Continuation of the front page (72) Inventor Kataro Imai 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in Toshiba Yokohama Office 5F083 FR02 GA21 JA15 JA17 JA36 JA38 JA39 JA40 JA43 JA45 MA05 MA06 MA17 NA01 PR22 PR34

Claims (10)

[Claims] A lower electrode formed on an interlayer insulating film and connected to a plug electrode penetrating the insulating film; and a capacitor insulating film made of a ferroelectric or high dielectric formed on the lower electrode. A semiconductor device having a capacitor having an upper electrode formed on the capacitor insulating film, wherein the lower electrode has a structure in which an IrO ₂ film is laminated on an Ir film, and an IrO ₂ film Is the X-ray diffraction intensity of IrO ₂
/ Ir is 10 or more. 2. A lower electrode formed directly on a gate electrode of a transistor or through an insulating film, a capacitor insulating film made of a ferroelectric or a high dielectric formed on the lower electrode, A semiconductor device having a capacitor having an upper electrode formed on an insulating film, wherein the lower electrode has a structure in which an IrO ₂ film is stacked on an Ir film, and the IrO ₂ film is an X-ray IrO ₂ at diffraction intensity
/ Ir is 10 or more. 3. The semiconductor device according to claim 1, wherein said IrO ₂ film has a columnar structure. 4. A lower electrode formed on an interlayer insulating film and connected to a plug electrode penetrating the insulating film, and a capacitor insulating film made of a ferroelectric or a high dielectric formed on the lower electrode. A semiconductor device having a capacitor provided with an upper electrode formed on the capacitor insulating film, wherein the lower electrode is made of a film containing Ir, and SrIrO ₃ or Pb ₂ Ir
A semiconductor device comprising a conductive complex oxide layer containing ₂ O _7-x as a main component. 5. A lower electrode formed directly on a gate electrode of a transistor or through an insulating film, a capacitor insulating film made of a ferroelectric or a high dielectric formed on the lower electrode, A semiconductor device having a capacitor having an upper electrode formed on an insulating film, wherein the lower electrode is made of a film containing Ir, and SrIrO ₃ or Pb ₂ Ir is provided between the lower electrode and the capacitor insulating film.
A semiconductor device comprising a conductive complex oxide layer containing ₂ O _7-x as a main component. 6. A lower electrode formed on an interlayer insulating film and connected to a plug electrode penetrating the insulating film, and a capacitor insulating film made of a ferroelectric or high dielectric formed on the lower electrode. A semiconductor device having a capacitor having an upper electrode formed on the capacitor insulating film, wherein the lower electrode is made of a film containing Ir, and has a thickness of 4 between the lower electrode and the capacitor insulating film. ~ 50nm SRO
A semiconductor device comprising a (SrRuO ₃ ) layer. 7. A lower electrode formed directly or via an insulating film on a gate electrode of a transistor, a capacitor insulating film made of a ferroelectric or high dielectric formed on the lower electrode, A semiconductor device having a capacitor having an upper electrode formed on an insulating film, wherein the lower electrode is made of a film containing Ir, and has a thickness of 4 to 50 nm between the lower electrode and the capacitor insulating film. SRO
A semiconductor device comprising a (SrRuO ₃ ) layer. 8. The semiconductor device according to claim 1, wherein a lower end of said plug electrode is connected to one of a source / drain region of a MOS transistor formed on a substrate. . 9. The semiconductor device according to claim 1, wherein said upper electrode has a structure containing Ru and RuO ₂ as main components or an electrode structure containing SRO. 10. A switching MOS on a semiconductor substrate.
A step of forming a transistor, a step of forming an interlayer insulating film on the transistor and flattening the surface, and a step of forming a plug electrode connected to one of a source and a drain of the transistor by embedding in the interlayer insulating film Forming an Ir film as a lower electrode on the interlayer insulating film by connecting to the plug electrode; and forming an IrO film on the Ir film.
₂ forming a film, forming a ferroelectric or high dielectric capacitor insulating film on the IrO ₂ film, and forming an upper electrode on the capacitor insulating film. Manufacturing method of a semiconductor device.