JP4299959B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor using a ferroelectric film formed in a semiconductor memory or the like as a dielectric, and a method of manufacturing a semiconductor device using a capacitor forming flash lamp.
[0002]
[Prior art]
With the development of communication technology, in recent years, electronic devices such as mobile phones and the Internet have become portable, networked, and cost-effective. The amount of information handled by these devices, such as image information and moving image information, is also increasing, and the expansion of the memory capacity used for electronic devices is required more than ever before. In order to achieve high integration of a semiconductor memory, it is necessary to miniaturize a capacitor that plays a role of storing charges therein. For example, in the high integration of DRAM (Dynamic Random Access Memory) which is a volatile memory, the memory capacity is increased at a speed of 4 times in 3 years, and a gigabit capacity has been developed. There are several means for miniaturizing capacitors for high memory integration. For example, (1) the material itself has a high dielectric constant, (2) the thickness of the capacitor is reduced, and (3) the capacitor area is increased. For (1), tantalum oxide (Ta) is used from the silicon oxide film that has been used for capacitor materials. ₂ 0 _Five ), Barium titanate / strontium (Ba, Sr) (TiO _Three ) And other thin films have been developed. These materials have a characteristic that the dielectric constant is about 10 to 100 times higher than that of silicon oxide. Regarding the thinning of the dielectric film of (2), the silicon oxide film has been thinned so far, but if the thickness is in the region of 3 nm or less, the leak current increases due to the tunnel current. Therefore, the limit for the thin film capacitor is approaching. In order to increase the area of the capacitor in (3), a method such as a trench type in which a deep hole is formed on a silicon substrate or a stack type capacitor in which a three-dimensional shape is formed is employed from the conventional planar capacitor structure. For a memory having a capacity of megabit to gigabit, for example, a DRAM requires a charge amount of 30 fC per cell. This amount depends on the characteristics of the sense amplifier that detects the charge stored in the capacitor, the capacitance of the bit line, and the like. However, with regard to the increase in the capacitor area, it is necessary to complicate the capacitor structure, and the burden on the capacitor formation process is increasing at present.
[0003]
In recent years, a ferroelectric memory (hereinafter referred to as a Ferroelectric Random Access Memory), which is a nonvolatile memory using a ferroelectric thin film, has been developed. Ferroelectric RAM is obtained by replacing the capacitor portion of DRAM with a ferroelectric film, and has the following characteristics, and is expected as a next-generation memory. (1) High-speed writing and erasing, and a cell size of 100 ns or less is possible by reducing the size of the cell. (2) Non-volatile memory, which requires no power supply unlike SRAM. , (3) Rewriting is possible many times, ferroelectric material (SBT, etc.), electrode material (IrOx, RuOx, SrRuO) _Three Etc.) ¹² 4) High density and high integration are possible, and the same degree of integration as DRAM can be obtained. 5) The internal write voltage can be reduced to about 2V, so low power consumption. Unlike (6) flash memory, bit rewriting and random access are possible.
[0004]
Utilizing these advantages, humidity sensors for air conditioners, monitoring tags for manufacturing processes of various electronic devices, resume functions for TV games, arcade game storage devices, TV and video setting storage, copying, FAX, printers, etc. Photosensitive drum usage monitor, satellite broadcasting, cable TV set-top box, automobile engine control, radio frequency preset, electronic key using RF-ID, noisy industrial product line production process monitor, Applications in various fields such as power integrators, industrial liquids, gas flow meter sensors, large tank liquid level gauges, AV personal computers, PC cards, file memories, and portable terminal devices have been put into practical use or are being studied. ing. Ferroelectric RAM has PZT (Pb (Zr _x Ti _1-x ) O _Three ), BIT (Bi _Four Ti _Three O ₁₂ ), SBT (SrBi ₂ Ta ₂ O ₉ ) Or other ferroelectric thin film is used. All have a crystal structure based on a perovskite structure having an oxygen octahedron as a basic structure. The same applies to the paraelectric BST currently being studied as a capacitor material for DRAM. Unlike conventional silicon oxide films, these materials cannot be used in an amorphous state. Therefore, a step for crystallization, for example, a crystallization heat treatment at a high temperature, an in-situ crystallization process at a high temperature, and the like are required. Although it depends on the material, a temperature of 400 to 700 ° C. is generally required for crystallization. Various methods such as laser ablation, vacuum deposition, and MBE have been studied as film formation methods, but those that have been put to practical use include MOCVD (Metal Organic Chemical Vapor Deposition), sputtering, and solution ( CSD: Chemical Solution Deposition. The MOCVD method and the sputtering method include both an in-situ crystallization process and an ex-situ crystallization process depending on the film formation temperature.
[0005]
In the following, a structure of a ferroelectric thin film capacitor and a method for producing the same will be described as an example.
A ferroelectric has a feature that it has a spontaneous polarization, and the spontaneous polarization can reverse the direction by an electric field. Spontaneous polarization has a polarization value (residual polarization) even when no electric field is applied, and the value (direction of polarization) depends on the state before the electric field is zero. The electric field value when the polarization becomes 0 in the hysteresis curve is called a coercive electric field. Depending on the direction of the applied electric field, + and-charges can be induced on the crystal surface, and this state corresponds to 0 and 1 of the memory element. The same 1T / 1C (1 transistor / 1 capacitor) structure as that of a DRAM can be used, but at present, a 2T / 2C structure is often used in order to improve reliability. Ferroelectric materials are required to have the following characteristics and specifications. (1) The amount of inversion polarization (switching charge) is large. This depends on the structure of the device, the set voltage value when sensing, the stability of the polarization value, etc., but generally 10 μC / cm ² More is needed. (2) The relative dielectric constant is small. The specific switching current value is small with respect to the switching current, and the S / N ratio can be suppressed. (3) The decrease (fatigue property) of the polarization value due to the rewriting cycle is small. In terms of fatigue characteristics, the ferroelectric material itself can be changed, or the electrode material can be oxide-based. ¹² More than once characteristics have been obtained. (4) The polarization reversal speed is fast. It has been shown that the switching characteristics are mainly influenced not by the net domain inversion speed but by electrode wiring resistance, stray capacitance, etc. due to the downsizing of the capacitor.
[0006]
(5) Leakage current is 10 ^-6 A / cm ² The following. Compared with a DRAM that uses the presence or absence of charge accumulated in a capacitor, a Ferroelectric RAM uses a remanent polarization value, so that a reference leakage current value is higher than that of a DRAM, and there is no problem. (6) The data retention characteristic is 10 years or more. The ferroelectric material actually used is PZT (Pb (ZrT _x Ti _1-x O _Three ) Thin film, SBT (SrBi ₂ Ta ₂ O ₉ ) Thin film. The former PZT has a crystallization temperature of about 600 ° C., a large polarization value and a residual polarization value of 20 μC / cm. ² Degree, coercive electric field is relatively small, and polarization reversal is possible at low voltage, in addition to crystallization temperature by Zr / Ti composition ratio, grain size, grain shape and other structural characteristics, polarization amount, coercive electric field, Pb called an A-site element is an element such as Sr, Ba, Ca, La and Zr called a B-site element because of the controllability of ferroelectric properties such as fatigue characteristics and leakage current, and the element tolerance of the pebrotite structure. , Ti can be substituted with elements such as Nb, W, Mg, Co, Fe, Ni, and Mn, and this has an advantage that it greatly affects the crystal structure, structural characteristics, and ferroelectric characteristics. .
[0007]
Originally, PZT is applied to transducers such as actuators, ultrasonic transducers, ultrasonic motors, hydrophones, piezoelectric transformers, passive components such as multilayer ceramic capacitors, applications to sensors such as infrared sensors, and structural phase transition, Many studies have been conducted so far on domain behavior, piezoelectricity, pyroelectricity, basic properties as ferroelectrics, microscopic behavior, etc., abundant database for PZT material design, property improvement, structural and electrical property elucidation, etc. It can be said that it is one advantage. In addition, PZT has been studied from the early stage because of its excellent piezoelectric, pyroelectric and ferroelectric properties, and there are many research examples in which a film is formed by a technique such as sputtering or sol-gel. From these backgrounds, PZT is a material that was first put into practical use as a Ferroelectric RAM. The decrease in the amount of polarization accompanying the increase in the number of writings (fatigue characteristics), which is a drawback, is characterized by the fact that the fatigue characteristics themselves are accelerated by an electric field, so the recent operating voltage has been lowered, and the Pt electrode that was originally used IrO _x For example, fatigue characteristics have been improved by using oxide electrodes.
[0008]
On the other hand, the latter SBT is a material developed to improve the fatigue characteristics of PZT and to achieve low voltage driving of the film. SBT is a kind of Bi layered compound (Aurivirius Phase), which is a quasi-perovskite structure layer made of oxygen octahedron that is the origin of ferroelectricity. ₂ O ₂ It has a crystal structure sandwiched between layers. With this structure, the main polarization axis is in a plane perpendicular to the c-axis, and there is no polarization in the c-axis direction or a small value, if any. The polarization is expressed by the oxygen octahedron in the pseudo-perovskite structure. Until now, there has been little research on ceramics due to its strong anisotropy. However, since MOD (Metalorganic Decomposition) method enabled thin film formation, it was confirmed that the formed polycrystalline SBT film exhibits ferroelectricity, good fatigue characteristics, and low voltage is possible. Further development is being accelerated. The fatigue of the PZT film is mainly caused by oxygen vacancies formed at the Pt electrode interface. One of the reasons for the generation of oxygen vacancies is the volatility and the ease of diffusion of the Pb element. Since Pb is a part of the perovskite structure, when oxygen depletion is formed, it forms dipoles with nearby cations and causes a decrease in switching charge. SBT has little influence on the direct perovskite structure because oxygen depletion itself that compensates for charges is formed in the Bi oxide layer even when Bi as a volatile element disappears. It is also effective not to have Ti whose valence is easy to change. SBT has a smaller amount of polarization than PZT, but it is also possible to increase the amount of polarization by substituting part of Ta with Nb. Recently, a device in which SBT is integrated as a capacitor has also been prototyped. SBT is also formed by a sol-gel method, a sputtering method, a laser ablation method or the like in addition to the MOD method.
[0009]
The PZT film is also formed by the MOD method, laser ablation method, ion beam sputtering method, thermal CVD method, MOCVD method, laser CVD method, etc., but the Ferroelectric RAM products are mainly sol-gel method and sputtering method. In the sputtering method, a high temperature of about 500 ° C. or higher is necessary to form a perovskite PZT film crystallized directly on the substrate. However, the vapor pressure of the low melting point element Pb is high and the sputtering rate is high. For this reason, it is easily evaporated and resputtered from the substrate at a high temperature. When the crystallization temperature is 500 ° C. or higher, Pb hardly reaches the substrate and the composition control is difficult. Usually, a Pb or PbO target is prepared separately and sputtered at the same time to supply an excess amount of Pb. However, it is difficult to form a film by uniformly controlling the composition on a substrate having a large area. Since the influence of Pb evaporation and resputtering is small at room temperature, a PZT film having a composition close to the target can be formed relatively easily. However, even at room temperature, the substrate and the shield part are likely to become high temperature due to the momentum of ions from the plasma, sputtered particles, etc., and it is necessary to pay attention to the effects of evaporation and resputtering. The composition changes because the impact of Ar ions varies depending on the potential of each part.
[0010]
A process for forming a ferroelectric film used for an electronic component will be described with reference to an example of a Ferroelectric RAM using a PZT ferroelectric film. An insulating film is formed on a silicon semiconductor substrate that has undergone a process for forming a transistor, and a Pt electrode having a thickness of 150 nm is formed as a base electrode by DC magnetron sputtering. Since Pt does not have good adhesion to the oxide film, Ti (20 nm) is formed as a bonding layer by continuous sputtering before forming Pt. Next, a PZT film is formed on the base electrode by RF magnetron sputtering. For the above reasons, the film is formed at room temperature without raising the substrate temperature. Sputtering is performed on a 12-inch ceramic PZT target at 1.0 to 1.5 kW. The sputtering gas was Ar and the film was formed in a pressure range of 0.5 to 2.0 Pa. A PZT amorphous film having a thickness of 250 to 300 nm can be obtained in a sputtering time of about 5 minutes. Before the PZT film formation, it is performed under the sputtering conditions for forming the pre-sputtering for about 1 hour. The amorphous PZT film is crystallized into a perovskite phase by an RTA (Rapid Thermal Anneal) process. Crystallization is possible in a few seconds at a temperature of 600 ° C. or higher. Crystallization is possible even in a tubular furnace or the like, but RTA has a smaller thermal budget and can suppress diffusion and reaction between the base electrode, the electrode and the PZT film, and is suitable for smoothing the interface. In addition, the PZT crystallization includes a non-ferroelectric phase pyrochlore phase as a different phase, and this phase is easily formed when the temperature rise rate of crystallization is reduced or when the Zr / Ti ratio is large. When the pyrochlore phase is formed as the second phase, not only the amount of polarization becomes small, but also the reliability of the PZT film may be affected.
Regarding the crystallized PZT film, a Pt film as an upper electrode is further formed by DC magnetron sputtering to form a capacitor structure. The capacitor pattern is etched by using an RIE (Reactive Ion Etching) apparatus in Ar and carbon fluoride gas to form a fine pattern. In order to improve the adhesion with the electrode, annealing is performed at 600 ° C. for 1 hour in oxygen. The PZT film thus formed is made of Pb _1.15-1.20 La _0.05 (Zr _0.4 Ti _0.6 ) O _Three The amount of Pb is changed within a range of 10% or less by changing the sputtering power and gas pressure during sputtering. The characteristics vary depending on the amount of Pb. The electrical characteristics of the formed PZT film having a columnar structure with a diameter of 100 to 300 nm include large leakage current due to changes in the composition and microstructure of the PZT film, poor fatigue characteristics, many with a small amount of polarization, large coercive electric field, etc. Problems also arise. When the unevenness on the surface of the PZT film is large, the unevenness on the processed surface becomes large during RIE. In RIE of PZT and Pt films, the physical etching effect is large due to ions, so that the unevenness of the film surface greatly affects the shape after etching.
[0011]
On the other hand, in a PZT film forming process formed by a solution method (CSD method) such as a sol-gel method or a MOD method, Pb, Ti, First, a raw material of a PZT film constituent element such as Zr is selected. In many cases, lead acetate trihydrate is used for Pb, zirconium tetrapropoxide is used for Zr, and titanium tetraisopropoxide is used for Ti. A solution of about 0.2M is first prepared using 2 methoxyethanol as a solvent. To do. This solution can be stored for a long time by sufficiently removing moisture. Generally, the water component of lead acetate hydrate is removed. At the time of film formation, water is added to this solution to cause a condensation polymerization reaction, but the cross-linked state of MOM is changed by dehydration reaction and dealcoholization reaction. The crosslinking state changes depending on the amount of water added at this time, the reaction time (retention time), pH, temperature, concentration, and the like. Since different amorphous states are formed as in the case of sputtering, the orientation, crystal grain properties, ferroelectric characteristics, leakage current, fatigue characteristics, etc. change after crystallization into a PZT perovskite structure. The same applies to the MOD method. Using Pb, Zr, Ti 2-ethylhexanoic acid or the like, an organic solvent xylene is used to prepare a PZT MOD solution. In the case of the MOD method, the hydrolysis reaction does not occur, and it is applied on the semiconductor substrate in that state (mixed state). After forming the film on the semiconductor substrate, drying and solvent removal are performed at a low temperature of about 250 ° C. to form an amorphous PZT film. In the MOD method, since the raw material has a structure containing a large amount of C, H, and O, the shrinkage of the film during crystallization is large, and in order to form a thick film of several hundreds of nanometers, the coating and crystallization processes are repeated. For crystallization, RTA is often used in the same manner as sputtering. A perovskite single phase is obtained by heat treatment at 750 ° C. for about 5 minutes. A PZT film using such a solution method has a crystal grain as small as 100 to several hundred nm, and often has a granular structure that does not show a columnar structure like a film formed by sputtering.
On the other hand, when a PZT film, an SBT film, or the like is formed by the MOCVD method, a film having good step coverage for forming a three-dimensional capacitor can be obtained by optimizing the conditions. However, there are many difficulties in the MOCVD technology of these ferroelectrics and dielectric materials. For example, it is difficult to control the film composition. Since Bi, Sr, Ba, etc., which are elements constituting the composite oxide, do not have a source material with a high vapor pressure, it is necessary to adopt a method using liquid supply. In addition, it is difficult to set optimum film forming conditions because the characteristics of the source of each element are different. There are situations where the amount of raw material supplied and the film composition are not necessarily proportional. Also, the difficulty increases because the source must be further selected when adding additives. In a process for obtaining a film crystallized in-situ, the characteristics of the film formed thereon vary depending on the state and composition of the surface (electrode surface) of the semiconductor substrate.
[0012]
[Problems to be solved by the invention]
In recent years, a COP (Capacitor On Plug) structure has been considered in order to fabricate a high-density ferroelectric memory using the film forming method described above. This is because the plug structure made of W or Si connected from the active area of the transistor is directly under the capacitor, and the cell size can be reduced. In the case of a planar capacitor, the above-described sputtering method, coating method, and MOCVD method can be used. When a three-dimensional capacitor structure is used, the MOCVD method or the like may be used. However, in this structure, the surface of the plug material immediately below is oxidized during the heat treatment to recover damage such as RIE processing when the capacitor ferroelectric film is crystallized or when the capacitor is integrated, and insulation film CVD. There is a problem that the resistance becomes high and peeling occurs when it is severe. In order to avoid this, formation of barrier layers such as TiAlN, TiN, TaSiN, IrO ₂ , Ir, RuO ₂ An electrode material such as Ru has been tried. Attempts have also been made to form a three-dimensional capacitor as described above. In film formation by MOCVD, a method of forming a film at a low temperature with good composition controllability and step coverage and crystallizing the dielectric film and the ferroelectric film in a subsequent heat treatment is performed. In addition, a capacitor manufacturing process using a damascene process has been proposed for the purpose of reducing RIE damage of the capacitor. In the process using CMP, a heat treatment is performed in a state where an oxide film, a dielectric film, and a ferroelectric film are in contact with each other. Because there is a thing to do, the reaction there is a problem. For example, PZT and SiO ₂ There is a problem that lead glass is formed by heat and the contact portion is remarkably deteriorated.
[0013]
On the other hand, a one-transistor type ferroelectric memory for further increasing the density of the Ferroelectric RAM is being developed. In the old days Bi directly on the gate of the transistor _Four Ti _Three O ₁₂ Researches and developments have been made on the formation of ferroelectrics such as that an oxide interface layer is formed at the interface with Si, that only specific materials can be crystallized, and interface reactions can be controlled. There were many obstruction factors such as inability to do so, and there were many defects at the interface, which could not be realized in terms of characteristics. Also, in the case of materials such as PZT, SiO ₂ It is difficult to crystallize above. In this case, if a crystallization heat treatment method such as RTA is adopted, crystallization is likely to proceed from the substrate side. ₂ This is because a deteriorated interface is formed by the reaction of and the Pb is consumed in the coil, resulting in a composition shift, and thus PZT does not crystallize thereon. It is possible to reduce the crystallization temperature by increasing the amount of Ti in PZT and promote crystallization from the upper part of the film or inside the film, but in this case, it is difficult to control the crystallization. In addition, the reaction with the substrate is unavoidable, and it is not satisfactory for producing a 1Tr type Ferroelectric RAM. The same applies to the case where a high dielectric constant film is used as the gate insulating film. ZrO ₂ , HfO ₂ Other ZrSiO _Three When a silicate film such as is used as a gate film, it is important to inhibit defect formation at the interface with Si. Also in this case, interfacial interdiffusion and reaction are caused by the crystallization process at a high temperature, and interface deterioration occurs.
[0014]
Conventionally, in the process of crystallizing an amorphous film on a silicon wafer, it is difficult to selectively crystallize using an RTA or a furnace. For example, when a film is formed and crystallized over a wide area like a capacitor film of a DRAM, a dielectric film is present not only on the electrode film but also on the insulating film. The part will also be exposed to heat. A reaction between the dielectric film and the insulating film may occur, which is not preferable for forming a device. Further, when there is a portion that is desired to be crystallized and a portion that is not desired to be crystallized on the same electrode, it is difficult with the conventional heating method.
Further, development of SOC (System On Chip) that integrates a memory function and a logic function on one chip is in progress. In order to fabricate the memory and logic in a common process, the consistency of each process is required. In the case of mixed mounting of Ferroelectric RAM and logic, it is possible by adding a capacitor process to the normal logic fabrication process. However, the capacitor for Ferroelectric RAM is easily damaged by the subsequent processing and insulating film formation process. A process for forming capacitors on multilayer wiring has been proposed because the material used is a new Si process and there is a problem of cross contamination, and it is difficult to adopt the low damage process unique to Ferroelectric RAM. Yes. In this case, since the multilayer wiring such as Al or Cu or the low dielectric constant film exists in the base, it is necessary to lower the capacitor formation temperature to about 400 ° C. However, it is difficult to produce a capacitor having good ferroelectric characteristics at such a low temperature, and it is difficult to achieve this structure.
Furthermore, the ferroelectric film represented by PZT and SBT used for Ferroelectric RAM is a new material for the Si process, which causes a problem of cross contamination. When the dielectric and ferroelectric films are formed by crystallization, as described above, SiO ₂ It is difficult to etch the beveled portion of the silicon wafer, which causes cross contamination and causes reaction.
The present invention has been made under such circumstances, and provides a semiconductor device having a structure in which a dielectric film and a ferroelectric film are crystallized regardless of the state of the base, and a method for manufacturing the semiconductor device.
[0015]
[Means for Solving the Problems]
The present invention is characterized in that in a semiconductor device including a capacitor using a ferroelectric film, a step of crystallizing the ferroelectric film using a flash lamp is used. In addition, using a flash lamp, SiO2 such as a gate oxide film ₂ A one-transistor type semiconductor memory is formed by crystallizing a ferroelectric film such as a PZT film on an insulating film or silicon while suppressing an interface reaction. In the present invention, it is also possible to crystallize only a portion irradiated with light by using a mask when using a flash lamp. As the mask material, a metal mask, a glass mask, or a metal film formed on amorphous silicon on a semiconductor substrate can be used. The present invention relates to flash lamp irradiation conditions (input power, pulse time, maximum current value) when a ferroelectric film is crystallized using a flash lamp in a semiconductor memory device having a capacitor using a ferroelectric film. In other words, the semiconductor device of the present invention has a semiconductor substrate, a connection plug embedded in a first insulating film formed on the semiconductor substrate, and the connection. A lower electrode electrically connected to the plug, a ferroelectric film formed on the lower electrode and crystallized, and an upper electrode formed on the ferroelectric film; and the capacitor A second insulating film made of a silicon oxide film formed on the first insulating film so as to cover the first insulating film, and a contact between the first insulating film and the ferroelectric film A mixed region of a cation element and silicon contained in the ferroelectric film formed in a portion is 30 nm or less, and the first insulating film in which the connection plug is embedded is formed on the semiconductor substrate. A metal wiring mainly composed of aluminum or a metal wiring mainly composed of copper, which is electrically connected to the formed semiconductor element, may be formed. A barrier layer is formed between the electrodes, and the total thickness of the lower electrode and the barrier layer may be 50 nm or more and 150 nm or less, more preferably 50 nm to 100 nm. It may be made of lead zirconate titanate.
[0016]
The method for manufacturing a semiconductor device according to the present invention is characterized by comprising a step of crystallizing the ferroelectric film by heating it using a flash lamp.
That is, the semiconductor device manufacturing method of the present invention includes a semiconductor substrate, a connection plug embedded in a first insulating film formed on the semiconductor substrate, a lower electrode electrically connected to the connection plug, A capacitor formed on the lower electrode and crystallized ferroelectric film and an upper electrode formed on the ferroelectric film, and the first insulation so as to cover the capacitor In a method of manufacturing a semiconductor device comprising a second insulating film made of a silicon oxide film formed on a film, the ferroelectric film is a flash lamp while the semiconductor substrate is kept at 350-400 ° C. It is characterized by being heated and crystallized. The ferroelectric film may be made of lead zirconate titanate. The flash lamp irradiation performed to crystallize the ferroelectric film may be performed according to the conditions of the following formulas (1) and (2).
E ≧ − (T / 10) +55 (1)
I = α · E / τ> 1500 (2)
E (J / cm ² ) Is the output of the Xe flash lamp (calculated from the amount of energy stored in the capacitor calculated from the total amount of charge stored in the capacitor as radiation efficiency 0.4, reflection efficiency 0.5, and irradiation area as lamp layout area) Where I (A) represents the flash lamp maximum current value, τ (msec) represents the pulse width (defined as the half width of the pulse current waveform) (irradiation time), and T (° C.) represents the assist temperature ( Represents the temperature of the semiconductor substrate during crystallization, and α is 70.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment will be described with reference to FIGS.
In this embodiment, a ferroelectric memory (Ferroelectric RAM) using a PZT film will be described. FIG. 1 is a sectional view of a silicon semiconductor substrate on which a capacitor using a PZT film as a dielectric film is formed, and FIG. 2 is a process flow diagram for manufacturing a semiconductor device. First, transistors Tr1 and Tr2 are formed in the n well and p well of the silicon semiconductor substrate 1 by a normal process to form a CMOS structure ((1)). Next, the transistor region is covered with an insulating film 2 made of a material such as PSG (Phospho-Silicate Glass) or BPSG (Born-doped Phospho Silicate Glass) by CVD, and the surface is flattened using CMP (Chemical Mechanical Polishing). ((2)). A silicon nitride film (SiN) 3 is formed thereon by CVD (3), and this is used as a base substrate. Here, in order to connect the capacitor and the active area (source and drain) 11 of the transistor using a plug made of tungsten (W), polycrystalline silicon, or the like, a contact hole in which the plug 4 is embedded is formed in advance. The plug material may be TiN embedded by CVD (4). In this embodiment, the plug is formed by using both blanket CVD and CMP. Next, the barrier layer 5 is formed for the purpose of preventing the surface of the plug 4 from being oxidized in the ferroelectric formation process or the subsequent annealing process in oxygen for securing the capacitor characteristics ((5)). TiAlN (Ti / Al = 0.9 / 0.1 (molar ratio)) is used for the barrier layer 5. The thickness is approximately 50 nm. It is not necessary to form a barrier layer on the entire surface under the lower electrode of the capacitor. The barrier layer may be formed only on the plug with the plug recessed, or may be formed when the lower electrode is formed on the entire surface under the lower electrode. . Depending on which one you choose, the overall process will be slightly different. In this embodiment, the barrier layer 5 is formed on the connection surface with the plug 4 by using a DC magnetron sputtering method. On top of this, Ru of the lower electrode 6 is formed by sputtering ((6)). When Ru is used as an electrode for a PZT capacitor, RuO is present at the interface. ₂ Thus, the fatigue properties of PZT (the phenomenon of deterioration in the amount of polarization when polarization inversion is repeated) are improved. Ru is the conductive oxide RuO. ₂ There are features such as formation of metal, good dry etching with a gas containing oxygen, and low material cost compared to noble metals such as Pt and Ir. Pt, Ir, IrO depending on the specification ₂ It is also possible to use electrodes such as.
[0018]
Next, after forming Ru with a thickness of about 50 nm, a PZT film 7 is formed by sputtering (7). In this case, an RF magnetron sputtering method is employed. Here, a PZT ceramic target in which the amount of Pb is increased by about 10 mol% is used. The composition ratio of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _0.6 O _Three It is. A PZT ceramic target is a ceramic sintered body having a theoretical density of 98% because the higher the density, the higher the sputtering rate and the better the environmental resistance against moisture and the like. At the time of sputtering, since there is a substrate temperature rise due to plasma and bombardment due to flying particles, evaporation of Pb from the silicon semiconductor substrate 1 and resputtering easily occur, and loss of the amount of Pb in the film tends to occur. Excess Pb in the target is added to compensate for it. Since elements such as Zr, Ti, and La are incorporated into the film in substantially the same amount as the target composition, elements having a desired composition ratio may be used. If the electrical characteristics are unstable due to the composition of the PZT film 7 or the like, a seed layer is formed above or below the amorphous PZT film 7. For example, in order to improve the structural and electrical characteristics of the PZT film 7 to be crystallized, a sputtering method in which oxygen is introduced is used. A PZT film formed by sputtering in an atmosphere into which Ar is introduced and a PZT seed layer formed by sputtering in Ar to which oxygen is added are used. As sputtering conditions, the distance between target substrates is 60 nm, and a 12-inch ceramic PZT target is sputtered at 1.0 to 1.5 kW using a rotary magnet. A film is formed for 15 to 30 seconds under the condition that the gas pressure is 0.5 to 2.0 Pa and 20% of oxygen is introduced into Ar, thereby forming a PZT amorphous seed layer having a thickness of about 2 to 5 nm. An amorphous PZT film 7 is formed on the underlying substrate Ru by RF magnetron sputtering using only Ar gas and a gas pressure of 0.5 to 2.0 Pa and a power of 1.0 to 1.5 kW for about 5 minutes. The film thickness is 100 to 150 nm. Instead of the PZT film, a thin Ti film, Zr film, Nb film, Ta film or the like having a thickness of about 2 to 5 nm may be used for the seed layer.
[0019]
Before the PZT film is formed, pre-sputtering for about 1 hour is performed under the same sputtering conditions in order to keep the target surface state, temperature, and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by this pre-sputtering. The PZT film 7 is crystallized by using a flash lamp in a structure in which amorphous PZT is formed on the Ru electrode formed on the plug through the barrier layer (8).
The flash lamp discharges Xe gas sealed for a short time of about 1 msec or less. For the purpose of promoting crystallization of the PZT film, the substrate temperature is previously maintained at 350 to 450 ° C. by a halogen lamp prepared under the silicon wafer. The emission energy of the Xe lamp is 25 J / cm ² It is. This energy is obtained from the amount of stored charge, but in fact it is considered that less than half of the energy contributes to the crystallization of the film. In this embodiment, the diffusion of light energy to the outside is prevented by providing a reflector on the side opposite to the lamp irradiation. The atmosphere is in an oxygen stream. By irradiating the above energy for about 1 msec under such conditions, the PZT film 7 is crystallized. When the crystal structure of the obtained film was examined by X-ray diffraction, very strong reflection from the (100) plane was obtained in the perovskite phase. According to the observation result of the fine structure, PZT particles having a diameter of 0.5 μm or less are formed on Ru.
[0020]
Next, a Ru film as the upper electrode 8 is formed on the crystallized PZT film 7 by DC magnetron sputtering to form a capacitor structure (9). The upper electrode pattern is formed by etching the Ru film formed on the entire surface of the semiconductor substrate 1 in a mixed gas of oxygen and chlorine using RIE. In order to improve the adhesion to the upper electrode 8 and the crystal matching, an annealing process is performed at 350 ° C. in nitrogen for 30 seconds to obtain ferroelectric characteristics. As a result of investigating the ferroelectricity with the hysteresis characteristic of charge amount Q-applied voltage V, it is about 30 μC / cm with a polarization amount 2 Pr (residual polarization × 2) when 2.5 V is applied. ² It was found that the PZT film had the same amount of polarization and coercive electric field on the entire surface of an 8-inch (about 20.32 cm) silicon wafer. The coercive voltage was as low as about 0.6V. When the fatigue characteristics of this sample were evaluated, the fatigue characteristics were evaluated with an array corresponding to an area of 50 μm × 50 μm. ¹² There is no change in the amount of polarization until the cycle, and the leakage current is 10 when 3V is applied ^-8 A / cm ² The order was low. The contact from the upper electrode 8 of the capacitor uses a normal LSI manufacturing process. That is, an insulating film 9 made of a silicon oxide film or the like is formed on the semiconductor substrate 1 to cover the capacitor and the SiN film 3. The surface of the insulating film 9 is flattened to form a contact hole from the surface to the upper electrode surface. Then, a plug 10 such as tungsten (W) is embedded therein, and the upper electrode 8 and the metal wiring 12 formed thereon are electrically connected. The metal wiring 12 such as Al or Cu is formed on the planarized surface of the insulating film 9. Next, an insulating film 13 made of a silicon oxide film or the like is formed on the semiconductor substrate 1 to cover the metal wiring 12 and the insulating film 9. Thereafter, the ferroelectric film is formed by drawing the wiring from the capacitor by repeating the insulating film, the RIE, and the wiring film forming process.
[0021]
As in this embodiment, in the crystallization process using the flash lamp, oxygen does not diffuse and react in the barrier layer portion that is the connection portion with the W plug, and therefore the plug is not oxidized and has stable electrical characteristics. A semiconductor device is obtained.
In the crystallization process, the oxidation of the plug made of tungsten or polysilicon is prevented by the barrier property that prevents the oxygen movement of the barrier layer 5 and the lower electrode 6 interposed between the PZT film 7 and the plug 4. It is. TiN, TiAlN, TiSiN, etc. are used for the barrier layer, and Ru, RuO are used for the lower electrode. ₂ , Ir, IrO ₂ These are materials having high barrier properties against oxygen. In order to maintain this barrier property effectively, the total thickness of the barrier layer and the lower electrode needs to be at least 50 nm, and the upper limit is preferably 100 nm or 150 nm. If the thickness is too large, the workability is deteriorated, and the capacitor is usually formed in a trapezoidal shape on the semiconductor substrate. Therefore, the size cannot be reduced, and the semiconductor device is not miniaturized.
[0022]
Next, a second embodiment will be described with reference to FIGS.
In this embodiment, a Ferroelectric RAM embedded logic in which a ferroelectric capacitor using a PZT thin film is formed on a multilayer wiring will be described. FIG. 3 is a cross-sectional view showing the structure of a capacitor using a PZT film. First, transistors Tr1 and Tr2 are formed on the p-type silicon semiconductor substrate 20 by a normal process to form a MOS structure. Here, cobalt (Co) silicide 22 is formed in the active area (source, drain) 21 of the capacitor and the transistor, and this is connected to the connection tungsten (W) plug 23. The connection with the W plug 23 uses a Ti / TiN laminated film 24, and the W plug 23 is formed by blanket CVD. A multilayer interlayer insulating film 26 (26a to 26e) is formed between the capacitor and the transistor, and a multilayer wiring 25 (25a to 25d) such as aluminum (Al) is formed on each interlayer insulating film. . The Al multilayer wiring 25 can be formed using a single damascene process or a daily damascene process. It is also possible to form by a multilayer wiring process in which a Cu wiring and a low dielectric constant film are combined.
A ferroelectric capacitor is formed on the interlayer insulating film 26 on which such multilayer wiring is formed.
[0023]
First, the Ir lower electrode 27 is formed by sputtering. When Ir is used as an electrode for a PZT capacitor, IrO ₂ As a result, the fatigue characteristics of PZT (the phenomenon of deterioration in the amount of polarization when polarization inversion is repeated) are improved. Ir is the conductive oxide IrO. ₂ There are features such as formation of, forming less interdiffusion due to reaction with PZT, and being chemically stable. Pt, Ru, RuO ₂ , IrO ₂ It is also possible to use electrodes such as. Between the lower electrode 27 and the W plug 23 electrically connected, for example, a barrier layer 32 such as Ti / TiN is interposed. After forming an Ir film having a thickness of 100 nm as the lower electrode 27, an amorphous PZT film 28 is formed so as to cover the lower electrode 27 by sputtering. Here, an RF magnetron sputtering method without heating the substrate is employed. In carrying out this method, a PZT ceramic target having a Pb amount increased by about 10% is used. The composition of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _0.6 O _Three It is. As the PZT ceramic target, a ceramic sintered body having a theoretical density of 98% is used because a high density target has a high sputtering rate and good environmental resistance against moisture and the like. At the time of sputtering, since there is a substrate temperature rise due to plasma and bombardment due to flying particles, Pb evaporation and resputtering from the silicon semiconductor substrate occurs, and the loss of Pb amount in the film tends to occur. Excess Pb in the target is added to compensate for the loss. Since elements such as Zr, Ti, and La are incorporated into the film in substantially the same amount as the target composition, elements having a desired composition ratio may be used. When the electrical characteristics are unstable due to the composition of the PZT film, a seed layer can be formed on the amorphous PZT film. For example, in order to modify the structure and electrical characteristics of the PZT film to be crystallized, a sputtering method in which oxygen is introduced is used. First, sputtering is performed in an atmosphere into which Ar is introduced, and then a PZT seed layer is formed by sputtering in Ar to which oxygen is added. As the sputtering conditions, sputtering is performed on a 12-inch ceramic PZT target with a target-substrate distance of 60 mm and a rotary magnet at 1.0 to 1.5 kW. The gas pressure is 0.5 to 2.0 Pa, and the film is formed for 15 to 30 seconds under the condition that 20% of oxygen is introduced into Ar to form a PZT amorphous seed layer having a thickness of 2 to 5 nm. An amorphous PZT film using RF magnetron sputtering is formed on the underlying Ru by using only Ar gas and a gas pressure of 0.5 to 2.0 Pa and a power of 1.0 to 1.5 kW for about 5 minutes. The film thickness formed is 100 to 150 nm. For the seed layer, a thin Ti film, Zr film, Nb film, Ta film, etc. of about 2 to 5 nm can be used instead of the PZT film. Before the PZT film formation, pre-sputtering for about 1 hour was performed under the same sputtering conditions in order to make the state of the target surface, temperature, and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by this pre-sputtering.
[0024]
Next, the PZT film 28 is crystallized using a flash lamp on the Ir electrode 27 formed on the W plug 23 through the barrier layer 32 and the amorphous PZT film 28 is formed. The flash lamp discharges the Xe gas sealed in a short time of about 1 msec or less. The substrate temperature is maintained at 350 to 400 ° C. by a halogen lamp prepared under the silicon wafer for the purpose of promoting crystallization of the PZT film. The emission energy of the Xe lamp is 23 J / cm ² It is. This energy is obtained from the amount of stored charge, but since the distance between the lamp and the substrate is 20 mm, it is considered that the energy of less than half actually contributes to the crystallization of the film. A reflection plate may be provided on the side opposite to the lamp irradiation so as to prevent the diffusion of light energy to the outside. For lamp irradiation, about 5 pulses were applied at intervals of 2 seconds. The atmosphere is in an oxygen stream. The flash lamp is irradiated with the above-mentioned energy for a time of 0.8 msec, whereby the PZT film is crystallized. When the crystal structure of the obtained film was examined by X-ray diffraction, very strong reflection from the (100) plane of the perovskite phase was obtained. According to the observation result of the fine structure, PZT particles having a diameter of 0.5 μm or less are formed on Ir. Next, an Ir film that is the upper electrode 29 is formed on the PZT crystal film 28 by DC magnetron sputtering to produce a capacitor structure.
[0025]
The upper electrode 29 is obtained by etching an Ir film formed on the entire surface of the substrate in a mixed gas of oxygen and chlorine using RIE to form a fine pattern. In order to improve the adhesion with the upper electrode 29 and the crystal matching, annealing was performed at 350 ° C. in nitrogen for 30 seconds to obtain a capacitor C having ferroelectric characteristics. When the ferroelectricity was examined by the hysteresis characteristic of the charge amount Q and the applied voltage V, it was about 30 μC / cm at a polarization amount 2Pr (residual polarization × 2) when 2.5V was applied. ² It was found that a PZT film having the same amount of polarization and coercive electric field was obtained on the entire surface of the 8-inch silicon wafer. The coercive voltage was as low as about 0.6V. When the fatigue characteristics of this sample were evaluated, the fatigue characteristics were evaluated with an array corresponding to an area of 50 μm × 50 μm. ¹² There is no change in the amount of polarization until the cycle, and the leakage current is 10 when 3V is applied. ^-8 A / cm ² The order was low. The contact from the capacitor upper electrode 29 uses a normal LSI manufacturing process. That is, a contact hole is formed in the insulating film 30 such as a silicon oxide film covering the capacitor C, and a wiring film forming process is further performed to lead out the wiring 31 from the capacitor C. In the crystallization process using a flash lamp, the shape deterioration of the Al wiring, Cu wiring, and interlayer insulating film of the multilayer wiring under the capacitor was not observed.
FIG. 10 is a photograph cross-sectional view showing the Al wiring disposed under the capacitor after the crystallization process. As shown in the figure, after irradiation with the flash lamp, the insulating film (SiO 2 film) is disposed under the ferroelectric film (PZT film) and the lower electrode (Pt film). ₂ The Al wiring covered with) was not deformed.
[0026]
Next, a third embodiment will be described with reference to FIG.
In this example, SiO ₂ A 1Tr type Ferroelectric RAM in which a PZT thin film is formed on a gate oxide film will be described. FIG. 4 shows a cross-sectional view of a capacitor structure (MFIS: Metal-Ferroelectric-Insulater-Semiconductor) using a PZT film. First, as shown in FIG. 4A, a transistor having a source / drain region 32 is formed on a p-type silicon semiconductor substrate 40 by a normal process to form a MOS structure. Here, the gate oxide film 33 is made of ordinary SiO. ₂ Is used. An amorphous PZT film 34 is formed on the gate oxide film 33 by a coating method such as a sol-gel method or a sputtering method. In normal crystallization by RTA, the gate oxide film and the PZT film are mutually diffused to form traps in the film, and good characteristics cannot be obtained. Here, crystallization is performed by a flash lamp. When the PZT film 34 is formed by sputtering, the following process is used. Here, an RF magnetron sputtering method without heating the substrate is employed. And the PZT ceramic target which increased Pb amount about 10% is used. The composition of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _0.6 O _Three It is. Since a high-density PZT ceramic target has a high sputtering rate and good environmental resistance against moisture and the like, a ceramic sintered body having a theoretical density of 98% is used. At the time of sputtering, since the substrate temperature rises due to plasma and there is bombardment due to flying particles, evaporation of Pb from the silicon semiconductor substrate 40 and re-sputtering occur, and the loss of the amount of Pb in the film tends to occur. Excess Pb in the target is added to compensate for it. Since elements such as Zr, Ti, and La are incorporated into the film in almost the same amount as the target composition, elements having a desired composition ratio may be used. When the electrical characteristics are unstable due to the composition of the PZT film, a seed layer is formed on the amorphous PZT film. For example, in order to modify the structure and electrical characteristics of the PZT film to be crystallized, a sputtering method in which oxygen is introduced is used. First, sputter deposition is performed in an atmosphere into which Ar is introduced, and then a PZT seed layer is formed by sputtering in Ar to which oxygen is added.
[0027]
As the sputtering conditions, a target-substrate distance is 60 mm, a rotary magnet is used, and sputtering is performed on a 12-inch ceramic PZT target at 1.0 to 1.5 kW. A PZT amorphous seed layer having a thickness of about 2 to 5 nm is formed by forming a film for 15 to 30 seconds under a condition of gas pressure of 0.5 to 2.0 Pa and 20% oxygen introduced into Ar. On the underlying Ru, an amorphous PZT film is formed by RF magnetron sputtering for about 5 minutes at a gas pressure of 0.5 to 2.0 Pa and a power of 1.0 to 1.5 kW using only Ar gas. The film thickness is 100 to 150 nm. Instead of the PZT film, a thin Ti film, Zr film, Nb film, Ta film or the like having a film thickness of about 2 to 5 nm may be used for the seed layer. Before the PZT film formation, pre-sputtering for about 1 hour was performed under the same sputtering conditions in order to keep the target surface state, temperature, and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by this pre-sputtering. The flash lamp discharges the Xe gas sealed in a short time of about 1 msec or less. The substrate temperature is maintained at 350 to 400 ° C. by a halogen lamp prepared under the silicon wafer for the purpose of promoting crystallization of the PZT film. Xe lamp emission energy is 23 J / cm ² It is. This energy is obtained from the amount of stored charge, but in fact, it is considered that less than half of the energy contributes to the crystallization of the film. A reflection plate is provided on the side opposite to the lamp irradiation to prevent the diffusion of light energy to the outside. Irradiation was performed by applying about 2 pulses at intervals of 2 seconds. The atmosphere is in an oxygen stream. The flash lamp is irradiated with the above energy for a time of 1 msec, which causes the PZT film to crystallize. When the crystal structure of the obtained film was examined by X-ray diffraction, very strong reflection from the (100) plane of the perovskite phase was obtained. According to the observation results of the fine structure, PZT particles having a diameter of 0.5 μm or less are SiO 2 ₂ Formed on top.
[0028]
Next, a Pt film as the upper electrode 35 is formed on the crystallized PZT film 34 by DC magnetron sputtering to produce a capacitor structure. The upper electrode 34 is obtained by etching a Pt film deposited on the entire surface of the substrate using RIE in a mixed gas of Ar and chlorine to form a fine pattern. In order to improve the adhesion with the upper electrode and the crystal matching, an annealing process is performed at 450 ° C. in nitrogen for about 30 seconds to obtain a memory having ferroelectric characteristics. Thereafter, wiring (not shown) is formed with Al and W plugs by a normal LSI manufacturing process. When the ferroelectricity was examined by the hysteresis characteristic of the charge amount Q and the applied voltage V, a 2 V memory window was confirmed when 5 V was applied, and a PZT film having the same polarization amount and coercive electric field on the entire surface of an 8-inch silicon wafer. It turns out that. When the gate portion was observed, the PZT film and SiO ₂ Gate oxide film (SiO ₂ It was confirmed that a good perovskite structure was formed without causing interdiffusion even though the film thickness was as small as 20 nm or less. Therefore, it is not necessary to have a thickness exceeding 20 nm. For example, as the reaction layer with Pb becomes thicker, the unevenness becomes larger and the gate oxide film SiO ₂ Will break down.
[0029]
In this semiconductor memory, when a high positive voltage is applied to the gate, the ferroelectric is polarized and electrons are induced in the channel (FIG. 4B). On the other hand, when a negative high voltage is applied to the gate, the ferroelectric substance is oppositely polarized and a positive charge is induced in the channel (FIG. 4C). In this case, since electrons are movable charges, current flows in the state of FIG. 4B, and no current flows in the state of FIG. 4C. In this way, the semiconductor memory can operate.
In this method, not only the MFIS structure, but also an MFS structure in which a ferroelectric film is formed directly on a silicon semiconductor substrate, an SiOF on a silicon semiconductor substrate. ₂ , CaF ₂ , MgAl ₂ O _Four , Ce0 ₂ MFIS structure through insulating film such as SiO ₂ It is clear that the present invention can be applied to an MFMIS structure in which a ferroelectric film is formed on a metal film such as Pt formed on a gate oxide film. Further, the ferroelectric material is not limited to PZT, but SBT, SBTN, Bi. _Four Ti _Three O ₁₂ , STN, etc. are all included. The electrode material can also include Pt, Ir, Ru and oxides thereof, and conductive oxide films having a perovskite structure.
[0030]
Next, a fourth embodiment will be described with reference to FIGS. 5 to 7 and FIG.
In this embodiment, a ferroelectric memory using a three-dimensional capacitor and having a PZT thin film will be described. FIG. 5 is a cross-sectional view showing a structure of a three-dimensional capacitor using a PZT film. First, although not shown, a transistor is formed on the silicon semiconductor substrate 50 by a normal process to form a CMOS structure. An insulating film 41 such as PSG or BPSG is formed by CVD so as to cover the transistor region, and the surface thereof is planarized using CMP. A silicon nitride film (SiN) is formed thereon by CVD, and this is used as a base substrate. Here, in order to connect the lower electrode of the capacitor and the active area (source / drain region) of the transistor using the plug 42 made of W or polycrystalline silicon, a contact hole is formed in the insulating film 41 in advance. The plug material may be TiN embedded by CVD. The formation of the plug 42 uses both blanket CVD and CMP. First, the barrier layer 43 is formed on the surface of the plug 42 for the purpose of preventing the plug surface from being oxidized in the annealing process in oxygen for forming the ferroelectric material or securing the capacitor characteristics thereafter. TiAlN (Ti / Al = 0.9 / 0.1 (molar ratio)) is used for the barrier layer 43. The thickness of the barrier layer 43 is approximately 50 nm. It is not necessary to form a barrier layer on the entire surface under the lower electrode, and the barrier layer may be formed only on the plug with the plug recessed, or may be formed when the lower electrode is formed on the entire surface under the lower electrode. . This makes the overall process slightly different. In this embodiment, the barrier layer 43 is formed on the connection surface with the plug 42 by DC magnetron sputtering. The barrier layer is separated into individual capacitor parts (if they are embedded on the plug, they are already separated), and further, SiO2 is deposited thereon by CVD using a material such as TEOS. ₂ An insulating film 48 is formed. Since the thickness of the oxide film 48 corresponds to the depth of the three-dimensional capacitor, the thickness is adjusted according to the capacitor size. The capacitance required for the capacitor is about 30 fC. Therefore, if a PZT film is used, the residual polarization amount is assumed to be 10 μC / cm. ² In this case, a 0.5 × 0.5 μm planar capacitor is 25 fC, so a capacitor having a smaller size needs to be three-dimensional. If the aspect ratio is 0.5, the area is approximately doubled on the side surface, so the capacity is tripled. In practice, however, the scaling effect of the thickness of the dielectric film is small, and the capacitor size is limited to that. Next, in order to form a concave capacitor in the insulating film 48, SiO 2 ₂ The insulating film 48 is etched by RIE to form a recess where the barrier layer 43 is exposed on the bottom surface. The etching gas used for RIE is CF _Four Use fluorocarbon gas.
[0031]
Next, the lower electrode 45 is formed by sputtering in the recess on which the barrier layer 43 is formed. At this time, it is more effective to use a method such as long throw sputtering in order to increase the step coverage. However, in the capacitor formed in this embodiment, the aspect ratio of the recesses is mainly about 1 or less, so that normal sputtering is also possible. Ru is used for the lower electrode 45. When Ru is used as an electrode for a PZT capacitor, RuO is present at the interface. ₂ As a result, the fatigue characteristics of PZT (the phenomenon of deterioration in the amount of polarization when polarization inversion is repeated) are improved. Ru is the conductive oxide RuO. ₂ There are features such as formation of metal, good dry etching with a gas containing oxygen, and low material cost compared to noble metals such as Pt and Ir. After the Ru film having a thickness of about 50 nm is formed, a resist is put in the recess for forming the capacitor, and the Ru film is processed by CMP to leave the lower electrode 45 only inside the recess. Thus, in order to prevent the upper electrode and the lower electrode from being short-circuited at the edge portion of the capacitor after the PZT film is formed, the edge portion of the Ru lower electrode 45 is processed to be below the CMP flat portion by etching using a resist. To do. Ru formed in a portion other than the capacitor is subjected to CMP using the underlying oxide film as a stopper. The Ru edge portion not covered with the resist is etched from the upper surface of the capacitor by dry or wet.
[0032]
Next, a PZT film 46 is formed on the processed upper portion of the lower electrode 45 by sputtering. For example, RF magnetron sputtering is used for the formation. Here, a PZT ceramic target having a Pb amount increased by about 10% is used. The composition of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _0.6 O _Three It is. As the PZT ceramic target, a ceramic sintered body having a theoretical density of 98% is used because a high-density one has a high sputtering rate and good environmental resistance against moisture and the like. During sputtering, the substrate temperature rises due to plasma and bombardment due to flying particles causes Pb evaporation and resputtering from the silicon semiconductor substrate, and the loss of the Pb amount in the film tends to occur. Excess Pb in the target is added to compensate for it. Since elements such as Zr, Ti, and La are incorporated into the film in almost the same amount as the target composition, elements having a desired composition ratio can be used. When the electrical characteristics are unstable due to the composition of the PZT film or the like, a seed layer is formed on the film, and a PZT film is formed thereon. As the sputtering conditions, a target-substrate distance is 60 mm, and a 12-inch ceramic PZT target is sputtered at 1.0 to 1.5 kW using a rotary magnet. The gas pressure is 0.5 to 2.0 Pa, and RF magnetron sputtering is performed with Ar for about 5 minutes. The film thickness is 100 to 150 nm. Before the PZT film is formed, pre-sputtering for about 1 hour is performed under the same sputtering conditions in order to keep the target surface state, temperature, and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by this pre-sputtering. The perovskite phase was crystallized in an oxygen stream using a Xe flash lamp. The flash lamp discharges the Xe gas sealed in a short time of about 1 msec or less. The substrate temperature is maintained at 350 to 400 ° C. by a halogen lamp prepared under the silicon wafer for the purpose of promoting crystallization of the PZT film. Xe lamp emission energy is 23 J / cm ² It is. This energy is obtained from the amount of stored charge, but in fact it is considered that less than half of the energy contributes to the crystallization of the film. A reflection plate is provided on the side opposite to the lamp irradiation to prevent the diffusion of light energy to the outside. The flash lamp is irradiated with the above-mentioned energy for a time of 1 msec, whereby the PZT film is crystallized. When the crystal structure of the obtained film was examined by X-ray diffraction, very strong reflection from the (100) plane of the perovskite phase was obtained. This microstructure is shown in the figure. According to the observation result of the microstructure, PZT particles having a diameter of 0.5 μm or less are formed. The coverage at the capacitor recess edge at this time was good as shown in FIG.
[0033]
Further, as shown in FIG. 6, PZT and SiO ₂ Even in the portion (A) in contact with the film, no remarkable deterioration of the shape due to mutual diffusion or reaction was observed. FIG. 6 is a cross-sectional view of a semiconductor substrate having a ferroelectric film. That is, generation of interface defects is prevented by crystallization by flash lamp processing. When the PZT film is not left on the entire surface of the wafer, the PZT film other than the capacitor is removed by CMP at this stage. Further, this step (CMP treatment of the PZT film) may be performed simultaneously with the CMP of the upper electrode after the formation of the upper electrode.
Next, a Ru film, which is the upper electrode 47, is formed on the PZT crystal film by DC magnetron sputtering to produce a capacitor structure. In order to form the upper electrode 47 by patterning the Ru film, only the capacitor part may be left using CMP, but etching is performed in a mixed gas of oxygen and chlorine using RIE to form a fine pattern. You may do it. In this case, the PZT capacitor body is not damaged because the upper electrode is processed at the peripheral portion of the PZT film. Thereafter, in order to improve the adhesion with the upper electrode and the crystal matching, annealing is performed in nitrogen at 500 ° C. for 30 seconds to obtain a ferroelectric having ferroelectric characteristics. When the ferroelectricity was examined by the hysteresis characteristic of the charge amount Q-the applied voltage V, the polarization amount was 2Pr (residual polarization × 2), and about 40 μC / cm. ² It was found that a PZT film having the same amount of polarization and coercive electric field was formed on the entire surface of the 8-inch silicon wafer. The coercive voltage was as low as about 1V. And the fatigue characteristic of this sample was evaluated. Fatigue properties were evaluated using an array corresponding to an area of 50 μm × 50 μm, and 1 × 10 ¹² There is no change in the amount of polarization until the cycle, and the leakage current is 10 when 5 V is applied. ^-8 A / cm ² The order was low.
[0034]
In this embodiment, a three-dimensional capacitor is formed by sputtering, but a method such as MOCVD or LSMCD may be employed in the case of a larger aspect ratio. In addition, it is possible to crystallize only a part of the wafer by using a mask material between the flash lamp and the silicon semiconductor substrate.
FIG. 7 is a cross-sectional view of a semiconductor substrate for explaining a state in which a ferroelectric film is partially crystallized from an amorphous state using a mask. Silicon oxide film (SiO2) on silicon semiconductor substrate ₂ (FIG. 7A) or an electrode film is formed, and an amorphous PZT film is formed thereon. If a mask is placed on it (see FIG. 7B) or placed in close contact with the amorphous PZT film (FIG. 7C), and the flash lamp is irradiated in this state as in this embodiment, the mask is not masked. Only part of the PZT film crystallizes.
If the PZT film is crystallized at the outer periphery of the wafer or the like, it is difficult to remove it by etching in the subsequent process, so that the problem of cross contamination tends to occur. For example, the problem can be solved by using a mask material that covers the wafer edge portion when the PZT film is crystallized (see FIG. 7B).
Further, when only a minute part is crystallized, a method of preparing a mask with higher accuracy and reducing the distance from the wafer, a method of reducing projection using a lens system, and the like can be considered. The latter can be used in combination with a normal exposure mask such as a Cr mask to further selectively crystallize a minute region, so that the ferroelectric film and the dielectric film can be selectively crystallized uniformly. become.
[0035]
As another application, flash lamp heating can be used for the gate insulating film itself. ZrO ₂ , HfO ₂ In order to increase the dielectric constant of these films, a method of partially crystallization can be achieved by the flash lamp heating used in the present invention.
That is, ZrSiO on a semiconductor substrate such as silicon _Three Silicate dielectrics such as SrTiO _Three Ya (BaSr) TiO _Three Perovskite dielectrics such as ZrO ₂ , HfO ₂ , Ta ₂ O _Five TiO ₂ A gate insulating film made of a high dielectric constant material such as a gate electrode is formed on the gate insulating film, and a light shielding mask is formed directly or on a portion of the gate insulating film other than the gate region where the gate electrode is formed. The gate insulating film is selectively crystallized by disposing a predetermined distance and irradiating the gate insulating film with a flash lamp through the light shielding mask.
Therefore, as in this embodiment, a light shielding mask is arranged on the peripheral bevel portion of the silicon wafer on which the ferroelectric film (PZT film) is formed up to the bevel portion, and in this state, the PZT film is irradiated with a flash lamp. The crystallization process is performed (FIG. 11). FIG. 11 is a plan view and a cross-sectional view of a silicon wafer on which a light shielding mask is arranged. The PZT film in the central part of the non-light-shielding part is crystallized by flash lamp irradiation, and the PZT film in the beveled part is in an amorphous state. Crystallized PZT films are soluble in hydrofluoric acid, but are difficult to etch with hydrochloric acid. However, since the amorphous PZT film can be easily etched with hydrochloric acid, it is not difficult to etch the silicon wafer bevel portion. When the ferroelectric film is crystallized in this way, SiO ₂ Etching treatment becomes easier when partial crystallization is performed using a mask, although the reaction proceeds and etching of the bevel portion of the silicon wafer, which causes cross contamination, becomes difficult.
[0036]
Next, a fifth embodiment will be described with reference to FIG. 8, FIG. 9, FIG. 12, and FIG.
In this embodiment, crystallization of a ferroelectric film will be described using a ferroelectric memory using a PZT thin film similar to that shown in FIG. FIG. 8 is a characteristic diagram showing the crystallization conditions of the ferroelectric film. The vertical axis represents the energy density (J / cm) applied to the semiconductor substrate by the flash lamp for crystallization. ² The horizontal axis represents the substrate temperature (assist temperature) (° C.) during crystallization. First, a transistor is formed on a silicon semiconductor substrate by a normal process to form a CMOS structure. An insulating film such as PSG or BPSG is formed in the transistor region by the CVD method, and the surface thereof is planarized by the CMP method. A silicon nitride film (SiN) is formed thereon by CVD, and this is used as a base substrate. Here, since the capacitor and the active area (source / drain region) of the transistor are connected using a plug made of tungsten (W) or polysilicon, the plug is formed in advance. For forming the plug, a blanket CVD method and CMP are used in combination. In the capacitor structure, first, Pt which is a lower electrode is formed. The Pt film is about 100 nm thick using DC magnetron sputtering. The lower electrode is made of Ru, Ir, RuO except for Pt. ₂ , IrO ₂ Alternatively, these stacked structures, and perovskite structure oxide conductors such as SRO, LSCO, and YBCO are also possible. When Ru is used as an electrode for a PZT capacitor, RuO is present at the interface. ₂ As a result, the fatigue characteristics of PZT (the phenomenon of deterioration in the amount of polarization when polarization inversion is repeated) are improved. Ru is the conductive oxide film RuO. ₂ There are characteristics such as good formation of oxygen and good dry etching including oxygen. An amorphous PZT film is formed on the lower electrode by RF magnetron sputtering. A PZT ceramic target with a Pb amount increased by about 10% is used.
[0037]
The composition of the target is Pb _1.10 La _0.05 Zr _0.4 Ti _0.6 O _Three It is. Since a high-density PZT ceramic target has a high sputtering rate and good environmental resistance against moisture and the like, a ceramic sintered body having a theoretical density of 98% is used. During sputtering, the substrate temperature rises due to plasma and bombardment due to flying particles causes Pb evaporation and resputtering from the silicon semiconductor substrate, and the loss of the Pb amount in the film tends to occur. Excess Pb in the target is added to compensate for the loss. Since elements such as Zr, Ti, and La are incorporated into the film in substantially the same amount as the target composition, elements having a desired composition ratio may be used. When the electrical characteristics are unstable due to the composition of the PZT film, a seed layer is formed on the amorphous PZT film. For example, in order to improve the structure and electrical characteristics of the PZT film to be crystallized, a sputtering method in which oxygen is introduced is used. First, sputter deposition is performed in an atmosphere into which Ar is introduced, and then a PZT seed layer is formed by sputtering in Ar to which oxygen is added. As the sputtering conditions, sputtering is performed on a 12-inch ceramic PZT target with a target-substrate distance of 60 mm and a rotary magnet at 1.0 to 1.5 kW. A PZT amorphous seed layer having a thickness of 2 to 5 nm is formed by forming a film for 15 to 30 seconds under a gas pressure of 0.5 to 2.0 Pa and introducing 20% oxygen into Ar. On the underlying Ru, an amorphous PZT film is formed by RF magnetron sputtering for about 5 minutes at a gas pressure of 0.5 to 2.0 Pa and a power of 1.0 to 1.5 kW using only Ar gas. The film thickness of the amorphous PZT film is 100 to 150 nm. Instead of the PZT film, a thin Ti film, Zr film, Nb film, Ta film or the like of about 2 to 5 nm may be used for the seed layer. Before the PZT film formation, pre-sputtering for about 1 hour is performed under the same sputtering conditions in order to make the target surface state, temperature, and chamber environment constant. The amount of Pb and the structure and electrical characteristics after crystallization are greatly changed by this pre-sputtering.
[0038]
The PZT film is crystallized using a flash lamp on the Ru electrode formed on the plug through the barrier layer and the amorphous PZT film is formed. The flash lamp discharges Xe gas sealed in a short time of about 1 msec or less. For the purpose of promoting crystallization of the PZT film, the substrate temperature is maintained at 350 to 450 ° C. by a halogen lamp prepared under the silicon wafer. Xe lamp emission energy is 25 J / cm ² It is. This energy is obtained from the amount of stored charge, but in fact it is considered that less than half of the energy contributes to the crystallization of the film.
FIG. 8 is a characteristic diagram showing the relationship between the substrate temperature and the crystallization energy of the flash lamp. The straight line Y shown in the figure defines the range of the crystallized region, the upper part of the straight line Y is the crystallized region, and the lower part is the non-crystallized region. The straight line Y is represented by Y = −0.1X + 5 (Y represents energy density and X represents assist temperature). The irradiation conditions of the flash lamp necessary for crystallization are expressed by the following formulas (1) and (2).
E ≧ − (T / 10) +55 (1)
I = α · E / τ> 1500 (2)
Where E (J / cm ² ) Is the output of the Xe flash lamp (calculated from the amount of accumulated energy in the capacitor as the radiation efficiency of 0.4 and reflection efficiency of 0.5, and the irradiation area as the lamp layout area). is there. I (A) is a lamp maximum current value. τ (msec) is a pulse width (defined as a half-value width of a pulse current waveform), that is, an irradiation time. T (° C.) is an assist temperature. n is the number of pulse applications. α is a constant and represents 70. When the lamp is irradiated under this crystallization condition, the ferroelectric film is crystallized.
[0039]
A reflection plate is provided on the side opposite to the lamp irradiation to prevent the diffusion of light energy to the outside. The atmosphere during crystallization is in an oxygen stream. The PZT film is crystallized by irradiating the above energy for about 1 msec. When the crystal structure of the obtained film was examined by X-ray diffraction, very strong reflection from the (100) plane of the perovskite phase was obtained. According to the observation result of the fine structure, PZT particles having a diameter of 0.5 μm or less are formed on the Pt lower electrode.
Next, a Ru film as an upper electrode is formed on the crystallized PZT film by DC magnetron sputtering to produce a capacitor structure. The upper electrode is formed into a fine pattern by etching the Ru film in a mixed gas of oxygen and chlorine using RIE. In order to improve the adhesion with the upper electrode and the crystal matching, an annealing treatment was performed at 400 ° C. in nitrogen for 30 seconds to obtain a ferroelectric film having ferroelectric characteristics.
FIG. 12 and FIG. 13 show characteristics obtained by optically measuring the state after the crystallization treatment of the 150 nm-thick PZT film formed on the TEOS film on the semiconductor substrate and the state without the crystallization treatment. In this figure, the horizontal axis represents 2θ. In FIG. 12, the semiconductor substrate is heated to 450 ° C. in advance. In this state, the characteristic line A shows the light irradiated to the PZT film by the flash lamp (Flash), and the characteristic line B is an example in which the flash lamp processing is not performed (No flash) as in the prior art. In this way, PZT having ferroelectric characteristics crystallized by the crystallization process is formed. FIG. 13 shows the effect of flash lamp irradiation when the semiconductor substrate is heated to 400.degree. The characteristic line A subjected to the lamp irradiation shows a crystallized PZT film (FIG. 13A), and the characteristic line B only for the conventional heat treatment does not show the crystallized PZT film (FIG. 13). (B)).
[0040]
Next, the heat processing apparatus used for this invention is demonstrated.
FIG. 9 is a schematic cross-sectional view of a heat treatment apparatus provided with a flash lamp. As shown in the figure, a rod-shaped lamp (halogen lamp) is disposed under the sample table on which the silicon wafer is placed, and is configured so that the wafer can be heated in advance. This heat treatment apparatus has a sample chamber 100 made of aluminum. Inside the sample chamber, a sample stage 102 on which a sample (silicon wafer) is placed, a gas inlet 103 for introducing a gas such as oxygen, and the like are exhausted. An exhaust port 104, an upper quartz window 105 for introducing light, a rod lamp 106 for preheating the sample, and a flash lamp 107 are provided. Sixteen rod lamps 106 of 3 kW tungsten halogen lamps are installed under the wafer 108 and heat the wafer 108 from below. On the other hand, the flash lamps 107 are similarly rod-shaped lamps, and 15 lamps are installed on the wafer 108 to heat the wafer 108 from above. Both lamps are connected to dedicated power sources 109 and 110, respectively. The lamp lighting timing, lighting time, and flash lamp lighting frequency are configured to be controlled by a microcomputer. It is not essential that the lamp 106 is a rod-shaped lamp, and a similar effect can be expected with a lamp of a type in which two external terminals are provided in one direction, which is called single-ended in the field of lamps.
[0041]
When the ferroelectricity was examined by the hysteresis characteristic of the charge amount Q and the applied voltage V, it was about 30 μC / cm at a polarization amount 2Pr (residual polarization × 2) when 2.5V was applied. ² It was found that the PZT film has the same amount of coercive electric field on the entire surface of the 8-inch silicon wafer. The coercive voltage was as low as about 0.6V. The fatigue characteristics of this sample were evaluated, and the fatigue characteristics were evaluated with an array corresponding to an area of 50 μm × 50 μm. ¹² There is no change in the amount of polarization until the cycle, and the leakage current is 10 when 3V is applied. ^-8 A / cm ² The order was low. The contact from the capacitor upper electrode uses a normal LSI manufacturing process. That is, the wiring is drawn out from the capacitor by repeating the insulating film, RIE, and wiring film forming process. In the crystallization process using the flash lamp, the barrier layer portion, which is the connection portion with the W plug, did not diffuse and reacted, and the plug was not oxidized.
[0042]
【The invention's effect】
As described above, according to the present invention, in a semiconductor memory device including a capacitor using a ferroelectric film, the ferroelectric film is crystallized by using a flash lamp, regardless of the structure under the capacitor. A film can be made. In the present invention, it is possible to reduce the thermal load on the base portion of the capacitor.
Further, the present invention is suitable for a 1Tr type memory in which a ferroelectric film such as PZT is crystallized on an insulating film (silicon oxide) such as a gate oxide film or a silicon semiconductor substrate while suppressing an interface reaction. . Also, ZrO formed as a gate oxide film ₂ , HfO ₂ The silicate film can be heat-treated for the purpose of increasing the dielectric constant and improving the crystallinity. Until now, diffusion and reaction with silicon has been a problem, but a good interface can be formed by flash lamp heating. Further, in a COP structure in which a capacitor is formed on a plug of tungsten, polysilicon, etc. having low heat resistance and oxidation resistance, the heat load applied to the plug portion is reduced, and the capacitor is suppressed while suppressing oxidation and increasing contact resistance. This ferroelectric film can be crystallized. This process enables a very small cell size and high integration of the semiconductor memory. Further, partial crystallization can be easily performed by using a mask material when using a flash lamp. Further, the present invention provides a three-dimensional capacitor structure in which a part of a dielectric film extends from a lower electrode film in a laminated structure of an electrode film / dielectric film / electrode film, and is insulated from the extended dielectric film. Reaction between the membrane is suppressed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a silicon semiconductor substrate on which a capacitor using a PZT film of the present invention as a dielectric film is formed.
FIG. 2 is a process flow diagram for manufacturing the semiconductor device of the present invention.
FIG. 3 is a cross-sectional view showing the structure of a capacitor using the PZT film of the present invention.
FIG. 4 is a cross-sectional view of a capacitor structure (MFIS) using the PZT film of the present invention.
FIG. 5 is a cross-sectional view showing the structure of a three-dimensional capacitor using the PZT film of the present invention.
FIG. 6 is a cross-sectional view of a semiconductor substrate having a ferroelectric film of the present invention.
FIG. 7 is a cross-sectional view of a semiconductor substrate for explaining a state in which a ferroelectric film is partially crystallized from an amorphous state using the mask of the present invention.
FIG. 8 is a characteristic diagram showing crystallization conditions for the ferroelectric film of the present invention.
FIG. 9 is a schematic cross-sectional view of a heat treatment apparatus provided with the flash lamp of the present invention.
10 is a cross-sectional view of a photograph showing a capacitor formed on a semiconductor substrate of the present invention and an Al wiring formed thereunder. FIG.
11A and 11B are a plan view and a cross-sectional view of a silicon wafer on which a light-shielding mask according to the present invention is arranged.
FIG. 12 is a characteristic diagram obtained by optical measurement of a state after a PZT film formed on a semiconductor substrate is crystallized with a flash lamp and a state without crystallizing.
FIG. 13 is a characteristic diagram optically measured after the PZT film formed on the semiconductor substrate is crystallized with a flash lamp and when it is not crystallized.
[Explanation of symbols]
1, 20, 40, 50... Semiconductor substrate (wafer),
2, 9, 13, 26 (26a, 26b, 26c, 26d, 26e), 30, 41, 48 ... insulating film, 3 ... silicon nitride film,
4, 10, 23, 42 ... plug,
5, 32, 43 ... barrier layer 6, 27, 45 ... lower electrode,
7, 28, 34, 46 ... ferroelectric film (PZT film),
8, 29, 35, 47 ... upper electrode,
11, 21... Source / drain regions,
12, 25 (25a, 25b, 25c, 25d, 25e), 31 ... wiring,
22 ... Cobalt silicide, 24 ... Ti / TiN laminated film,
33 ... Gate oxide film, 100 ... Sample chamber,
102 ... Sample stage, 103 ... Gas inlet,
104 ... exhaust port, 105 ... quartz window, 106 ... bar lamp,
107: Flash lamp, 108 ... Wafer,
109, 110: Power supply.

Claims (3)

  A semiconductor substrate, a connection plug embedded in a first insulating film formed on the semiconductor substrate, a lower electrode electrically connected to the connection plug, formed on the lower electrode and crystallized A capacitor comprising a ferroelectric film and an upper electrode formed on the ferroelectric film, and a silicon oxide film formed on the first insulating film so as to cover the capacitor. In a method of manufacturing a semiconductor device comprising two insulating films, the ferroelectric film is heated and crystallized using a flash lamp in a state where the semiconductor substrate is maintained at 350 to 400 ° C. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1 , wherein the ferroelectric film is made of lead zirconate titanate. 3. The semiconductor device according to claim 1, wherein the flash lamp irradiation performed to crystallize the ferroelectric film is performed according to the conditions of the following formulas (1) and (2): Manufacturing method.
E ≧ − (T / 10) +55 (1)
I = α · E / τ> 1500 (2)
E (J / cm ² ) is the output of the Xe flash lamp (the amount of energy stored in the capacitor determined from the total amount of charge stored in the capacitor is defined as radiation efficiency 0.4 and reflection efficiency 0.5, and the irradiation area is the lamp layout area. I (A) represents the flash lamp maximum current value, τ (msec) represents the pulse width (defined as the half-value width of the pulse current waveform) (irradiation time), and T (° C. ) Represents an assist temperature (temperature of the semiconductor substrate during crystallization), and α is 70.

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