JPH11233734A - Semiconductor memory element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory element having good characteristic by introducing an electrode structure which can be resistive to annealing under a high temperature. SOLUTION: In a method of manufacturing a semiconductor memory element, after an Ir film 4 is formed on a diffused barrier film 5 consisting of Tax Si1-x Ny or Hfx Si1-x Ny (0.2<x<1, 0<y<1), an initial film 5 is formed in the thickness or 300 Å or less under the temperature equal to or higher than 300 deg.C but equal to or lower than 400 deg.C. Next, an IrO2 film 6 and a dielectric film 7 are sequentially formed on the initial film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a lower electrode and a dielectric film electrically connected to a select transistor via a conductive plug and a diffusion barrier film. And a semiconductor memory device provided with a capacitor comprising an upper electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art Ferroelectrics have many functions such as spontaneous polarization, high dielectric constant, electro-optic effect, piezoelectric effect, and pyroelectric effect, and are therefore widely applied to devices. For example, the pyroelectricity is used for an infrared linear array sensor, the piezoelectricity is used for an ultrasonic sensor, the electro-optic effect is used for a waveguide type optical modulator, and the high dielectric property is used. It is used in various fields such as DRAM and MMIC capacitors. Above all, with the recent development of thin film forming technology, a ferroelectric nonvolatile memory (F
RAM) has been actively developed.

A non-volatile memory using a ferroelectric thin film is:
Due to its characteristics such as high-speed writing / reading, low-voltage operation, and high resistance to repeated writing / reading operations, it not only replaces the conventional nonvolatile memory but also
As a memory that can be replaced in the SRAM and DRAM fields, research and development for practical use have been actively conducted.

Conventionally, oxide ferroelectrics (PZT (lead zirconate titanate), SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ ) have been studied as ferroelectric materials used for ferroelectric capacitors. And Pt, Pt / T
a, a noble metal material such as Pt / Ti or a composite electrode of a noble metal material and an adhesion film has been used for studying the characteristics of a ferroelectric thin film.

In order to utilize the function of a ferroelectric film, a crystallized film is required. Therefore, high-temperature heat treatment at 600 to 800 ° C. in an oxygen atmosphere is required as a crystallization process.

Further, it is said that a stacked structure is indispensable as a device structure for realizing high integration of 4 Mbit or more using these ferroelectric capacitors and processes. That is, a structure in which the select transistor and the ferroelectric capacitor are electrically connected using a conductive plug such as polysilicon is required. In the case of the Pt / polysilicon structure, a ferroelectric crystallization process is performed. In this case, a diffusion barrier film such as TiN is required because the Pt lower electrode causes a silicidation reaction.

However, the Pt film itself has sufficient oxidation resistance, but in the Pt / TiN / Ti structure, TiN is oxidized by oxygen gas permeating the Pt film grain boundaries in the ferroelectric crystallization process. It is said that "19
Proceedings of the 43rd Alliance Lecture Meeting on Applied Physics, Spring 1996, 28p-V-6, (pp. 500). Furthermore, "Proceedings of the 43rd Lecture Meeting on Applied Physics in the Spring of 1996, 28p-V-7, (pp.50
0) ”, in order to reduce the stress change caused by the volume expansion accompanying the oxidation of TiN,
There was a very serious problem that peeling or Pt hillocks occurred upward at the Pt / TiN interface.

Further, due to the oxygen permeability of the Pt film described above, when an adhesion film is used, Pt / Ta / Ti
With both N / Ti and Pt / Ti / TiN / Ti structures, Pt
Another problem is that Ta or Ti immediately below is oxidized, resulting in formation of an insulator and disconnection of electrical connection. Incidentally, the lowermost Ti is a film necessary for making contact with the polysilicon.

As described above, when Pt or only Pt and an adhesion film are used as electrodes, a diffusion barrier film such as TiN is oxidized, and the problems of hillocks and contact failure increase.
It was difficult to realize a stacked structure.

On the other hand, as a lower electrode of the oxide ferroelectric film, an oxide electrode material such as IrO ₂ , RuO ₂ , Rh
O ₂ , OsO ₂ , ReO _{2, and the} like have begun to be studied in terms of their excellent barrier properties and compatibility with the oxide dielectric formed thereon.

Above all, IrO ₂ is described in the document “Ap
pl. Phys. Lett. vol. 65 (1994)
pp. 1522-1524 "and" Jpn. J. App.
l. Phys. vol. 33 (1994) pp. 520
7-5210, it is reported that the fatigue characteristics of PZT formed on Ir / IrO ₂ / polysilicon or Pt / IrO ₂ / polysilicon electrodes are remarkably improved. This is because the IrO ₂ film has a barrier property to ferroelectric film constituent elements such as Pb.

However, in this structure, the problem of contact failure due to oxidation of polysilicon at the interface between IrO ₂ and polysilicon, and the problem of silicidation of IrO ₂ formed immediately above polysilicon are caused by the formation of the IrO ₂ film and the strong It occurs during the process of forming the dielectric film.

In order to solve the above-mentioned problem of the reaction between Ir and IrO ₂ and polysilicon, IrO ₂ (100) in which TiN is applied to oxide electrode IrO ₂ as a barrier metal.
0Å) / Ir (500Å) / TiN / Ti lower electrode is reported in “Proceedings of the 43rd Joint Lecture Meeting on Applied Physics Spring 1996, 28p-V-4, (pp.499)”.

As a result of forming a high dielectric SrTiO ₃ film and performing ion implantation to check the contact with the silicon substrate whose resistance has been reduced, it was confirmed that an ohmic contact was established, and the leakage current density was 10%. ^-7 A / c
It is stated that m ² , a relative dielectric constant of about 216 and a value comparable to the characteristics on the Pt electrode can be obtained. Such IrO ₂ /
Ir / TiN / Ti structure is a high dielectric material SrT
In a process at a relatively low temperature of 200 to 450 ° C. used for the iO ₃ film, since there is no deterioration in the electrical characteristics of the capacitor due to the deterioration of hillocks and flatness, it is promising for a stacked type structure using a high dielectric capacitor. It has been confirmed that there is.

However, in the ferroelectric crystallization process, an oxygen atmosphere of 600 ° C. or more is required even when a PZT film is formed, and an oxygen atmosphere of 800 ° C. or more is generally used for SrBi ₂ Ta ₂ O ₉ . Often used for. At this temperature, in the Pt / TiN / Ti structure, in addition to the problem that conduction cannot be achieved due to oxidation of Ti as an adhesion film, hillocks occur due to film stress caused by oxidation of TiN. Also, IrO ₂ / Ir / TiN / T
Hillocks also occur in the i-structure due to film stress due to the crystallization process at high temperatures (> 600 ° C.).

[0016]

However, in order to increase oxidation resistance, Ir and IrO ₂ having high crystallinity are required.
However, when IrO ₂ is directly formed on Ir at a high temperature, there is a problem that a film unevenness occurs and a uniform film cannot be formed at a high temperature. In addition, there is a problem that the heat resistance of the diffusion barrier film is low and hillocks and the like are generated in a high-temperature atmosphere.

As described above, the practical use of a memory using a ferroelectric film or a high-dielectric film in a stacked type structure requires 600 ° C.
It is desirable to have a process resistance in the heat treatment step in an oxidizing atmosphere, no reaction with a ferroelectric material deposited on the upper portion, a flat and dense shape, and a resistivity equivalent to that of a conventional Pt electrode. I was

[0018]

According to a first aspect of the present invention, there is provided a semiconductor memory device according to the present invention, wherein a lower electrode and a dielectric film are electrically connected to a selection transistor via a conductive plug and a diffusion barrier film. and a semiconductor memory device having a capacitor consisting of the upper electrode, the diffusion barrier film Ta _x Si _1-x N _y or _{Hf x Si 1-x N y} (0.2 <x <
1, 0 <y <1), and an Ir film and an IrO ₂ film are sequentially formed as a lower electrode on the diffusion barrier film.

In the semiconductor memory device according to the present invention, the Ir film and the I film may be used as the lower electrode.
The rO ₂ film and a conductive film containing at least one metal element selected from the group consisting of Pt, Ir, Ru, Rh, Os and Re are sequentially formed. 3. A method for manufacturing a semiconductor memory device according to (1).

Further, the semiconductor memory device of the present invention according to claim 3, the diffusion barrier film Ta _x Si _1-x N _y or _{Hf x Si 1-x N y} (0.75 <x <0. 95, 0.3 <
3. The semiconductor memory device according to claim 1, wherein y <0.5.

Further, the semiconductor memory device of the present invention according to claim 4, the ratio of the thickness of the IrO ₂ film of the film thickness and the Ir film, 1 ≦ (IrO ₂ film having a thickness / Ir film Thickness) ≤
3. The semiconductor memory device according to claim 1, wherein

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, comprising: a lower electrode, a dielectric film, and an upper portion electrically connected to a selection transistor via a conductive plug and a diffusion barrier film. In the method for manufacturing a semiconductor memory device provided with a capacitor composed of an electrode, an Ir film is formed on the diffusion barrier film, and then at 300 ° C.
Forming an initial film having a thickness of 50 ° or more and 300 ° or less containing at least one metal element selected from the group consisting of Ir, Ru, Rh, Os and Re at a temperature of 00 ° C or less; Forming an IrO ₂ film, the dielectric film, and the upper electrode on the initial film sequentially.

According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device according to the present invention, wherein a group consisting of Pt, Ir, Ru, Rh, Rh, Os and Re is provided between the IrO ₂ film and the dielectric film. 6. The method according to claim 5, further comprising the step of forming a conductive film containing at least one metal element selected from the group consisting of:

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor memory device, the IrO ₂ film is formed at 450 ° C. or more and 700 ° C. or less.
A method for manufacturing a semiconductor memory device according to claim 5 or 6.

In the method of manufacturing a semiconductor memory device according to the present invention, the ratio of the IrO ₂ film thickness to the Ir film thickness is 1 ≦ (IrO ₂ film thickness / Ir film). Thickness) ≦ 3
A method for manufacturing a semiconductor memory device according to any one of claims 5 to 7, characterized in that:

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device according to the present invention, wherein the lower electrode, the dielectric film and the upper portion are electrically connected to the selection transistor via the conductive plug and the diffusion barrier film. A method of manufacturing a semiconductor memory device having a capacitor composed of an electrode, after forming an Ir film on the diffusion barrier film, forming the dielectric film using a material containing oxygen; Forming an upper electrode.

According to a tenth aspect of the present invention, in the method for manufacturing a semiconductor memory device according to the present invention, the diffusion barrier film is made of Ta _x S
i _1-x N _y or _{Hf x Si 1-x N y} (0.2 <x <1,0 <
10. The method of manufacturing a semiconductor memory device according to claim 5, wherein y <1) is used.

In the method of manufacturing a semiconductor memory device according to the present invention, the diffusion barrier film may be formed by using a Ta _x S film.
i _1-x N _y or _{Hf x Si 1-x N y} (0.75 <x <0.9
5, 0.3 <y <0.5).
A method for manufacturing a semiconductor memory device according to claim 10.

Further, in the method of manufacturing a semiconductor memory device according to the present invention, the initial film is made of an IrO ₂ film. Item 12. A method of manufacturing a semiconductor memory device according to any one of items 11.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a diagram showing a cross-sectional structure in a state where a ferroelectric film is formed on a lower electrode according to an embodiment of the present invention.
FIG. 3 is a diagram showing a change in resistivity when the Ta composition x in the Ta _x Si _(1-x) N _y film is changed, FIG. 3 is a diagram showing an XRD chart characteristic with a change in film forming temperature, and FIG. FIG. 5 is a diagram showing a change in resistivity of the IrO ₂ film when the film formation temperature is changed. FIG. 5 is a structural cross-sectional view of a semiconductor memory element according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing a hysteresis loop obtained by a semiconductor memory device. 1 and 5, reference numeral 1 denotes a silicon substrate, 2 denotes a thermal oxide film, 3 denotes a TaSiN film, 4 denotes an Ir film, 5 denotes an initial film, 6 denotes an IrO ₂ film, 7 denotes a ferroelectric film, and 8 denotes a ferroelectric film. A lower electrode, 9 is a LOCOS oxide film, 10 is a gate electrode, 11 is a source / drain region, 12 is a first silicon oxide film, 13 is a polysilicon plug, 14 is a TaSiN film, 15 is an Ir film, and 16 is IrO _2. / Initial film, 17 is a ferroelectric film, 18 is an upper electrode, 19 is a second silicon oxide film, 20 is a first aluminum lead electrode, and 21 is a second aluminum lead electrode.

The substrate used for a semiconductor memory device having a ferroelectric capacitor in the present invention is not particularly limited as long as it can be used as a substrate for ordinary semiconductor devices and integrated circuits. A semiconductor substrate, a compound semiconductor substrate such as GaAs, an oxide crystal substrate such as MgO, a glass substrate, and the like can be selected according to the type and use of an element to be formed, but a silicon substrate is preferable.

On this substrate, a lower electrode is formed. This lower electrode means a part of the semiconductor memory element to be formed in the present invention, that is, an electrode used when used as a capacitance material of a capacitor. This lower electrode is formed on a substrate, and may be formed on a substrate provided with an insulating film, a lower film wiring, a desired element, an interlayer insulating film, or the like, or a plurality thereof.

In this embodiment, a sputtering method is used as a film forming method, and Ir, Ru, Rh, and O are formed between IrO ₂ / Ir.
By inserting a thin film containing at least one of s and Re, unevenness occurring at the time of high-temperature film formation of IrO ₂ is eliminated, high-temperature film formation becomes possible, and the crystallinity of the electrode material is improved. An object of the present invention is to provide an electrode structure having both high oxidation resistance and high heat resistance. Further, by optimizing the composition of TaSiN and combining it with the lower electrode, it is possible to realize an electrode structure with improved high-temperature oxygen atmosphere resistance.

In the conventional method, Ir / IrO ₂ / Ir /
At a temperature of 600 ° C., 60
In the heat treatment of n, conduction with the lower silicon cannot be achieved due to oxidation of Ti. However, in the film formation of the present invention, even if the heat treatment was performed in a diffusion furnace at 700 ° C. for 60 minutes, there was no oxidation of the underlying TaSiN diffusion barrier film. According to this, an oxide electrode having heat resistance and oxidation resistance at a temperature of 100 ° C. or higher as compared with the conventional method can be produced.

In the present invention, a ferroelectric film is formed on the electrode structure to form a ferroelectric element. The ferroelectric thin film is made of an oxide ferroelectric (PZT (lead zirconate titanate)). , SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ ) or the like can be used. In this case, if the Bi-based ferroelectric having a layered perovskite structure, is not particularly limited, the ferroelectric _{film, Bi 2 A m-1 B} m O 3m + 3
(A is Na, K, Pb, Ca, Sr, Ba or Bi; B
Is preferably a ferroelectric material represented by Fe, Ti, Nb, Ta, W or Mo), and more preferably a compound in which m is a natural number. Specifically, Bi ₄ Ti ₃ O ₁₂ , SrB
i ₂ Ta ₂ O ₉ , SrBi ₂ Nb ₂ O ₉ , BaBi ₂ Nb
₂ O ₉ , BaBi ₂ Ta ₂ O ₉ , PbBi ₂ Nb ₂ O ₉ , PbB
i ₂ Ta ₂ O ₉ , PbBi ₄ Ti ₄ O ₁₅ , SrBi ₄ Ti ₄ O
₁₅ , BaBi ₄ Ti ₄ O ₁₅ , Sr ₂ Bi ₄ Ti ₅ O ₁₈ , Ba ₂
Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ Ti ₅ O ₁₈ , Na _0.5 Bi
_4.5 Ti ₄ O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O ₁₅ , Sr ₂ Bi ₄ T
i ₄ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ Ti ₅ O ₁₈
And the like, among which SrBi ₂ Ta ₂ O ₉ is preferable.

These ferroelectric films can be formed by selecting a known method, for example, a spin-on method, a reactive evaporation method, an EB evaporation method, a sputtering method, a laser ablation method, or the like. For example, in the spin-on method, generally, a part or all of the elements constituting the thin film are dispersed in a solvent, and the resultant is applied on a substrate by spin coating, dried, and then present in the film. The carbon component present is burned by sintering (temporary sintering), and then fired in a gas component containing oxygen or an oxygen compound to form a crystal having a perovskite structure, thereby forming a ferroelectric film on the substrate. .

An upper electrode film is formed on the ferroelectric film. The upper electrode film may be formed of a single layer structure such as a Pt film, or may be formed of the same material as the lower electrode film by the same method. A ferroelectric capacitor can be formed on the upper electrode film by performing a desired wiring step, an insulating film forming step, and the like.

In the semiconductor memory element of the present invention using a ferroelectric film, the ferroelectric element itself is used as a ferroelectric capacitor, and the ferroelectric element is used as a ferroelectric device or a semiconductor device. An integrated circuit can be configured by mounting the integrated circuit on a wafer for an integrated circuit. For example, a ferroelectric element is used as a capacitor of a nonvolatile memory, or
Applied to the gate electrode of FET, gate insulating film, source /
By forming the drain region and the like in combination, M
It can also be used as an FMIS-FET, MFS-FET, or the like.

Embodiment 1 Hereinafter, the steps of manufacturing a semiconductor memory device of the present invention, particularly, a diffusion barrier film of a capacitor, a lower electrode, and a ferroelectric film will be described.

First, a film thickness of about 6 is formed on the surface of the silicon substrate 1.
A thermal oxide film 2 of 000 ° is formed. Next, an amorphous TaSiN film 3 serving as a diffusion barrier film having a thickness of 1000 Å is formed by DC magnetron sputtering, and then heat-treated in a nitrogen atmosphere to stabilize the TaSiN film 3. This heat treatment may not be particularly necessary depending on the film forming conditions.

The composition of the formed TaSiN film 3 is Ta
It is preferable that _x Si _1-x N _y (0.2 <x <1, 0 <y <1), and further, 0.75 <x <0.95, 0.
It is more desirable that 3 <y <0.5.

As shown in FIG. 2, the composition y of nitrogen is set to 0.1.
By setting the composition x of 5, 0.41, 0.3, and Ta in each case to 0.75 to 0.95, 1000 to 20
The resistivity could be suppressed to about 00 μΩcm, and the reaction between the underlying polysilicon and the components of the thin film formed on the TaSiN was sufficiently suppressed. This was confirmed by Auger electron spectroscopy analysis and no reaction. However, in each case of 0.5 <y and y <0.3, even in the case of 0.75 <x <0.95, the barrier property is weak, and the barrier property between the underlying polysilicon and the thin film formed on the top is low. This is not an appropriate condition since the reaction occurs easily at sintering temperatures below 600 ° C.

The conditions for forming the amorphous TaSiN film 3 in this embodiment are as follows: an alloy target of Ta / Si = 10/3, a substrate temperature of 500 ° C., a sputtering power of 2000 W, and a sputtering gas pressure of 0.7 Pa, Ar
The flow rate / N ₂ flow rate was 3/2, and the heat treatment conditions were as follows: a temperature rising rate of 5 ° C./min and a holding temperature of 60 in a pure nitrogen atmosphere.
At 0 ° C., the holding time was 1 hour. X-ray diffraction spectroscopy confirmed that the tantalum silicon nitride 3 formed under the above conditions had an amorphous structure, and Auger spectroscopy confirmed that the composition ratio was Ta _0.85 Si _0.15 N _0.41. Was.

Subsequently, a lower electrode 8 was formed thereon by DC magnetron sputtering. The stacked film structure of IrO ₂ / Ir is such that an Ir film 4 is formed first, and then an IrO ₂ film 6 is formed.

First, the Ir film 4 was set to a DC power of 0.5 kW,
A substrate temperature of 500 ° C., a gas pressure of 0.6 Pa, and a film thickness of 100
0% created. The sputtering gas was only Ar gas. In the film formation stage, despite the high-temperature film formation at 500 ° C., the film showed dense and flat surface properties. This is because, by lowering the sputter power and the sputter rate, rapid grain growth was suppressed, and film roughness was prevented. The surface properties of the electrode structure were observed by SEM. further,
An initial film 5 for forming an IrO ₂ film 6 at 500 ° C. is formed on the Ir film 4. The film formation conditions were a DC power of 1 kW, a substrate temperature of 350 ° C., a gas pressure of 0.71 Pa, and a film thickness of 200
Å Created. The flow ratio of the sputtering gas is Ar / O ₂ = 1 /
It was set to 9. That is, reactive sputtering is performed using an Ir target to form an IrO ₂ film 5 on the substrate.

Here, the reason why the film formation temperature is set to 300 ° C. is as follows.
If the temperature at the time of film formation is higher than 400 ° C., Ir
This is because unevenness in film formation occurs on a metal such as the film 4, and when the temperature is lower than 300 ° C., variation in crystallinity of the film occurs in a subsequent film formation at a high temperature.

Although the film thickness was set to 200 ° this time, any film thickness of 300 ° or less can be used if a uniform film can be obtained. However, a film thickness of at least 50 ° is required. On the other hand, if the thickness exceeds 300 °, the oxidation resistance of the thin film becomes non-uniform due to variations in the crystallinity of the thin film during the high-temperature process, and hillocks occur in some places. When the film is formed by sputtering, the film becomes an island shape when the film thickness is less than 100 °. However, when the film is formed with a film thickness less than 100 °, exposure to oxygen plasma or irradiation of the substrate surface with ozone is performed. The IrO ₂ film 6 can be uniformly formed on the surface of the Ir film 4 with an arbitrary thickness, and can be used as the initial film 5.

In the first embodiment, the initial film 5 is made of IrO
_Two films may be used as long as the film contains at least one metal element selected from the group consisting of Ir, Ru, Rh, Os, and Re. However, later IrO
_{2 It} is desirable to use IrO ₂ , which uses the same raw material target as that for forming the film 6, for the initial film 5 from the viewpoint of improving film characteristics and simplifying the process.

Next, on this initial film 5 at 500 ° C., Ir
An O ₂ film 6 is formed. The film formation conditions were a DC power of 1 kW, a gas pressure of 0.71 Pa, and a film thickness of 1300 °. The sputtering gas flow ratio was set to Ar / O ₂ = 1/9. In this embodiment, the film formation temperature was set to 500 ° C. From the results of the XRD of FIG. 3, the XRD when the film was formed at 400 ° C. and 450 ° C.
Comparing the charts, it is apparent that the peak intensity of IrO ₂ (200) when IrO ₂ is formed at 450 ° C. or more is at least four times as large as that when the film is formed at 400 ° C. In addition, film formation at 450 ° C. and 500
It can be seen that there is almost no difference when compared with the film formation at a temperature of ° C. Therefore, the crystallinity changes between 400 ° C. and 450 ° C., indicating that IrO ₂ (200) is preferentially oriented and the crystallinity has not changed since then. Further, as shown in FIG. 4, the resistivity ρ of the IrO ₂ film gradually decreases to around 450 ° C., and thereafter keeps a low value. Therefore, the film forming temperature of the IrO ₂ film 6 may be 450 ° C. or higher.

When the temperature of the atmosphere reaches 700 ° C. or higher, Ir is oxidized by heating the substrate and the oxygen introduced into the chamber when the IrO ₂ film 6 is formed, and the fine IrO is formed.
_It has been experimentally found that the _two aggregates are formed on the substrate. Therefore, the film formation temperature of the IrO ₂ film 6 is 7
It must be below 00 ° C. Further, in order to examine the oxidation resistance, the presence or absence of hillock when only the electrode was annealed in oxygen at each temperature was examined.
When the film was formed at 0 ° C. or lower, there was no heat resistance and oxidation resistance in oxygen at 600 ° C. or higher. On the other hand, when the film was formed at 450 ° C. or higher, no hillock was formed up to 800 ° C. in oxygen.
From these results, superiority at a film formation temperature of 450 ° C. or more was shown.

Next, SB is formed on the substrate by spin-on method.
The T film 7 was formed. In the method of forming the SBT film, first, a precursor solution in which constituent elements are dispersed in a solvent is formed, and the precursor solution is applied at a rotation speed of 3000 rpm using a spinner, and is applied at 150 ° C. for 10 minutes in the atmosphere. After drying, pre-baking is performed at 400 ° C. for 30 minutes in the air, and then crystallization is performed at 700 ° C. for 1 hour to form. These steps were repeated three times to form the SBT film 7 at 2000 ° (FIG. 1). Hillocks and the like were not observed after the SBT film 7 was formed, and the lower electrode 8 was determined by cross-sectional SEM and Auger spectroscopy.
And SBT film 7 did not react.

Similarly, instead of TaSiN, Hf
Similar results were obtained when SiN was used.

Further, a Pt film is formed on the lower electrode by 500 °.
When an SBT film was formed on the deposited electrode in the same manner as described above, no hillocks or the like were observed, and no reaction was observed. Further, in the case of this structure, the leakage current value was reduced by about one digit. That is, in the SBT / IrO ₂ (including IrO _{2 serving} as an initial film) / Ir / TaSiN structure, the leakage current value was 1.2 × 10 ⁻⁶ (A / cm ² ), whereas SBT / Pt / IrO ₂ (IrO ₂ to be the initial film
) / Ir / TaSiN structure, the leakage current value was 9.8 × 10 ⁻⁸ (A / cm ² ). In this case, Pt was used. However, a similar effect was exhibited by, for example, a Pt-Rh thin film made of Ir, Ru, Rh, Os, Re and an alloy thereof.

From the above results, in the lower electrode formed by using the oxide conductive film 8 shown in Embodiment 1, Ir
By using the initial film 5 on the film, the film can be formed at 450 ° C. or higher, thereby improving the crystallinity and preventing the tantalum silicon nitride film 3 from being oxidized in a high-temperature oxygen atmosphere. . Therefore, a ferroelectric film can be formed in a high-temperature and oxygen atmosphere, and an electrode having a sufficient and sufficient oxygen barrier property for realizing a high-density FRAM can be formed.

Embodiment 2 Next, the Ir film and the IrO constituting the lower electrode 8 of the present invention will be described.
Examples of _two film thicknesses will be described.

As in the first embodiment, a thermal oxide film 2 is formed on a silicon substrate 1 at 6000 °, and a tantalum silicon nitride film 3 is formed thereon.

Subsequently, a lower electrode 8 was formed thereon by DC magnetron sputtering. The stacked film structure of IrO ₂ / Ir is such that an Ir film 4 is formed first, and then an IrO ₂ film 6 is formed.

First, the Ir film 4 was set to a DC power of 0.5 kW,
A substrate temperature of 500 ° C., a gas pressure of 0.6 Pa, and a film thickness of 100
0% created. The sputtering gas was only Ar gas.

Further, an IrO ₂ film 6 is deposited on the Ir
An initial film 5 made of IrO ₂ for forming a film at 0 ° C. is formed. The film formation conditions are DC power 1 kW, substrate temperature 350
C. and a gas pressure of 0.71 Pa, and a film thickness of 200 ° was formed.
The flow ratio of the sputtering gas was set to Ar / O ₂ = 1/9.

Next, on this initial film 5 at 500 ° C., Ir
An O ₂ film 6 is formed. Film formation conditions were DC power of 1 kW, gas pressure of 0.71 Pa, and a film thickness of 500 to 1800 °. The flow ratio of the sputtering gas is Ar / O ₂ = 1 /
It was set to 9.

In order to show the relationship between this film thickness and heat resistance,
As in Example 1, evaluation was made based on the presence or absence of hillocks caused by annealing in oxygen. From the evaluation results, 1 ≦ (IrO
There was no hillock in the range of ₂ film thicknesses (including the initial film thickness when the initial film 5 made of an IrO ₂ film is present. The same applies hereinafter) / (Ir film thickness) ≦ 3. 1> (IrO ₂
If the thickness of the film) / (thickness of the Ir film), there is no oxygen barrier property of IrO _2, it will be permeable to oxygen, IrO ₂
Ir precipitates on the film and forms a single crystal of IrO ₂ , resulting in film roughness.

Further, 3 <(thickness of IrO ₂ film) / (Ir
In the case of (film thickness), since the IrO ₂ film is thick, strong stress is generated during high-temperature processing in the lateral direction, and fine cracks are generated. Oxygen enters from there, and the oxygen that has entered is I
However, under this condition, the thickness of the Ir film 4 does not have sufficient resistance to the transmitted oxygen,
As a result, oxygen reaches the TaSiN film 3 to cause oxidative expansion, and as a result, separation occurs.

In the case of 1 ≦ (IrO ₂ film thickness) / (Ir film thickness), the IrO ₂ film has sufficient resistance to oxygen and blocks oxygen. No peeling is seen. It was also found that if (IrO ₂ film thickness) / (Ir film thickness) ≦ 3, the stress was relaxed and hillocks did not occur.

In the first embodiment, the thickness of the Ir film is 1000
And the total film thickness of the initial film 5 and the IrO ₂ film 6 is 15
00Å, and (IrO ₂ film thickness) / (Ir film thickness) = 1.5.

From the above results, hillocks can be suppressed by controlling the film thickness, and a high heat resistant electrode for realizing a high density FRAM can be formed.

Example 3 Next, an example of heat resistance and oxidation resistance depending on the composition of a TaSiN film as a diffusion barrier film will be described.

As in the first embodiment, a thermal oxide film 2 having a thickness of about 6000 ° is formed on a silicon substrate 1 and a TaS film is formed thereon.
An iN film 3 is formed. The composition of the formed TaSiN film 3 was the same as that shown in Example 1.

On top of this, the Ir film 4 was set to a DC power of 0.5 k.
W, substrate temperature 500 ° C., gas pressure 0.6 Pa, film thickness 10
00 mm was produced. The sputtering gas was only Ar.

Next, a spin-on method is used to
The BT film 7 was formed in the same manner as in Example 1. On this occasion,
Firing for crystallization was performed for 1 hour each, for a total of 700 ° C. for 3 hours.

After the formation of the SBT film, no hillocks or the like were observed, and no reaction between the SBT film 7 and other films was observed from the cross-sectional SEM observation. Also, as a result of Auger analysis, SBT
A region where the constituent elements are interdiffused at the interface between the film and the Ir electrode is observed at about 100 °.
Spreading of about 00 ° was observed.

In the third embodiment, the IrO ₂ film is not used as in the first embodiment, but the principle of not allowing oxygen to permeate is the same. In other words, when the SBT film is formed, the surface of the Ir film is oxidized by, for example, oxygen contained in the solution by a spin-on method, and an IrO ₂ film having a thickness of about 100 to 300 ° is formed. It is formed. These films exhibit the same effect as when the IrO ₂ film is directly formed, and exhibit the same oxygen barrier properties. By using this embodiment, a lower electrode having an oxygen barrier property can be formed without performing a separate step of forming an IrO ₂ film.

Here, the composition of Ta _x Si _1-x N _y is set to 0.
By setting 75 <x <0.95 and 0.3 <y <0.5, a film having a high barrier property at a high temperature of 600 ° C. or higher can be formed.

For forming a ferroelectric film, a similar effect can be obtained by a sputtering method or an MOCVD method in addition to the spin-on method. Further, the film thicknesses of Ir and TaSiN are not limited to the film thicknesses used in the third embodiment, and may be any film thickness at which no reaction occurs at a desired temperature. Further, although a TaSiN film was used as the diffusion barrier film, the same effect was obtained with HfSiN. Similar results were obtained for electrodes formed on TaSiN or HfSiN, which are barrier metal films, with Pt, Ru or Os in addition to Ir.

From the above results, the heat resistance and the oxidation resistance were improved by the electrode structure shown in Example 3, and the TaSiN film 3 was not oxidized in the high-temperature oxygen atmosphere.
For this reason, a ferroelectric film can be formed in a high-temperature and oxygen atmosphere, and an electrode having an oxygen barrier property necessary and sufficient for realizing a high-density FRAM can be formed.

Embodiment 4 Next, the formation of a semiconductor memory device using a ferroelectric using the lower electrode 8 using the oxide conductor shown in Embodiments 1 to 3 will be described.

First, a film thickness of about 5
The LOCOS oxide film 9 is formed to a thickness of 000 ° to form an element isolation region. Next, after forming a selection transistor including a gate electrode 10, a source / drain region 11, and the like, a first silicon oxide film 12 is formed as an interlayer insulating film by a CVD method.
A film is formed with a thickness of about 5000 °, and then a contact hole having a diameter of 0.5 μm is formed. Next, after the polysilicon is buried by the CVD method, the surface is flattened by the CMP method, and the polysilicon plug 13 is formed.

Next, on the polysilicon plug 13,
As shown in Examples 1 and 2, an amorphous TaSiN film having a thickness of 1000 ° was formed by DC magnetron sputtering.
The film 14 is stabilized. This heat treatment may not be particularly necessary depending on the film forming conditions.

The conditions for forming the amorphous TaSiN film 14 are as follows: an alloy target of Ta / Si = 10/3, a substrate temperature of 500 ° C., and a sputtering power of 2000
W, the sputtering gas pressure was 0.7 Pa, the flow ratio of the sputtering gas was Ar / N ₂ = 3/2, and the heat treatment conditions were a temperature rising rate of 5 ° C./min and a holding temperature of 60 in a pure nitrogen atmosphere.
At 0 ° C., the holding time was 1 hour.

Subsequently, a multilayer electrode structure using an oxide dielectric was formed thereon by the DC magnetron sputtering method shown in Examples 1 and 2.

First, the Ir film 15 was set to a DC power of 0.5 k.
W, substrate temperature 500 ° C., gas pressure 0.6 Pa, film thickness 1
2,000 mm. The sputtering gas was only Ar gas.

Further, an initial film made of an IrO ₂ film for forming an IrO ₂ film 16 at 500 ° C. is formed on the Ir film 15. The film formation conditions were a DC power of 1 kW and a substrate temperature of 35.
At 0 ° C. and a gas pressure of 0.71 Pa, a film thickness of 200 ° was formed. The flow ratio of the sputtering gas was set to Ar / O ₂ = 1/9.

Next, an IrO ₂ film 16 is formed on this film at 500 ° C. The film formation conditions were a DC power of 1 kW, a gas pressure of 0.71 Pa, and a film thickness of 1300 °. The sputtering gas flow ratio was set to Ar / O ₂ = 1/9. In the case where the lower electrode is formed by further forming a Pt film on the IrO ₂ film 16 by 500 °, the leak current can be further reduced as in the case of the first embodiment.

Next, a ferroelectric film 17 was formed on the deposited electrode as shown in the first embodiment. Next, after an electrode having a thickness of 500 ° is formed by DC magnetron sputtering, the ferroelectric film 17 is dry-etched using argon and C ₂ F ₆ , and the upper electrode 18 is dry-etched using Cl _2. It was processed to a size of, for example, 2.6 μm square by an etching method.

Subsequently, the electrodes having the stacked film structure were processed by, for example, a dry etching method using Cl ₂ and C ₂ F ₆ , and the TaSiN film 14 was processed by a dry etching method using C ₂ F ₆ .

Thereafter, a second silicon oxide film 19 is formed as an interlayer insulating film by using the CVD method, and then a contact hole is formed, and the upper electrode 1 of the ferroelectric capacitor is formed.
The aluminum extraction electrode 20 from 8 is formed by DC magnetron sputtering, and a semiconductor memory device as shown in FIG. 5 is formed.

By applying a triangular wave voltage between the aluminum extraction electrode 20 from the upper electrode 18 and the aluminum extraction electrode 20 from the silicon substrate 1 of the capacitor having the ferroelectric film manufactured by the above process, The hysteresis loop shown in FIG. 6 was obtained. still,
The applied triangular wave had an intensity of 150 kV / cm and a frequency of 75 Hz. As shown in FIG. 6, ferroelectric characteristics large enough to be used as a ferroelectric capacitor are obtained, and the symmetry of the hysteresis loop is not broken, so that the silicon substrate 1 and the Ir / IrO ₂ This shows that the contact with the lower electrode is sufficiently obtained. This indicates that there is no reaction between Ir and the polysilicon plug. Further, the diffusion barrier film and the Ir / IrO ₂
This indicates that there is no reaction with the lower electrode.

Further, as a result of observing the cross-sectional structure with an electron microscope, there was no reaction in each film, and no reaction was observed by Auger spectroscopy.

In the above embodiment, the MOD method is used as the method for forming the dielectric film. However, a method such as a vacuum evaporation method, a DC magnetron sputtering method, and an MOCVD method may be used. In this embodiment, SBT is used as the ferroelectric film, but SrB is used as another dielectric film.
i ₂ Nb ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ , BaBi ₂ Nb ₂ O ₉ , B
aBi ₂ Ta ₂ O ₉ , PbBi ₂ Ta ₂ O ₉ , SrBi ₄ Ti ₄
O ₁₅ , SrBi ₄ Ti ₄ O ₁₅ , PbBi ₄ Ti ₄ O ₁₅ , Na
_0.5 Bi _4.5 Ti ₄ O ₁₅ , K _0.5 Bi _4.5 Ti ₄ O ₁₅ , Sr ₂
Bi ₄ Ti ₄ O ₁₈ , Ba ₂ Bi ₄ Ti ₅ O ₁₈ , Pb ₂ Bi ₄ T
i ₅ O _{18 and the} like, and also as a high dielectric film (B
a _x Sr _1-x ) TaO ₃ , SrBi ₄ Ti ₄ O _{15, and the} like also provide sufficient oxidation resistance.

The same effect was obtained when tungsten or the like was used in addition to polysilicon as the contact plug material.

[0091]

As described above in detail, by using the present invention, since the diffusion barrier film has an amorphous structure, it has no grain boundaries and is remarkably resistant to oxygen, platinum, bismuth and the like. Has barrier properties. Further, by the lower electrode including the IrO ₂ film treated at a high temperature using the initial film,
Oxygen does not permeate even when sintered in a high-temperature oxygen atmosphere, so that the upper surface of the plug made of polysilicon, tungsten, or the like is not oxidized, and good contact can be maintained.

Therefore, a semiconductor memory element having good characteristics can be obtained by using an electrode structure that can withstand annealing at a high temperature.

Further, by using the present invention described in claim 2 and claim 6, it is possible to reduce the leak current.

Further, by using the present invention described in claims 3 and 11, the oxygen barrier properties can be further improved.

Further, by using the present invention described in claims 4 and 8, the occurrence of hillocks can be suppressed.

Further, by using the present invention as defined in claim 7, the resistivity of the IrO ₂ film is lowered, and when the IrO ₂ film is formed, the underlying Ir film is oxidized and fine IrO ₂ aggregates are formed. This can be suppressed.

Further, by using the present invention as set forth in claim 9, it is possible to eliminate the step of separately forming an IrO ₂ film,
Since a lower electrode having oxygen barrier properties can be obtained, the number of steps can be reduced.

Further, using the present invention according to claim 12,
Ir using the same raw material target as used in the formation of the IrO ₂ film
By using O ₂ for the initial film, the film characteristics can be improved and the process can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional structure of an embodiment of the present invention.

FIG. 2 is a diagram showing a change in resistivity when a Ta composition x in a Ta _x Si _1-x N _y film is changed.

FIG. 3 is a diagram showing XRD chart characteristics depending on a change in film forming temperature.

FIG. 4 shows IrO ₂ of resistivity when film forming temperature is changed.
FIG. 4 is a diagram illustrating a change in the resistivity of a film.

FIG. 5 is a structural sectional view of a semiconductor memory device according to one embodiment of the present invention;

6 is a diagram showing a hysteresis loop obtained by the semiconductor memory device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Thermal oxide film 3 TiSiN film 4 Ir film 5 Initial film 6 IrO ₂ film 7 Ferroelectric film 8 Lower electrode 9 Locos oxide film 10 Gate electrode 11 Source / drain region 12 First silicon oxide film 13 Polysilicon Plug 14 TaSiN film 15 Ir film 16 IrO ₂ / initial film 17 Ferroelectric film 18 Upper electrode 19 Second silicon oxide film 20 First aluminum extraction electrode 21 Second aluminum extraction electrode

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792 (72) Inventor Jun Kudo 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka

Claims (12)

[Claims] 1. A semiconductor memory device comprising a capacitor composed of a lower electrode, a dielectric film, and an upper electrode, which is electrically connected to a selection transistor via a conductive plug and a diffusion barrier film. There Ta _x Si _1-x N _y or Hf _x Si _1-x
N _y (0.2 <x <1, 0 <y <1), wherein an Ir film and an IrO ₂ film are sequentially formed as a lower electrode on the diffusion barrier film. . 2. The lower electrode, wherein the Ir film, the IrO ₂ film, and a conductive film containing at least one of metal elements selected from the group consisting of Pt, Ir, Ru, Rh, Os and Re. 2. The method according to claim 1, wherein the semiconductor memory devices are sequentially formed. Wherein said diffusion barrier layer is Ta _x Si _1-x N _y or _{Hf x Si 1-x N y} (0.75 <x <0.95,0.3
3. The semiconductor memory device according to claim 1, wherein <y <0.5). Ratio of 4. The thickness of the IrO ₂ film of the film thickness and the Ir film, 1 ≦ (IrO ₂ film thickness of thickness / Ir film)
4. The semiconductor memory device according to claim 1, wherein ≦ 3. 5. 5. A method of manufacturing a semiconductor memory device including a capacitor comprising a lower electrode, a dielectric film and an upper electrode, which is electrically connected to a selection transistor via a conductive plug and a diffusion barrier film. After forming an Ir film on the barrier film, a film containing at least one of metal elements selected from the group consisting of Ir, Ru, Rh, Os and Re at 300 ° C. or higher and 400 ° C. or lower. The thickness is more than 50mm and 300
(4) A method for manufacturing a semiconductor memory device, comprising: a step of forming an initial film described below; and a step of sequentially forming an IrO ₂ film, the dielectric film, and an upper electrode on the initial film. 6. A conductive film containing at least one metal element selected from the group consisting of Pt, Ir, Ru, Rh, Os, and Re between the IrO ₂ film and the dielectric film. 6. The method according to claim 5, further comprising the step of forming. 7. The method according to claim 1, wherein the IrO ₂ film is formed at a temperature of 450 ° C. or higher.
The method according to claim 5, wherein the semiconductor memory device is formed at a temperature of 700 ° C. or less. 8. The method according to claim 5, wherein a ratio of the film thickness of IrO _{2 to} the film thickness of Ir is 1 ≦ (film thickness of IrO ₂ / film thickness of Ir) ≦ 3. Item 8. A method for manufacturing a semiconductor memory device according to any one of Items 7. 9. A method of manufacturing a semiconductor memory device including a capacitor comprising a lower electrode, a dielectric film and an upper electrode, which is electrically connected to a selection transistor via a conductive plug and a diffusion barrier film. Forming an Ir film on a barrier film, forming the dielectric film using a raw material containing oxygen, and forming an upper electrode on the dielectric film; A method for manufacturing a memory element. 10. A the diffusion barrier film Ta _x Si _1-x N _y
Or _{Hf x Si 1-x N y} (0.2 <x <1,0 <y <1)
10. The method for manufacturing a semiconductor memory device according to claim 5, wherein: To 11. The diffusion barrier film Ta _x Si _1-x N _y
Or _{Hf x Si 1-x N y} (0.75 <x <0.95,0.
3 <y <0.5) is used.
0. A method for manufacturing a semiconductor memory device according to item 0. 12. The method according to claim 5, wherein the initial film is made of an IrO ₂ film.