JP3299909B2 - Multilayer structure electrode using oxide conductor - Google Patents

Multilayer structure electrode using oxide conductor

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Publication number
JP3299909B2
JP3299909B2 JP05848097A JP5848097A JP3299909B2 JP 3299909 B2 JP3299909 B2 JP 3299909B2 JP 05848097 A JP05848097 A JP 05848097A JP 5848097 A JP5848097 A JP 5848097A JP 3299909 B2 JP3299909 B2 JP 3299909B2
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Japan
Prior art keywords
electrode
iro
layer
film
tasin
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JPH10242078A (en
Inventor
泰史 荻本
俊 御手洗
昌也 長田
宏典 松永
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Sharp Corp
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Sharp Corp
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は酸化物導電体を用い
た多層構造電極に関し、より詳細には、酸化物強誘電体
を応用した各種デバイス、例えば強誘電体不揮発性メモ
リ、DRAM、赤外線センサアレイ等における強誘電体
薄膜の下部電極として用いられる多層構造電極に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layered electrode using an oxide conductor, and more particularly to various devices using an oxide ferroelectric, such as a ferroelectric nonvolatile memory, a DRAM, and an infrared sensor. The present invention relates to a multilayer structure electrode used as a lower electrode of a ferroelectric thin film in an array or the like.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】近年、
DRAM並の高集積化、高速動作、低消費電力、高信頼
性を兼ね備える不揮発性メモリとして強誘電体メモリの
開発が行われている。強誘電体メモリ用のメモリキャパ
シタ材料としてはPZT(チタン酸ジルコン酸鉛)、S
rBi2Ta29、Bi4Ti312を始めとした酸化物
強誘電体の結晶薄膜が用いられている。
2. Description of the Related Art In recent years,
A ferroelectric memory has been developed as a nonvolatile memory having high integration, high-speed operation, low power consumption, and high reliability comparable to a DRAM. PZT (lead zirconate titanate), S
Crystal thin films of oxide ferroelectrics such as rBi 2 Ta 2 O 9 and Bi 4 Ti 3 O 12 are used.

【0003】酸化物強誘電体の結晶薄膜を形成する場
合、通常、酸素を含む雰囲気中で600〜800℃の高
温熱処理を必要とする。そのため、その下方に形成され
る下部電極は、高融点で耐酸化性に優れたPtが多く用
いられてきた。一方、メモリ素子の高集積化のためには
スタックセル(STC)構造の実現が望まれている。S
TC構造では、半導体トランジスタと強誘電体メモリキ
ャパシタとをポリシリコン等のプラグで接続する必要が
ある。しかし、従来のPt電極は耐酸化性には優れる
が、酸素を透過しやすいという問題点がある。このた
め、ポリシリコン上にPt電極を形成した場合には、強
誘電体薄膜を形成する際にプラグに用いられているポリ
シリコンが酸化されてしまい、電気的な接続が得られな
いという問題が起こる。
When a crystalline thin film of an oxide ferroelectric is formed, a high-temperature heat treatment at 600 to 800 ° C. is usually required in an atmosphere containing oxygen. Therefore, Pt having a high melting point and excellent oxidation resistance has been often used for the lower electrode formed thereunder. On the other hand, realization of a stack cell (STC) structure is desired for higher integration of memory elements. S
In the TC structure, it is necessary to connect the semiconductor transistor and the ferroelectric memory capacitor with a plug such as polysilicon. However, although the conventional Pt electrode is excellent in oxidation resistance, it has a problem that oxygen is easily transmitted. For this reason, when a Pt electrode is formed on polysilicon, the polysilicon used for the plug when the ferroelectric thin film is formed is oxidized, and the electrical connection cannot be obtained. Occur.

【0004】これに対して、酸素透過を防止するための
バリア層としてTiN、プラグと下部電極との間の接着
層としてTiを用いたPt/TiN/Ti等の多層構造
電極が検討されている。しかし、この場合もPtを透過
した酸素によってTiN層が酸化し、その体積膨張のた
めにPt/TiN界面での剥離やヒロック発生という新
たな問題が生じている(1996年春季第43回応用物
理学関係連合講演会講演予稿集28p−V−6、7)。
On the other hand, a multi-layer electrode such as Pt / TiN / Ti using TiN as a barrier layer for preventing oxygen permeation and Ti as an adhesive layer between a plug and a lower electrode has been studied. . However, also in this case, the TiN layer is oxidized by oxygen permeated by Pt, and the volume expansion causes a new problem such as separation at the Pt / TiN interface and generation of hillocks (43rd Applied Physics Spring 1996). Proceedings of the Lectures at Academic Alliance Lectures 28p-V-6, 7).

【0005】また、下部電極として、酸化物導電体材料
を用いることも検討されており、このうち、IrO2
RuO2、YBa2Cu37-X、LaSrCoO3等は優
れたバリヤ性や酸化物強誘電体との整合性等の点から有
望視されている。特に、IrO2は、ポリシリコン上に
直接形成された例が報告されている。例えば、特公平6
−87493号公報には、IrO2/ポリシリコン上に
BaTiO3を作製し良好な誘電特性が得られることが
記載されている。また、Appl.Phys.Lett.vol.65(1994)p
p.1522-1524、Jpn.J.Appl.Phys.vol.33(1994)pp.5207-5
210及び特開平8−51165号公報には、Ir/Ir
2/ポリシリコン又はPt/IrO2/ポリシリコン上
にPZTを形成した場合、その疲労特性が大幅に改善さ
れていることを記載されており、この理由としてIrO
2膜が、Pb等の強誘電体構成元素に対して良好なバリ
ア性を有していることが挙げられている。
The use of an oxide conductive material as the lower electrode has also been studied, of which IrO 2 ,
RuO 2 , YBa 2 Cu 3 O 7-x , LaSrCoO 3, and the like are promising from the viewpoint of excellent barrier properties and compatibility with oxide ferroelectrics. In particular, it has been reported that IrO 2 is formed directly on polysilicon. For example, Tokuho 6
Japanese Patent No. 87493 describes that BaTiO 3 is produced on IrO 2 / polysilicon to obtain good dielectric properties. Appl.Phys.Lett.vol.65 (1994) p
p.1522-1524, Jpn.J.Appl.Phys.vol.33 (1994) pp.5207-5
210 and JP-A-8-51165, Ir / Ir
It is described that when PZT is formed on O 2 / polysilicon or Pt / IrO 2 / polysilicon, the fatigue characteristics thereof are greatly improved.
It is mentioned that the two films have good barrier properties against ferroelectric constituent elements such as Pb.

【0006】しかし、これらの構造の様にポリシリコン
上に直接酸化物のIrO2を形成する場合には、ポリシ
リコン表面の酸化によるコンタクト不良の発生が懸念さ
れる。そこで、ポリシリコンとIrO2の間にバリアメ
タルを挿入したIrO2/Ir/TiN/Ti構造の多
層電極の検討が報告されている(1996年春季第43
回応用物理学関係連合講演会講演予稿集28p−V−
4)。この報告によれば、スパッタ法により形成したI
rO2(100nm)/Ir(50nm)/TiN(3
0nm)/Ti(20nm)/Si基板の構造をした電
極上に高誘電体SrTiO3(200nm)を形成し、
Pt(50nm)を上部電極としたキャパシタにおいて
は、比誘電率216以下、リーク電流密度10-7A/c
2以下の比較的良好な電気特性を得ており、この多層
構造電極がSTC構造の適用に有望であることが示され
いる。
However, when IrO 2 of oxide is formed directly on polysilicon as in these structures, there is a concern that contact failure may occur due to oxidation of the polysilicon surface. Therefore, a study of a multilayer electrode having an IrO 2 / Ir / TiN / Ti structure in which a barrier metal is inserted between polysilicon and IrO 2 has been reported (43rd Spring 1996).
Proceedings of the JSCE Lecture Meeting 28p-V-
4). According to this report, I was formed by sputtering.
rO 2 (100 nm) / Ir (50 nm) / TiN (3
0 nm) / Ti (20 nm) / High dielectric SrTiO 3 (200 nm) is formed on an electrode having a structure of a Si substrate.
In the capacitor using Pt (50 nm) as the upper electrode, the relative dielectric constant is 216 or less, and the leak current density is 10 −7 A / c.
Relatively good electrical properties of less than m 2 have been obtained, indicating that this multilayered electrode is promising for STC applications.

【0007】しかし、この多層構造電極の酸素バリア
性、反応防止性等については不明である。すなわち、S
rTiO3は、通常500℃以下の比較的低い温度で形
成されるが、この多層構造電極を600℃以上の成膜温
度を必要とする強誘電体薄膜の成膜プロセスに適用した
場合には、そのプロセス耐性が十分にあるか否かは自明
とは言えない。例えば、ゾルーゲル法によりPZT膜を
上記のPt/TiN/Ti電極上に形成する際、400
〜450℃の仮焼成段階ではヒロック発生や剥離は発生
しないが、600℃以上の本焼成でこれらの問題が発生
することが知られているからである。
However, the oxygen barrier property, reaction prevention property, and the like of this multilayer structure electrode are unknown. That is, S
rTiO 3 is usually formed at a relatively low temperature of 500 ° C. or lower, but when this multilayer structure electrode is applied to a ferroelectric thin film forming process requiring a film forming temperature of 600 ° C. or higher, It is not self-evident whether its process tolerance is sufficient. For example, when a PZT film is formed on the Pt / TiN / Ti electrode by the sol-gel method,
Hillock generation and peeling do not occur in the pre-firing stage at -450 ° C, but it is known that these problems occur in the main firing at 600 ° C or higher.

【0008】本発明は上記課題に鑑みなされたものであ
り、STC構造に適用可能なプロセス耐性に優れた電極
の開発の必要から、電極自体にヒロックや剥離が発生
せず、下部ポリシリコンプラグへの酸素拡散がなく、
電極の表面平坦性、緻密性が確保され、電極として
シート抵抗等の電気特性が確保される、600℃以上の
酸素雰囲気中での熱処理工程に対するプロセス耐性を有
する電極を実現できる多層構造電極を提供することを目
的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and since there is a need to develop an electrode having excellent process resistance applicable to an STC structure, hillocks and peeling do not occur on the electrode itself and the lower polysilicon plug can be connected to the lower polysilicon plug. Without oxygen diffusion
Provide a multi-layer electrode capable of realizing an electrode having process resistance to a heat treatment step in an oxygen atmosphere at 600 ° C. or higher, which ensures the surface flatness and denseness of the electrode and ensures electrical characteristics such as sheet resistance as the electrode. The purpose is to do.

【0009】[0009]

【課題を解決するための手段】本発明によれば、半導体
基板上に形成される多層構造電極において、下部にTa
又はHf、およびSi、Nを構成元素とするバリアメタ
ル(以下、「TaSiN又はHfSiN」と記す)を有
し、該バリアメタルの上部に、膜厚36〜82nmのI
rO2/膜厚22〜66nmのIr(上層/下層)の積
層構造電極が形成されてなる酸化物導電体を用いた多層
構造電極が提供される。
According to the present invention, a multi-layered electrode formed on a semiconductor substrate has a lower Ta electrode.
Or a barrier metal containing Hf, Si, and N as constituent elements (hereinafter, referred to as “TaSiN or HfSiN”), and a 36 to 82 nm-thick I
A multilayer structure electrode using an oxide conductor formed by forming an Ir (upper layer / lower layer) laminated electrode of rO 2 / film thickness of 22 to 66 nm is provided.

【0010】[0010]

【発明の実施の形態】本発明における多層構造電極は、
強誘電体不揮発性メモリ、DRAM、赤外線センサアレ
イ等における強誘電体薄膜の下部電極として用いること
ができるものであり、半導体基板上に形成される。半導
体基板としては、通常上記素子の基板として用いること
ができるものであれば、特に限定されるものではなく、
例えばシリコン基板、GaAs、InGaAs等の化合
物半導体基板等を使用することができる。本発明の多層
構造電極は、半導体基板上に直接形成してもよいし、S
iN、SiO2 等の絶縁膜を介して形成してもよいし、
キャパシタ、トランジスタ又は金属配線等の所望の素子
を形成した上に層間絶縁膜を介して形成してもよい。例
えば、絶縁膜を介して形成する場合には、絶縁膜の膜厚
は500〜2000nm程度が好ましく、所望の素子及
び層間絶縁膜を介して形成する場合には、層間絶縁膜
は、素子と電極との絶縁性を確保することができる十分
な膜厚であることが好ましい。これら絶縁膜等は、公知
の方法、例えばCVD法、スピンコート法等により形成
することができる。この際の成膜温度は、600℃程度
以下であることが好ましい。
BEST MODE FOR CARRYING OUT THE INVENTION A multilayer electrode according to the present invention comprises:
It can be used as a lower electrode of a ferroelectric thin film in a ferroelectric nonvolatile memory, a DRAM, an infrared sensor array, and the like, and is formed on a semiconductor substrate. The semiconductor substrate is not particularly limited as long as it can be used as a substrate of the above-described element.
For example, a silicon substrate, a compound semiconductor substrate of GaAs, InGaAs, or the like can be used. The multilayer structure electrode of the present invention may be formed directly on a semiconductor substrate,
It may be formed via an insulating film such as iN or SiO 2 ,
A desired element such as a capacitor, a transistor, or a metal wiring may be formed over an interlayer insulating film. For example, when formed through an insulating film, the thickness of the insulating film is preferably about 500 to 2000 nm. When formed through a desired element and an interlayer insulating film, the interlayer insulating film is It is preferable that the film thickness is sufficient to ensure the insulating property with respect to. These insulating films and the like can be formed by a known method such as a CVD method and a spin coating method. The film forming temperature at this time is preferably about 600 ° C. or less.

【0011】本発明の多層構造電極は、バリアメタルと
してTaSiN又はHfSiNのいずれかを用いた電極
であり、具体的には、IrO2/Ir/TaSiN又は
IrO2/Ir/HfSiNの多層構造電極である。バ
リアメタルであるTaSiN又はHfSiN膜は、例え
ば100〜500nm程度の膜厚で、公知の方法、例え
ばRFマグネトロンスパッタ法、DCマグネトロンスパ
ッタ法、真空蒸着法、電子ビーム蒸着法等種々の方法で
形成することができる。ここで、TaSiN又はHfS
iN膜をバリアメタルとして用いるには、一般にアモル
ファス構造が望ましいため、その組成比は自由に変更す
ることができる。
The multi-layer electrode of the present invention is an electrode using either TaSiN or HfSiN as a barrier metal, and more specifically, a multi-layer electrode of IrO 2 / Ir / TaSiN or IrO 2 / Ir / HfSiN. is there. The TaSiN or HfSiN film serving as a barrier metal is formed with a thickness of, for example, about 100 to 500 nm by various methods such as a known method, for example, an RF magnetron sputtering method, a DC magnetron sputtering method, a vacuum evaporation method, and an electron beam evaporation method. be able to. Here, TaSiN or HfS
In order to use an iN film as a barrier metal, an amorphous structure is generally desirable, so that the composition ratio can be freely changed.

【0012】また、バリアメタル直上に形成される積層
構造電極を構成するIr膜は、公知の方法、例えば、R
Fマグネトロンスパッタ法、DCマグネトロンスパッタ
法、真空蒸着法、電子ビーム蒸着法等種々の方法で、後
の工程におけるIrO2 層の形成に際して、下部のバリ
アメタルの酸化を抑止するのに十分な膜厚で形成するこ
とが好ましい。この膜厚は、例えば、22nm以上があ
げられる。また、Ir層は(111)面に配向して形成
されることが好ましい。具体的には、RFマグネトロン
スパッタ法の場合は、RFパワー80〜200W程度、
基板温度を200〜270℃程度に保持しながら、スパ
ッタガスとしてAr、N等の不活性ガスを用いて成膜す
る方法があげられる。
Further, the Ir film constituting the laminated electrode formed directly on the barrier metal can be formed by a known method, for example, R
A film thickness sufficient to suppress oxidation of the lower barrier metal when forming an IrO 2 layer in a later step by various methods such as an F magnetron sputtering method, a DC magnetron sputtering method, a vacuum evaporation method, and an electron beam evaporation method. It is preferable to form with. This film thickness is, for example, 22 nm or more. Further, the Ir layer is preferably formed to be oriented in the (111) plane. Specifically, in the case of the RF magnetron sputtering method, the RF power is about 80 to 200 W,
A method of forming a film by using an inert gas such as Ar or N as a sputtering gas while maintaining the substrate temperature at about 200 to 270 ° C.

【0013】また、Ir膜上に形成されるIrO2
は、公知の方法、例えば、上述と同様の方法で、後述す
る積層構造電極の高温アニールに際して下部のバリアメ
タルの酸化を抑止するに十分な膜厚で形成することが好
ましい。この膜厚は、例えば、36nm以上があげられ
る。但し、IrO2 /Ir膜の総膜厚が150nm以
下、さらに60nm以上で形成されることが好ましい。
また、IrO2 層は(100)面に配向して形成される
ことが好ましい。具体的には、RFマグネトロンスパッ
タ法の場合は、RFパワー80〜200W程度、基板温
度を200〜270℃程度に保持しながら、スパッタガ
スとしてAr、N等の不活性ガスに酸素ガスを1:10
〜10:1程度の割合で混合したガスを用いて成膜する
方法があげられる。
The IrO 2 film formed on the Ir film is sufficiently formed by a known method, for example, the same method as described above, to suppress the oxidation of the lower barrier metal during the high-temperature annealing of the laminated electrode described below. It is preferable to form it with a small thickness. This film thickness is, for example, 36 nm or more. However, the total thickness of the IrO 2 / Ir film is preferably 150 nm or less, more preferably 60 nm or more.
Further, the IrO 2 layer is preferably formed to be oriented in the (100) plane. Specifically, in the case of the RF magnetron sputtering method, while maintaining the RF power at about 80 to 200 W and the substrate temperature at about 200 to 270 ° C., an oxygen gas is added to an inert gas such as Ar or N as a sputtering gas at a ratio of 1: 10
A method of forming a film using a gas mixed at a ratio of about 10: 1 is exemplified.

【0014】このような多層積層電極により、600℃
以上の酸素雰囲気中での熱処理プロセスに十分な耐性を
有する電極構造を実現できる。また、IrO2では(1
00)面、Irでは(111)面に配向した結晶薄膜を
用いることにより、微結晶粒からなる緻密な表面平坦性
に優れた積層電極構造を実現することができる。このよ
うな表面平坦性、緻密性を備えた配向性の多層積層電極
は、強誘電体薄膜の下地電極として適するだけでなく、
電極自体のシート抵抗までも制御できることとなり、種
々の素子の電極として使用することができる。以下に、
本発明の酸化物導電体を用いた多層構造電極について説
明する。
With such a multilayer laminated electrode, a temperature of 600 ° C.
An electrode structure having sufficient resistance to the heat treatment process in the above oxygen atmosphere can be realized. In IrO 2 , (1
By using a crystal thin film oriented in the (00) plane and the (111) plane, a laminated electrode structure composed of fine crystal grains and having excellent surface flatness can be realized. Such surface flatness, a multilayer laminated electrode of orientation with denseness is not only suitable as a base electrode of a ferroelectric thin film,
Since the sheet resistance of the electrode itself can be controlled, it can be used as an electrode of various elements. less than,
The multi-layered electrode using the oxide conductor of the present invention will be described.

【0015】実施例1 本発明の多層構造電極は、図1に示したように、単結晶
Si(100)ウエハ1の表面に600nmの厚さのS
iO2膜2、その上にバリアメタル3としてTaSiN
(100nm)、さらにその上に電極層4としてIrO
2(230nm)、Ir(130nm)、IrO2(82
nm)/Ir(66nm)のいずれかが形成されて構成
されている。なお、本実施例のTaSiNの組成はTa
5 SiN4 であった。
Embodiment 1 As shown in FIG. 1, a multi-layered electrode of the present invention has a 600 nm thick S on a surface of a single crystal Si (100) wafer 1.
iO 2 film 2, on which TaSiN is used as barrier metal 3
(100 nm), and IrO as an electrode layer 4 thereon.
2 (230 nm), Ir (130 nm), IrO 2 (82
nm) / Ir (66 nm). The composition of TaSiN in this example is Ta
5 SiN 4 .

【0016】上記多層構造電極は、以下のように形成す
る。まず、Siウェハ1表面に、熱酸化法によりSiO
2 膜2を形成した。次いでこのSiO2 膜2上にTaS
iN膜をスパッタ法により形成した。さらに、このTa
SiN膜上に、3種類の内のいずれかの電極層4をRF
マグネトロンスパッタ法により形成した。成膜条件とし
ては、RFパワー100W、基板温度250℃、ガス圧
1Paとして、Ir成膜はArガス、IrO2はAr/
2=1/1混合ガスをスパッタガスとした。また、I
rO2/Ir積層構造は、上記の条件でIrを成膜した
後に引き続きIrO2を成膜して形成した。各電極表面
のモフォロジーはSEM観察の結果、緻密で平滑な表面
性を有していた。これは成膜温度が250℃と比較的低
温であるため、成膜中の粒成長が抑制されたからである
と考えられる。
The above-mentioned multilayer structure electrode is formed as follows. First, on the surface of the Si wafer 1, SiO
Two films 2 were formed. Next, TaS is formed on the SiO 2 film 2.
An iN film was formed by a sputtering method. Furthermore, this Ta
On the SiN film, one of the three types of electrode layers 4 is RF
It was formed by magnetron sputtering. The film formation conditions were as follows: RF power 100 W, substrate temperature 250 ° C., gas pressure 1 Pa, Ir film formation was Ar gas, and IrO 2 was Ar /
O 2 = 1/1 mixed gas was used as a sputtering gas. Also, I
The rO 2 / Ir laminated structure was formed by forming Ir under the above conditions and then forming IrO 2 . The morphology of each electrode surface was dense and smooth as a result of SEM observation. This is presumably because the film formation temperature was relatively low at 250 ° C., so that grain growth during film formation was suppressed.

【0017】続いて、酸素中での高温熱処理耐性を調べ
るために、上記の3種類の電極を1気圧の酸素中で62
5℃、10分間のアニールを施した。その結果、IrO
2/TaSiN構造ではIrO2の剥離が認められた。こ
れはIrO2成膜時のO2プラズマ及びその後に酸素中で
の高温アニールによりTaSiN表面が酸化された結
果、その界面でのストレスを解放するために剥離が発生
したと考えられる。
Subsequently, in order to examine the resistance to high-temperature heat treatment in oxygen, the above three kinds of electrodes were subjected to 62-hour pressure in 1 atmosphere of oxygen.
Annealing was performed at 5 ° C. for 10 minutes. As a result, IrO
In the 2 / TaSiN structure, peeling of IrO 2 was observed. This is presumably because the TaSiN surface was oxidized by the O 2 plasma during the IrO 2 film formation and subsequently by the high-temperature annealing in oxygen, and as a result, separation occurred to release the stress at the interface.

【0018】一方、成膜時にO2プラズマを用いないI
r/TaSiN構造では、成膜直後に平坦であった電極
表面が酸素中での高温アニール後では凹凸が発生し表面
平坦性が損なわれた。この原因を調べるためにアニール
前後でのXRDパターンの変化を測定した。成膜直後に
は(111)配向したIr膜であるが、アニールによっ
て酸化物IrO2が発生している。また、Ir(11
1)反射のピーク強度が約40%増加しており結晶化も
促進されていることが分かった。これらの酸化及び結晶
化(粒成長)の結果、Ir電極表面の凹凸が発生したも
のと考えられる。
On the other hand, when the O 2 plasma is not used during film formation,
In the case of the r / TaSiN structure, the surface of the electrode that was flat immediately after film formation became uneven after high-temperature annealing in oxygen, and the surface flatness was impaired. To investigate the cause, the change in the XRD pattern before and after annealing was measured. Immediately after the film formation, the Ir film is (111) -oriented, but the oxide IrO 2 is generated by the annealing. In addition, Ir (11
1) It was found that the peak intensity of reflection increased by about 40%, and crystallization was promoted. It is considered that as a result of these oxidation and crystallization (grain growth), irregularities on the Ir electrode surface occurred.

【0019】以上の結果、IrO2/TaSiN構造及
びIr/TaSiN構造では、いずれも膜形成時あるい
は形成後の酸素中高温アニール処理での酸化反応等によ
り膜の剥離あるいは電極表面の凹凸が発生し、酸化物強
誘電体薄膜を形成するために下部電極としては不適であ
る。次に、IrO2/Ir/TaSiN構造について見
ると、図2に示す様に酸素中高温アニール後も剥離やヒ
ロック等の発生は認められず、更に電極表面の平坦性も
アニール前と同等に保たれた緻密な膜となっている。ま
た、XRD測定からもアニール前後で回折パターンの変
化は見られず、IrO2(100)/Ir(111)の
配向膜構造が得られていることが分かった。
As a result, in the IrO 2 / TaSiN structure and the Ir / TaSiN structure, peeling of the film or unevenness of the electrode surface occurs due to an oxidation reaction or the like in the high-temperature annealing treatment in oxygen after the film is formed. However, it is not suitable as a lower electrode for forming an oxide ferroelectric thin film. Next, looking at the IrO 2 / Ir / TaSiN structure, as shown in FIG. 2, no peeling or hillocks were observed even after the high-temperature annealing in oxygen, and the flatness of the electrode surface was maintained at the same level as before the annealing. It is a dense and thin film. Also, from the XRD measurement, no change in the diffraction pattern was observed before and after annealing, indicating that an IrO 2 (100) / Ir (111) alignment film structure was obtained.

【0020】これらの結果は、TaSiN上にIr膜を
形成することで、その上にIrO2層の成膜時に直接T
aSiN表面を酸素プラズマにさらさずにすむこと、さ
らにはIr表面がわずかに酸化しその酸化層IrO2
TiSiN界面の酸化を抑制しかつ成膜温度が250℃
と低いためにIr表面の平坦性が損なわれないこと、最
上部に形成したIrO2層がアニール時の酸素拡散によ
る下部のIr/TaSiNの酸化を抑制していること等
によって得られたものと考えられる。
These results are obtained by forming an Ir film on TaSiN, and directly forming an IrO 2 layer on the Ir film.
The aSiN surface does not need to be exposed to oxygen plasma. Further, the Ir surface is slightly oxidized, and the oxide layer IrO 2 suppresses the oxidation of the TiSiN interface, and the film forming temperature is 250 ° C.
And that the IrO 2 layer formed on the uppermost portion suppresses the oxidation of the lower Ir / TaSiN due to oxygen diffusion during annealing. Conceivable.

【0021】このIrO2/Ir/TaSiN構造での
シート抵抗を測定したところ、成膜直後では約1.2Ω
/□が得られ、アニール後も有意な変化はなかった。従
来用いられているPt(100nm)/TiN/Ti構
造でのシート抵抗は約1Ω/□であり、ほぼ同程度のシ
ート抵抗が得られていることから、十分に電極として使
用できることが確認された。
When the sheet resistance of the IrO 2 / Ir / TaSiN structure was measured, it was found to be about 1.2 Ω immediately after the film formation.
/ □ was obtained, and there was no significant change after annealing. The sheet resistance of the conventionally used Pt (100 nm) / TiN / Ti structure is about 1 Ω / □, and the sheet resistance is almost the same, confirming that the sheet can be sufficiently used as an electrode. .

【0022】また、バリアメタルにHfSiNを用いた
IrO2/Ir/HfSiN構造においても同様に剥離
やヒロックのない表面平坦で緻密な電極を作製でき、酸
素中での高温アニール耐性があることが確認された。
Similarly, in the IrO 2 / Ir / HfSiN structure using HfSiN as the barrier metal, a dense electrode having a flat surface without peeling or hillocks can be produced, and it has been confirmed that it has high temperature annealing resistance in oxygen. Was done.

【0023】以上述べたように、半導体基板上に形成さ
れる電極構造において、その下部構造がTaSiN、H
fSiNのいずれか一つから選択された構造であり、そ
の上部に結晶性の(100)配向のIrO2と(11
1)配向のIrからなるIrO2/Ir積層構造を有す
る多層電極は、600℃以上の酸素雰囲気中でのアニー
ルプロセス耐性を有する。すなわち、Ir層がIrO2
層の形成に際して下部構造であるTaSiN、HfSi
Nの酸化を抑止する厚さ以上の膜厚を有し、またIrO
2層が酸素中での高温アニールプロセスによる下部構造
であるバリアメタルTaSiN、HfSiNの酸化を抑
止する厚さ以上の膜厚を有することにより、上記プロセ
ス耐性を有する電極となることが示された。また、この
電極は表面平坦性、緻密性を備えており、シート抵抗も
Pt/TiN/Ti構造のそれと同程度の優れた電気的
特性を持つ。
As described above, in the electrode structure formed on the semiconductor substrate, the lower structure is TaSiN, H
The structure is selected from any one of fSiN, and the crystalline (100) -oriented IrO 2 and (11
1) A multilayer electrode having an IrO 2 / Ir multilayer structure composed of oriented Ir has an annealing process resistance in an oxygen atmosphere at 600 ° C. or higher. That is, the Ir layer is made of IrO 2
TaSiN, HfSi which is a lower structure when forming a layer
A film thickness not less than the thickness for suppressing oxidation of N, and
It was shown that an electrode having the above process resistance was obtained when the two layers had a thickness not less than the thickness for suppressing the oxidation of the barrier metals TaSiN and HfSiN, which are the lower structures by the high-temperature annealing process in oxygen. Further, this electrode has surface flatness and denseness, and has excellent sheet resistance similar to that of the Pt / TiN / Ti structure.

【0024】実施例2 基板及び成膜条件は実施例1と同様のものを用いて、各
層厚の異なるIrO2/Ir/TaSiN構造のサンプ
ルを作製した。ただし、(100)配向のIrO2層の
膜厚を36〜82nm、(111)配向のIr層の膜厚
を15〜66nmの範囲で作製した。ここで、膜厚はス
パッタ成膜時間を変化させることで制御した。各々膜厚
の異なる電極構造について、実施例1と同様のアニール
を行った。
Example 2 Samples having IrO 2 / Ir / TaSiN structures having different thicknesses were prepared by using the same substrate and the same film forming conditions as in Example 1. However, the thickness of the (100) -oriented IrO 2 layer was in the range of 36 to 82 nm, and the thickness of the (111) -oriented Ir layer was in the range of 15 to 66 nm. Here, the film thickness was controlled by changing the sputter deposition time. Annealing similar to that of Example 1 was performed for the electrode structures having different thicknesses.

【0025】Ir層の膜厚が15nmと最も薄いIrO
2(82nm)/Ir(15nm)/TaSiN構造で
はアニール後にヒロックが観察された。これは、実施例
1で示したIrO2/TaSiN構造でIrO2が剥離し
たのと同じ原因であると考えられる。すなわち、Ir層
の膜厚が非常に薄いために完全にTaSiN表面を覆い
きれていない、あるいはその後のIrO2形成時の酸素
プラズマによる酸化を抑止できない程度に膜厚が薄いた
めにTaSiNが酸化される箇所が存在し、そこでのス
トレスがヒロックを発生させたと考えられる。
The thickness of the Ir layer is 15 nm, the thinnest IrO
Hillocks were observed after annealing in the 2 (82 nm) / Ir (15 nm) / TaSiN structure. This is considered to be the same cause as the separation of IrO 2 in the IrO 2 / TaSiN structure shown in the first embodiment. That is, the TaSiN surface is not completely covered because the thickness of the Ir layer is very thin, or TaSiN is oxidized because it is so thin that the oxidation by oxygen plasma during the formation of IrO 2 cannot be suppressed. It is considered that there was a place where the stress caused hillocks.

【0026】その他のサンプルについては全てアニール
後においても剥離、ヒロック等は見られず、アニール耐
性のあることが確認できた。作製したサンプルの中で最
も膜厚の薄いIrO2(36nm)/Ir(22nm)
/TaSiN構造のアニール後の断面をSEM観察した
ところ、IrO2/Irの膜厚が60nm程度と薄い場
合においても平坦性が保たれており、TaSiN部分も
反応や拡散等は見られなかった。
No peeling or hillocks were observed in any of the other samples even after annealing, confirming that the samples had annealing resistance. IrO 2 (36 nm) / Ir (22 nm) with the thinnest film thickness among the fabricated samples
When the cross section of the / TaSiN structure after annealing was observed by SEM, the flatness was maintained even when the film thickness of IrO 2 / Ir was as thin as about 60 nm, and no reaction or diffusion was observed in the TaSiN portion.

【0027】すなわち、(100)に配向したIrO2
及び(111)配向したIrからなるIrO2/Ir積
層電極構造を用いることで、非常に緻密で60nm程度
の薄い薄膜で酸化物強誘電体薄膜の成膜プロセス耐性を
実現できた。更に、作製したサンプルについてシート抵
抗を測定したところ、図3に示すようにIrO2/Ir
積層電極におけるIr層及びIrO2層の膜厚を変える
ことで電極全体のシート抵抗を1.2〜2.8Ω/□の
範囲で制御できることが分かった。
That is, IrO 2 oriented to (100)
By using the IrO 2 / Ir laminated electrode structure made of Ir with (111) orientation, the film formation process resistance of the oxide ferroelectric thin film can be realized with a very dense and thin film of about 60 nm. Further, when the sheet resistance of the fabricated sample was measured, as shown in FIG. 3, IrO 2 / Ir
It was found that the sheet resistance of the entire electrode could be controlled in the range of 1.2 to 2.8 Ω / □ by changing the thickness of the Ir layer and the IrO 2 layer in the laminated electrode.

【0028】また、バリアメタルとしてHfSiNを用
いたIrO2/Ir/HfSiN構造においても、少な
くともIrO2/Ir電極の膜厚が約60nm〜150
nmの範囲で同様に剥離、ヒロックのない平坦で緻密な
電極構造を作製でき、かつ酸素中での高温アニール耐性
が得られることを確認できた。以上で述べたように、本
発明のIrO2/Ir電極構造を用いることで平坦性、
緻密性に優れた電極を作製できる。その結果、Ir層の
膜厚が22nm以上でかつIrO2層の膜厚が36nm
以上の条件においてIrO2/Ir電極の膜厚が約60
〜150nmと薄いプロセス耐性に優れた電極が作製で
きた。さらに、シート抵抗が各層の膜厚を変えることに
より1.1〜2.8Ω/□まで制御できた。
In the IrO 2 / Ir / HfSiN structure using HfSiN as a barrier metal, at least the thickness of the IrO 2 / Ir electrode is about 60 nm to 150 nm.
Similarly, it was confirmed that a flat and dense electrode structure without peeling and hillocks could be produced in the range of nm, and high-temperature annealing resistance in oxygen could be obtained. As described above, by using the IrO 2 / Ir electrode structure of the present invention, flatness,
An electrode having excellent denseness can be manufactured. As a result, the thickness of the Ir layer was 22 nm or more, and the thickness of the IrO 2 layer was 36 nm.
Under the above conditions, the film thickness of the IrO 2 / Ir electrode is about 60
An electrode excellent in process resistance as thin as 150 nm was produced. Further, the sheet resistance could be controlled from 1.1 to 2.8 Ω / □ by changing the thickness of each layer.

【0029】[0029]

【発明の効果】本発明によれば、STC構造を用いた強
誘電体メモリやDRAMの実用化に不可欠なプロセス耐
性に優れた下部電極が再現性良く作成することができ
る。特に、IrO2層及びIr層が結晶薄膜であり、I
rO2層は(100)面に配向し、Ir層は(111)
面に配向してなる場合には、その電極は平坦性、緻密性
にも優れるため、微細加工プロセス等への適用性も高く
なる。
According to the present invention, a lower electrode having excellent process resistance, which is indispensable for practical use of a ferroelectric memory or a DRAM using an STC structure, can be formed with good reproducibility. In particular, the IrO 2 layer and the Ir layer are crystalline thin films,
The rO 2 layer is oriented in the (100) plane, and the Ir layer is oriented in the (111) plane.
When the electrode is oriented in a plane, the electrode is excellent in flatness and denseness, so that applicability to a fine processing process or the like is also increased.

【0030】さらに、IrO2/Ir層の膜厚が150
nm以下である場合には、積層構造電極の各層の膜厚を
変えることでシート抵抗等の電気特性の制御も可能とな
る。このように、本発明の多層構造電極においては、例
えば、強誘電体膜の形成プロセスにおいて、下部の半導
体との反応、相互拡散を防止することができ、信頼性の
高い、良好な特性を有する素子を得ることが可能とな
る。
Further, the thickness of the IrO 2 / Ir layer is 150
When the thickness is not more than nm, electric characteristics such as sheet resistance can be controlled by changing the film thickness of each layer of the laminated structure electrode. As described above, in the multilayer structure electrode of the present invention, for example, in the process of forming a ferroelectric film, it is possible to prevent a reaction with a lower semiconductor and interdiffusion, and to have high reliability and good characteristics. An element can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の酸化物導電体を用いた多層構造電極の
実施例を示す概略断面図である。
FIG. 1 is a schematic cross-sectional view showing an embodiment of a multi-layered electrode using an oxide conductor according to the present invention.

【図2】本発明の多層構造電極のIrO2/Ir/Ta
SiN構造のアニール後の表面及び断面のSEM写真で
ある。
FIG. 2 shows IrO 2 / Ir / Ta of a multilayer structure electrode of the present invention.
It is a SEM photograph of the surface and cross section of the SiN structure after annealing.

【図3】本発明の多層構造電極のIrO2/Ir/Ta
SiN構造のシート抵抗を示すグラフである。
FIG. 3 shows IrO 2 / Ir / Ta of a multilayer electrode according to the present invention.
4 is a graph showing a sheet resistance of a SiN structure.

【符号の説明】[Explanation of symbols]

1 単結晶Si基板 2 SiO2膜 3 バリアメタル 4 電極層Single crystal Si substrate 2 SiO 2 film 3 barrier metal 4 electrode layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI H01L 29/788 29/792 (72)発明者 松永 宏典 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (56)参考文献 特開 平8−116032(JP,A) 特開 平8−236479(JP,A) 特開 平10−173154(JP,A) 特開 平10−150155(JP,A) 特開 平9−82666(JP,A) 特開 平9−8253(JP,A) 特開 平8−330513(JP,A) 特開 平8−306722(JP,A) 特開 平8−277196(JP,A) 特開 平8−264665(JP,A) 特開 平8−107153(JP,A) 特開 平8−51165(JP,A) 特開 平7−302888(JP,A) 特開 平7−245237(JP,A) 特開 平7−99290(JP,A) 特開 平7−74177(JP,A) 特開 平6−338502(JP,A) 特開 平6−326249(JP,A) 特開 昭62−89355(JP,A) 特開 平8−260148(JP,A) 特表 平11−510317(JP,A) Gbit−DRAM用電極,半導体・ 集積回路技術第51回シンポジウム講演論 文集,日本,電気化学会電子材料委員 会,1996年12月5日,54−59 Jpn.J.Appl.Phys., Vol.33,Part1,No.9B, 5207−5210 (58)調査した分野(Int.Cl.7,DB名) H01L 21/28 301 H01L 21/822 H01L 21/8247 H01L 27/04 H01L 27/105 H01L 29/788 H01L 29/792 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification code FI H01L 29/788 29/792 (72) Inventor Hironori Matsunaga 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-8-116032 (JP, A) JP-A-8-236479 (JP, A) JP-A-10-173154 (JP, A) JP-A-10-150155 (JP, A) JP-A-9 -82666 (JP, A) JP-A-9-8253 (JP, A) JP-A-8-330513 (JP, A) JP-A-8-306722 (JP, A) JP-A-8-277196 (JP, A) JP-A-8-264665 (JP, A) JP-A-8-107153 (JP, A) JP-A-8-51165 (JP, A) JP-A-7-302888 (JP, A) 245237 (JP, A) JP-A-7-99290 (JP, A) JP-A-7-74177 (JP, A) JP-A-6-338249 (JP, A) JP-A-6-89355 (JP, A) JP-A-8-260148 (JP, A) JP-A-11-510317 (JP, A) A) Electrodes for Gbit-DRAM, Semiconductor / Integrated Circuit Technology 51st Symposium Proceedings, Electronic Materials Committee of the Institute of Electrical Chemistry, Japan, December 5, 1996, 54-59 Jpn. J. Appl. Phys. , Vol. 33, Part 1, No. 9B, 5207-5210 (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/28 301 H01L 21/822 H01L 21/8247 H01L 27/04 H01L 27/105 H01L 29/788 H01L 29/792

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に形成される多層構造電極
において、下部にTa又はHf、およびSi、Nを構成
元素とするバリアメタルを有し、該バリアメタルの上部
に、膜厚36〜82nmのIrO2/膜厚22〜66n
mのIr(上層/下層)の積層構造電極が形成されてな
ることを特徴とする酸化物導電体を用いた多層構造電
極。
1. A multilayer electrode formed on a semiconductor substrate, comprising a barrier metal containing Ta or Hf, Si, and N as constituent elements in a lower portion, and a film thickness of 36 to 82 nm on an upper portion of the barrier metal. IrO 2 / film thickness 22-66n
A multilayered electrode using an oxide conductor, wherein a laminated electrode of m (upper layer / lower layer) is formed.
【請求項2】 IrO2層及びIr層が結晶薄膜であ
り、IrO2層は(100)面に配向し、Ir層は(1
11)面に配向してなる請求項1記載の多層構造電極。
2. The IrO 2 layer and the Ir layer are crystalline thin films, the IrO 2 layer is oriented in the (100) plane, and the Ir layer is (1).
11) The multilayer structure electrode according to claim 1, which is oriented in a plane.
JP05848097A 1997-02-25 1997-02-25 Multilayer structure electrode using oxide conductor Expired - Fee Related JP3299909B2 (en)

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* Cited by examiner, † Cited by third party
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010013637A1 (en) * 1999-03-05 2001-08-16 Fengyan Zhang Iridium conductive electrode/barrier structure and method for same
US6236113B1 (en) * 1999-03-05 2001-05-22 Sharp Laboratories Of America, Inc. Iridium composite barrier structure and method for same
JP3681632B2 (en) 2000-11-06 2005-08-10 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
US6794705B2 (en) 2000-12-28 2004-09-21 Infineon Technologies Ag Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials
KR100709033B1 (en) 2005-08-06 2007-04-18 주식회사 아이피에스 Method for depositing HfSiN thin film on wafer
KR100748309B1 (en) 2006-02-10 2007-08-09 삼성에스디아이 주식회사 Organic light-emitting display device and method for fabricating the same
JP4983172B2 (en) 2006-09-12 2012-07-25 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6289355A (en) * 1985-10-16 1987-04-23 Hitachi Ltd Semiconductor device
US5536947A (en) * 1991-01-18 1996-07-16 Energy Conversion Devices, Inc. Electrically erasable, directly overwritable, multibit single cell memory element and arrays fabricated therefrom
JP2874512B2 (en) * 1993-05-13 1999-03-24 日本電気株式会社 Thin film capacitor and method of manufacturing the same
JP2586292B2 (en) * 1993-05-31 1997-02-26 日本電気株式会社 Method for manufacturing semiconductor device
US5407855A (en) * 1993-06-07 1995-04-18 Motorola, Inc. Process for forming a semiconductor device having a reducing/oxidizing conductive material
JPH0774177A (en) * 1993-08-31 1995-03-17 Sony Corp Method and equipment for manufacturing semiconductor device
JP3461398B2 (en) * 1994-01-13 2003-10-27 ローム株式会社 Dielectric capacitor and method of manufacturing the same
JP3247023B2 (en) * 1994-01-13 2002-01-15 ローム株式会社 Dielectric capacitor, non-volatile memory and method of manufacturing the same
JP3197782B2 (en) * 1994-04-29 2001-08-13 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Semiconductor integrated circuit capacitor and its electrode structure
US5585300A (en) * 1994-08-01 1996-12-17 Texas Instruments Incorporated Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
JP3263941B2 (en) * 1994-10-05 2002-03-11 ソニー株式会社 Method for manufacturing semiconductor device
US5576579A (en) * 1995-01-12 1996-11-19 International Business Machines Corporation Tasin oxygen diffusion barrier in multilayer structures
JP3279453B2 (en) * 1995-03-20 2002-04-30 シャープ株式会社 Non-volatile random access memory
JP3130757B2 (en) * 1995-03-27 2001-01-31 富士通株式会社 Method for forming thin film for capacitor electrode, semiconductor device and method for manufacturing the same
JP3672115B2 (en) * 1995-09-19 2005-07-13 富士通株式会社 Thin film forming method and semiconductor device manufacturing method
JPH08277196A (en) * 1995-03-31 1996-10-22 Tdk Corp Ferroelectric thin film, its production, semiconductor non-volatile memory element, ferroelectric gate-type fet element and sensor
JP2956582B2 (en) * 1995-04-19 1999-10-04 日本電気株式会社 Thin film capacitor and method of manufacturing the same
JP3526651B2 (en) * 1995-04-28 2004-05-17 ローム株式会社 Semiconductor device and wiring method
KR0147640B1 (en) * 1995-05-30 1998-08-01 김광호 Capacitor of semiconductor device & its fabrication method
KR100190111B1 (en) * 1996-11-13 1999-06-01 윤종용 Fabricating method for capacitor in semiconductor device
US6130124A (en) * 1996-12-04 2000-10-10 Samsung Electronics Co., Ltd. Methods of forming capacitor electrodes having reduced susceptibility to oxidation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Gbit−DRAM用電極,半導体・集積回路技術第51回シンポジウム講演論文集,日本,電気化学会電子材料委員会,1996年12月5日,54−59
Jpn.J.Appl.Phys.,Vol.33,Part1,No.9B,5207−5210

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8405188B2 (en) 2007-02-28 2013-03-26 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing the semiconductor device
US8664011B2 (en) 2007-02-28 2014-03-04 Fujitsu Limited Semiconductor device and method of manufacturing the semiconductor device
US8390045B2 (en) 2007-03-20 2013-03-05 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing same
US8609440B2 (en) 2007-03-20 2013-12-17 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing same
US8629487B2 (en) 2007-03-20 2014-01-14 Fujitsu Semiconductor Limited Semiconductor device and method of manufacturing same

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