JP3197782B2 - Semiconductor integrated circuit capacitor and its electrode structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor used for a memory, and more particularly to a semiconductor-side electrode structure of an oxide type high dielectric capacitor suitable for a dynamic random access memory (DRAM).

[0002]

2. Description of the Related Art Dynamic random access memory (DR)
AM) to high densities of 1 gigabit or higher, high dielectric constant materials are needed to build capacitors of sufficient size in the reduced surface area on integrated circuit chips. is necessary. 1 Gigabit DR
Materials with a sufficiently high dielectric constant required for AM include:
Composite oxide type materials, especially Ba _x Sr _(1-x) TiO ₃ and P
_{bZr X T 1-X O 3} (PZT) ferroelectric or paraelectric material, such as seems to be. These materials must be deposited on the electrodes in electrical contact with the silicon or its alloy. The high dielectric constant material can be deposited by various methods, but many are heated to a temperature of 500 ° C. or more at a certain stage. Materials may be exposed to higher temperatures during device fabrication.

In processing the capacitor structure, the conductivity of the electrodes must be maintained and the formation of a silicon oxide layer in series with the high dielectric capacitor must be prevented. In order to maintain the structure and properties of the high-k material, the interaction between the electrode and the high-k material must also be avoided.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated circuit capacitor, particularly an integrated circuit capacitor suitable for use in a dynamic random access memory (DRAM).

Another object of the invention is to provide an electrode wherein the third layer acts as a barrier to the titanate component, preventing the titanate component from interacting with the metal oxide forming the second layer. It is to provide a structure, for example, a bottom electrode of the capacitor.

Another object of the present invention is to provide a semiconductor in a high dielectric constant material that is conductive and prevents diffusion of oxygen into the underlying semiconductor, eg, silicon, and forms a low dielectric material at the dielectric interface when combined. Prevent the diffusion of atoms such as silicon,
It is to provide a three-layer electrode structure.

[0007]

According to the present invention, there is provided a semiconductor device formed from a group consisting of Ru, Ir, Re, Rh, Os, Pd, and alloys thereof formed in ohmic contact with the semiconductor region. A first layer of a selected metal;
R formed on the layer in ohmic contact with the first layer
a second metal oxide selected from the group consisting of oxides of u, Ir, Re, Rh, Os, Pd and mixtures thereof.
Layer and a high dielectric constant material such as barium strontium titanate or lead zirconium titanate (PZT) formed thereon, Pt, Au, Ru, Ir, Re, Rh, O
and a third layer of a metal selected from the group consisting of s, Pd and alloys thereof, wherein a single-sided electrode structure of a capacitor of a high dielectric constant material is provided that contacts a semiconductor region on a substrate having an exposed surface. You.

The present invention further comprises a capacitor and the above-mentioned electrode structure, and further comprises a composite oxide type material,
aTiO ₃ , SrTiO ₃ , Ba _x Sr _(1-x) TiO ₃ , P
LT, PLZT, or PbZr _X T _{1 -X} O ₃ (PZT)
For producing a capacitor including a fourth layer of a high-permittivity material selected from the group consisting of ferroelectric materials or paraelectric materials, and a fifth layer of a conductive material formed on the fourth layer I will provide a.

[0009] These and other features, objects, and advantages of the present invention will become apparent from the following detailed description of the invention when read in conjunction with the drawings.

[0010]

1 shows a memory array 9 including capacitors 10 and 11 for storing charge. FIG. 2 is an enlarged view showing a cross-sectional view of a part of the capacitor 10 and the semiconductor region 26 of FIG. Capacitors 10 and 11 are formed on upper surface 22 above semiconductor regions 26 and 28, respectively. Semiconductor regions 26 and 2
8 serves to electrically couple the lower electrode structures 14 of the capacitors 10 and 11 with the doped regions 38 and 40 in the substrate 12. Semiconductor regions 26 and 28
May be, for example, silicon, germanium, gallium, arsenic and their alloys. Substrate 12 may be, for example, a semiconductor such as silicon, germanium, gallium, arsenic, and alloys thereof. Capacitors 10 and 11 each include a lower electrode structure 14, a dielectric layer 16 of a high dielectric constant material such as barium titanate, lead zirconium titanate (PZT), and an upper electrode 18 of a conductive material such as aluminum, platinum and the like. And may be included.

The substrate 12 can have a dielectric layer 20 formed on a top surface 21. The dielectric layer 20 of, for example, silicon oxide has an upper surface 22. Opening, via, or groove 2
4 and 25 are formed on the upper surface 22, penetrating through the layer 20 or into the upper surface 21 of the substrate 12. Closures, vias, or trenches 24 and 25 are provided, for example, to mask layer 20 and provide reactive ion etching (RI
E). Grooves 24 and 25 are filled with doped silicon or a doped silicon alloy such as silicon-germanium or, for example, polycrystalline silicide to form semiconductor regions 26 and 2.
8 is formed. Semiconductor regions 26 and 28 have upper surfaces 27 and 2 which are coplanar with upper surface 22 of dielectric layer 20, respectively.
9 The coplanar top surfaces 22, 27, 29 can be formed by chemical mechanical polishing (CMP). Semiconductor region 26
And 28 form an exposed surface for later making electrical contact with lower electrode structure 14 of capacitors 10 and 11, respectively.

As shown in FIG. 2, the lower electrode structure 14 of the capacitors 10 and 11 includes three layers. That is,
Upper surface 27 of semiconductor region 26 and upper surface 22 of dielectric layer 20
A first layer 31, a second layer 32, and a third layer 33 formed on top of each other.

The first layer 31 includes the semiconductor region 26 and the dielectric layer 2.
A metal selected from the group consisting of Ru, Ir, Re, Rh, Os, Pd, and their alloys formed on O.sub.0 and in ohmic contact with the semiconductor region 26 may be used. First
Layer 31 can be formed by sputter deposition in an oxygen-free plasma, such as in a pure argon atmosphere, or by chemical vapor deposition in an oxygen-free atmosphere or environment.

The second layer 32 is formed on the first layer 31 and the dielectric layer 20 so as to make ohmic contact with the first layer 31, and is composed of Ru, Ir, Re, Rh, Os, Pd and the like. A metal oxide selected from the group consisting of alloy oxides may be used. The second layer 32 may be formed by sputter deposition or reactive sputtering of the selected metal target in an oxygen-containing plasma, or by reactive deposition of the selected metal target in oxygen, or in an oxygen atmosphere or environment. By chemical vapor deposition from a suitable precursor.

The third layer 33 is formed on the second layer 32 and the dielectric layer 20 so as to make ohmic contact with the second layer 32.
It may be a metal selected from the group consisting of t, Au, Ru, Ir, Re, Rh, Os, Pd and alloys thereof. The third layer 33 can be formed by sputter deposition or evaporation.

Semiconductor region 26 and top surface 27 interact with layer 31 to produce a compound of the atoms of semiconductor region 26;
A metal semiconductor layer 34 such as metal silicide is formed. The atoms of the metal semiconductor layer 34 are
Is formed or not depending on whether the temperature of the surface 27 has risen to a temperature sufficient to diffuse from the first layer 31 to the first layer 31 or vice versa to form a compound.

The dielectric layer 16 can be selected from the group consisting of ferroelectric or paraelectric materials such as barium strontium titanate and lead zirconium titanate (PZT), for example. It is a high dielectric constant material.

The upper electrode 18 is made of, for example, Pt, Au, R
It may be a layered metal selected from the group consisting of u, Ir, Re, Rh, Os, Pd and alloys thereof.

A voltage is applied to the upper electrode 18 through the conducting wire 40, and the lower electrode 14, the semiconductor region 26, the doped region 3
8, if the substrate 12 of the bottom are conducted through wires 42 thereto, by multiplying the secondary voltage V ₂ to the substrate 12, it takes the primary voltages V ₁ to the capacitor 10. A semiconductor region 26 and, if present, a metal semiconductor layer 34;
Since the lower electrode 14 including the first layer 31, the second layer 32, and the third layer 33 is conductive, the voltage V ₁ applied to the conductor 40 and the upper electrode 18 is increased by the conductor 42 through the dielectric layer 1.
6, the voltage V ₂ is applied to the lower electrode 14. The potential difference across the capacitor 10 is V ₁ -V _2.

The first layer 31 of the lower electrode structure 14 is formed after the formation of the first layer 31 and during the formation of the second layer in which a portion of the first layer may be oxidized. It works to prevent oxidation. For example, if region 26 is silicon, metal silicide layer 34 may be ruthenium silicide,
The first layer 31 may be ruthenium. The second layer 32 may be ruthenium oxide and acts as a diffusion barrier for oxygen and semiconductor atoms. The semiconductor atoms come from the semiconductor region 26 and the oxygen atoms come from the dielectric layer 16.

The third layer 33 is preferably made of an antioxidant metal such as platinum, for example, and prevents interaction between the subsequently formed high dielectric oxide of the dielectric layer 16 and the metal oxide of the second layer 32. Has functions. Without the 33 layers of antioxidant metal, the metal oxide of layer 32 would interact with and diffuse into dielectric layer 16 or dielectric layer 16 would interact with metal oxide layer 32 and Could spread to Without the diffusion barrier layer 33, the metal oxide from the layer 32 is likely to migrate or diffuse into the dielectric layer 16.

In a preferred embodiment, the first layer 31
Contains metals such as Ru, Ir, Re, and Rh. Second layer 32
Contains oxides of one or several metals constituting the first layer 31.

FIG. 3 shows a capacitor suitable for the memory array 9. In FIG. 3, FIG. 1 and FIG.
The functions corresponding to are marked with the same symbols. Semiconductor region 26 'extends above surface 22 of dielectric layer 20 to increase the surface area of lower electrode structure 14' formed over semiconductor region 26 '. A dielectric layer 16 'and an upper electrode 18' are formed over the lower electrode structure 14 '. The semiconductor region 26 ′ is cubic, rectangular, cylindrical, conical, or a complex geometric shape and protrudes from the surface 21 of the substrate 12. The shape above surface 22 includes lower electrode 14 'and upper electrode 18'.
It serves to give more surface area to the surface.

As described above, the substrate, the semiconductor region on the substrate having the exposed surface, and Ru, Ir, Re, Rh, O, O formed on the semiconductor region so as to make ohmic contact with the semiconductor region.
a first layer of a metal selected from the group consisting of s, Pd and alloys thereof, and Ru, Ir, Re, Rh, Os, Pd, and Ru formed on the first layer in ohmic contact with the first layer. A second layer of a metal oxide selected from the group consisting of oxides of those mixtures; and Pt, Au, Ru, Ir, R
a third layer selected from the group consisting of e, Rh, Os, Pd and alloys thereof, and a composite oxide type material, especially Ba
_{x Sr (1-x) TiO} 3 and PbZr _X T _1-X O ₃ and a fourth layer of high dielectric material selected from the ferroelectric or the group consisting of paraelectric material (PZT) or the like, the fourth A capacitor and electrode structure has been described, including a fifth layer of conductive material formed on the layer.

In summary, the following is disclosed regarding the configuration of the present invention.

(1) A substrate, a semiconductor region on the substrate, and Ru, Ir, Re, Rh, Os, and Ru formed on the semiconductor region in ohmic contact with the semiconductor region.
A first layer of a metal selected from the group consisting of Pd and their alloys, and Ru, Ir, Re, Rh, Os, Os, formed on the first layer in ohmic contact with the first layer;
A second layer of a metal oxide selected from the group consisting of oxides of Pd and their alloys, and Pt, Au, Ru, Ir, Re,
And a third layer of a metal selected from the group consisting of Rh, Os, Pd, and alloys thereof. (2) The semiconductor integrated circuit capacitor electrode structure according to (1), wherein the semiconductor region includes a material selected from the group consisting of silicon, germanium, and alloys thereof. (3) The capacitor electrode structure for a semiconductor integrated circuit according to the above (1), wherein the semiconductor region and the metal of the first layer form a compound at an interface between them. (4) The capacitor electrode structure for a semiconductor integrated circuit according to the above (3), wherein the compound is a silicide. (5) A group consisting of Ru, Ir, Re, Rh, Os, Pd, and an alloy thereof formed on the substrate, the semiconductor region on the substrate, and the semiconductor region in ohmic contact with the semiconductor region. And a first layer of a metal selected from the group consisting of Ru, Ir, Re, Rh, Os, Pd, and mixtures thereof formed on the first layer in ohmic contact with the first layer. Second of selected metal oxide
Layers and Pt, Au, Ru, Ir, Re, Rh, Os, P
a third layer of a metal selected from the group consisting of d and alloys thereof, a fourth layer of a high dielectric constant material, and a fifth layer of a conductive material formed on the fourth layer. Integrated circuit capacitors. (6) The high dielectric constant material is BaTiO ₃ , SrTiO ₃ ,
Ba _x Sr _(1-x) TiO ₃ , PLT, or PbZr _X T
The semiconductor integrated circuit capacitor according to the above (5), which is _1-X O ₃ (PZT). (7) The semiconductor integrated circuit capacitor according to the above (5), wherein the capacitor is a capacitor for a dynamic random access memory (DRAM).

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is an enlarged view of a part of FIG.

FIG. 3 is a cross-sectional view of an alternative embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Capacitor 11 Capacitor 12 Substrate 14 Lower electrode 16 Dielectric layer 18 Upper electrode 20 Dielectric layer 24 Groove 25 Groove 26 Semiconductor region 28 Semiconductor region 38 Doped region 40 Doped region

Continued on the front page (72) Inventor Richard Joseph Gambino United States 11790 Stony Brook, New York Sycamore Circle 148 (72) Inventor Alfred Grill United States 10605 New York White Plains Overlook Road 85 (72) Invented Author William Francis Cane United States 10921 Florida New Street, New York 17 (72) Inventor Donald Joseph Micalsen US 10512 New York, Carmel Longfellow and Hutchinson Drives (No Address) (56) References Special JP-A-7-263635 (JP, A) JP-A-5-29567 (JP, A) JP-A-6-5810 (JP, A) JP-A-4-37170 (JP, A) JP-A-7-99290 (JP JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04 H01L 27/105

Claims (7)

(57) [Claims] A substrate, a semiconductor region on the substrate, and Ru, Ir, Re, Rh, Os, Pd formed on the semiconductor region so as to make ohmic contact with the semiconductor region.
And a first layer of a metal selected from the group consisting of alloys thereof, and Ru, Ir, Re, Rh, Os, Pd, and Ru formed on the first layer in ohmic contact with the first layer. A second layer of a metal oxide selected from the group consisting of oxides of those alloys, and a Pt, on which a high dielectric material can be formed;
And a third layer of a metal selected from the group consisting of Au, Ru, Ir, Re, Rh, Os, Pd and alloys thereof. 2. The semiconductor integrated circuit capacitor electrode structure according to claim 1, wherein said semiconductor region contains a material selected from the group consisting of silicon, germanium, and alloys thereof. 3. The capacitor electrode structure of a semiconductor integrated circuit according to claim 1, wherein said semiconductor region and said metal of said first layer form a compound at their interface. 4. A capacitor electrode structure for a semiconductor integrated circuit according to claim 3, wherein said compound is silicide. 5. A substrate, a semiconductor region on the substrate, and Ru, Ir, Re, Rh, Os, Pd formed on the semiconductor region so as to make ohmic contact with the semiconductor region.
And a first layer of a metal selected from the group consisting of alloys thereof, and Ru, Ir, Re, Rh, Os, Pd, and Ru formed on the first layer in ohmic contact with the first layer. A second layer of a metal oxide selected from the group consisting of mixtures thereof; and a third layer of a metal selected from the group consisting of Pt, Au, Ru, Ir, Re, Rh, Os, Pd and alloys thereof. And a fourth layer of a high dielectric constant material; and a fifth layer of a conductive material formed on the fourth layer. 6. The high dielectric constant material is BaTiO ₃ , SrT.
iO ₃ , Ba _x Sr _(1-x) TiO ₃ , PLT, or PbZ
The semiconductor integrated circuit capacitor according to claim 5, characterized in that the _{r X T 1-X O 3} (PZT). 7. The semiconductor integrated circuit capacitor according to claim 5, wherein said capacitor is a capacitor for a dynamic random access memory (DRAM).