JP3307609B2 - Semiconductor storage device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device having a flat capacitor using a high dielectric constant oxide and a method for manufacturing the same.

[0002]

[Prior art]

[0003]

BACKGROUND OF THE INVENTION Dynamic Random Access Memo (DRAM)
ries) and other high-density oxide films such as (Ba, Sr) TiO ₃ instead of silicon oxide films or silicon nitride films as capacitive insulating films have been prosperous. Is being considered.

Because of the high dielectric constant of such a high-dielectric-constant oxide, it can be applied not only to a three-dimensional structure such as a stack type structure which is currently mainstream, but also to a planar type structure in a capacitor cell structure.

FIGS. 8 and 9 are cross-sectional views showing a manufacturing process near a flat capacitor portion of a semiconductor memory device having a planar capacitor cell structure according to a conventional method.

First, as shown in FIG. 8A, a capacitor contact 101 is formed on a first interlayer insulating film 102.
Lower electrode layer 103a having a laminated structure composed of Ti, TiN, Ru, RuO ₂ , high dielectric constant oxide layer 104a composed of (Ba, Sr) TiO ₃ , upper electrode layer 105 composed of Pt
a is sequentially formed by a chemical vapor deposition method (CVD method) or a sputtering method.

Next, a desired shape is processed by a dry etching method using a PR mask, and then the PR mask is removed to form a capacitor insulating film made of a high dielectric constant oxide as shown in FIG. 104 is a lower electrode 103 and an upper electrode 10
5 to form a flat capacitor (thin film capacitor) having a laminated structure.

[0008] Thereafter, as shown in FIG. 8 (c), C is applied so as to cover the second interlayer insulating film 106 on the flat capacitor.
It is formed by the VD method.

Subsequently, as shown in FIG. 9D, a contact opening 107a for a plate contact for leading to a plate electrode is formed by a dry etching method using a PR mask.

After that, the adhesion layer 108 made of Ti is
The contact plug 107 is formed on a region including the inner surface of the contact opening 107a on the interlayer insulating film 106, and then an electrode material layer made of Pt to be the plate electrode 109 is deposited by a sputtering method so as to fill the contact opening 107a. Then, the electrode material layer is processed into a desired shape together with the adhesion layer by dry etching using a PR mask to form a plate electrode 109, thereby obtaining a conventional semiconductor memory device (FIG. 9E). ).

[0011]

In the semiconductor memory device formed by the above conventional method, an adhesion layer made of Ti exists at the interface between the contact plug and the upper electrode. The heat treatment (annealing treatment) performed in an oxygen atmosphere causes oxidation and diffusion of the adhesion layer, resulting in a problem that the resistance of the contact increases and the leak current density increases.

FIGS. 3A and 3B show the resistance of the plate contact and the current-voltage of the capacitor after annealing the semiconductor memory device formed by the above-mentioned conventional method in an oxygen atmosphere at 400 ° C. The evaluation results of the characteristics are shown. By annealing at 400 ° C. in an oxygen atmosphere,
Contact resistance and leakage current density are increasing,
It turns out that there is a problem in device operation.

The cause of the increase in the contact resistance is as follows.
From the result of the AES analysis in the sectional direction, the contact plug 1
Adhesion layer 1 existing at the interface between the electrode 07 and the upper electrode 105
08 was suggested to be due to oxidation.

The cause of the increase in the leak current density is as follows.
The results of the AES analysis in the cross-sectional direction suggested that the Ti adhesion layer 108 was caused by diffusion in the direction of the upper electrode 105.

An object of the present invention is to provide a plate contact having no contact layer at least at an interface between a contact plug and an upper electrode, thereby suppressing an increase in contact resistance and leak current density after oxygen annealing. And a method of manufacturing the same.

[0016]

According to a first aspect of the present invention, there is provided a flat capacitor having a laminated structure in which a capacitive insulating film made of a high dielectric constant oxide is sandwiched between an upper electrode and a lower electrode, and an interlayer on the flat capacitor. A semiconductor memory device having a plate electrode formed through an insulating film, and having a structure in which the plate electrode and the upper electrode are electrically connected by a contact plug formed in the interlayer insulating film. Between the interlayer insulating film and the plate electrode,
An adhesion layer including a layer made of a material containing at least one of TiN, TiSi _x , Ta, TaN, W, and WSi;
Further, the adhesion layer does not exist at the interface of the connection portion between the contact plug and the upper electrode, and the upper electrode, the upper electrode,
The contact plug and the plate electrode are Pt, Ru,
At least one of Ir, Re, Os, Rh and oxides thereof
A semiconductor memory device characterized by comprising the.

According to a second aspect of the present invention, there is provided the above-described semiconductor memory device, wherein the adhesion layer is not formed at the interface between the interlayer insulating film and the contact plug.

According to a third aspect of the present invention, there is provided a container made of a high dielectric constant oxide.
Laminated structure in which the insulating film is sandwiched between the upper and lower electrodes.
Having a flat capacitor and on the flat capacitor
And a plate electrode formed through an interlayer insulating film.
And the plate electrode and the upper electrode are formed of the interlayer insulating film.
Electrically connected by contact plugs formed in
The interlayer insulating film and the plate electrode
In between, Ti, TiN, TiSi _x , Ta, TaN, W,
A dense layer including a layer made of a material containing at least one of WSi
A contact layer, and the contact plug and the upper electrode.
A method of manufacturing a semiconductor memory device in which the adhesion layer does not exist at an interface between a pole and a contact, wherein a step of forming an interlayer insulating film on a flat capacitor, and a step of contacting the interlayer insulating film to reach an upper electrode Forming an opening, forming an adhesion layer, removing the adhesion layer formed at the bottom of the contact opening so that the upper electrode is exposed by photolithography, and forming a plate electrode so as to fill the contact opening. Or forming a plate electrode after filling the contact opening with a conductive material.

According to a fourth aspect of the present invention, there is provided a container made of a high dielectric constant oxide.
Laminated structure in which the insulating film is sandwiched between the upper and lower electrodes.
Having a flat capacitor and on the flat capacitor
And a plate electrode formed through an interlayer insulating film.
And the plate electrode and the upper electrode are formed of the interlayer insulating film.
Electrically connected by contact plugs formed in
The interlayer insulating film and the plate electrode
In between, Ti, TiN, TiSi _x , Ta, TaN, W,
A dense layer including a layer made of a material containing at least one of WSi
A contact layer, and the contact plug and the upper electrode.
The adhesion layer does not exist at the interface of the connection portion with the pole,
Adhesion also at the interface between the inter-insulation film and the contact plug
A method for manufacturing a semiconductor memory device having no layer formed thereon, comprising: a step of forming an interlayer insulating film on a flat capacitor; a step of forming an adhesion layer on the interlayer insulating film; Forming a contact opening so that the film reaches the upper electrode and the upper electrode is exposed; and forming a plate electrode so as to fill the contact opening.
Alternatively, a step of forming a plate electrode after filling the contact opening with a conductive material, and forming a plate electrode
And then annealing at 300 to 600 ° C. in an oxygen atmosphere.
And a method of manufacturing a semiconductor memory device having the steps of:

The fifth invention relates to the method of manufacturing a semiconductor memory device according to the third invention , which comprises a step of annealing at 300 to 600 ° C. in an oxygen atmosphere after forming a plate electrode.

[0021]

As described above, the increase in the contact resistance and the leak current density of the semiconductor memory device according to the conventional method are the same as those in the plate contact structure. 108. Then, the present inventor diligently studied a structure in which the adhesion layer 108 does not exist at the interface between the contact plug 107 and the upper electrode 105. As a result, a semiconductor memory device having extremely good characteristics can be obtained. Reached.

Hereinafter, a preferred embodiment of the present invention will be described in detail.

First Embodiment FIGS. 1 and 2 are cross-sectional views showing a manufacturing process in the vicinity of a flat capacitor portion of a semiconductor memory device having a planar capacitor cell structure for explaining a first embodiment of the present invention. is there.

First, as shown in FIG. 1A, a capacitor contact 101 is formed on a first interlayer insulating film 102.
Lower electrode layer 103a having a laminated structure composed of Ti, TiN, Ru, RuO ₂ , high dielectric constant oxide layer 104a composed of (Ba, Sr) TiO ₃ , upper electrode 105a composed of Pt
Are sequentially formed by a chemical vapor deposition method (CVD method) or a sputtering method.

Next, a desired shape is processed by a dry etching method using a PR mask, and then the PR mask is removed to form a capacitor insulating film made of a high dielectric constant oxide as shown in FIG. 104 is a lower electrode 103 and an upper electrode 10
5 to form a flat capacitor (thin film capacitor) having a laminated structure.

Thereafter, as shown in FIG. 1C, a second interlayer insulating film 106 is formed so as to cover the flat capacitor by a CVD method.

Subsequently, as shown in FIG. 1D, a contact opening 107a for a plate contact for leading out to a plate electrode is formed in the second interlayer insulating film 106 by dry etching using a PR mask. Is formed to reach.

Thereafter, as shown in FIG. 2E, an adhesion layer 108 made of Ti is formed on the region including the inner surface of the contact opening 107a on the second interlayer insulating film 106.

Next, as shown in FIG. 2F, the contact opening 1 is formed by dry etching using a PR mask.
07a is removed and the upper electrode 105 is removed.
To expose.

Next, an electrode material layer made of Pt to be the plate electrode 109 is formed by a sputtering method on the contact opening 1.
07a are formed so as to be embedded.
Then, the electrode material layer is processed into a desired shape together with the adhesion layer by a dry etching method using a PR mask to form a plate electrode 109 (FIG. 2G).
Here, after forming the contact plug 107 by filling the contact opening 107a with a conductive material, a plate electrode may be formed by forming an electrode material layer. afterwards,
Annealing is performed in an oxygen atmosphere. This oxygen annealing is performed to recover the high dielectric constant oxide film damaged by the etching, and the leak characteristics can be improved by the oxygen annealing. The condition of such oxygen annealing is that the temperature is 300 ° C.
-600 ° C., preferably 350 ° C.-500 ° C., and an oxygen atmosphere in an inert gas such as nitrogen or argon having a partial pressure of oxygen of 0.1-10%, preferably about 0.5-5% is sufficient. The effect can be obtained.

FIGS. 3A and 3B show the evaluation of the resistance of the plate contact and the current-voltage characteristics of the capacitor after the semiconductor memory device according to the present embodiment is annealed in an oxygen atmosphere at 400 ° C., respectively. The results are shown. For comparison, the evaluation results of the semiconductor memory device according to the conventional method shown in FIGS. 9 and 10 are also shown.

The contact resistance of the semiconductor memory device manufactured by the conventional method is increased by almost half during the measurement at 25 points, whereas the semiconductor memory device according to the present embodiment has
During the measurement at 25 points, good contact resistance values were obtained at all points.

The leakage current density of the semiconductor memory device manufactured by the conventional method is large when the driving voltage is 1 V or less, and there is a problem in device operation. On the other hand, in the semiconductor memory device according to the present embodiment, Even at a driving voltage of 1.5 V, the leakage current density is 1 × 10 ⁻⁸ A / c.
Good leak characteristics of m ² or less could be obtained.

In the present embodiment, the structure in which the adhesion layer 108 does not exist at the interface between the upper electrode 105 and the contact plug 107 is employed. Therefore, oxidation and diffusion of the adhesion layer do not occur. Shows good contact resistance and leak characteristics.

Second Embodiment FIGS. 4 and 5 are cross-sectional views showing a manufacturing process of a flat capacitor portion of a semiconductor memory device having a planar capacitor cell structure for explaining a second embodiment of the present invention. .

First, as shown in FIG. 4A, on the first interlayer insulating film 102 in which the capacitance contact 101 has been formed,
Lower electrode layer 103a having a laminated structure composed of Ti, TiN, Ru, RuO ₂ , high dielectric constant oxide layer 104a composed of (Ba, Sr) TiO ₃ , upper electrode layer 105 composed of Pt
a is sequentially formed by a chemical vapor deposition method (CVD method) or a sputtering method.

Next, a desired shape is processed by a dry etching method using a PR mask, and then the PR mask is removed. As shown in FIG. 104 is a lower electrode 103 and an upper electrode 10
5 to form a flat capacitor having a laminated structure.

Thereafter, as shown in FIG. 4C, a second interlayer insulating film 106 is formed so as to cover the flat capacitor by a CVD method, and then an adhesion layer 108 made of Ti is formed.
To form

Next, as shown in FIG.
08 and the second interlayer insulating film 106, a contact opening 10 for a plate contact for leading out to a plate electrode.
7a is formed by dry etching using a PR mask so as to reach the upper electrode 105 and expose the upper electrode.

After that, an electrode material layer made of Pt to be the plate electrode 109 is formed on the contact opening 1 by sputtering.
07a are formed so as to be embedded.
Then, the electrode material layer is processed into a desired shape together with the adhesion layer by a dry etching method using a PR mask to form a plate electrode 109 (FIG. 5E).
Here, after forming the contact plug 107 by filling the contact opening 107a with a conductive material, a plate electrode may be formed by forming an electrode material layer. afterwards,
Oxygen annealing is performed as in the first embodiment.

FIGS. 6A and 6B show the evaluation of the resistance of the plate contact and the current-voltage characteristics of the capacitor after the semiconductor memory device according to the present embodiment is annealed in an oxygen atmosphere at 400 ° C., respectively. The results are shown.

As in the first embodiment, in the semiconductor memory device according to the present embodiment, good contact resistance values are obtained at all points during the measurement at 25 points, and the driving voltage is 1.5 V
In this case, good leak characteristics with a leak current density of 1 × 10 ⁻⁸ A / cm ² or less can be obtained.

After the formation of the plate electrode, the adhesion of the plate electrode was also evaluated by a peeling test.
The in-plane adhesion was also good.

Third Embodiment In the first and second embodiments, Ti is applied to the adhesion layer, but Ta can be applied as another material. This embodiment will be described with reference to FIGS. 4 and 5 used in the second embodiment.

First, as shown in FIG. 4A, a capacitor contact 101 is formed on a first interlayer insulating film 102.
Lower electrode layer 103a having a laminated structure composed of Ti, TiN, Ru, RuO ₂ , high dielectric constant oxide layer 104a composed of (Ba, Sr) TiO ₃ , upper electrode layer 105 composed of Pt
a is sequentially formed by a chemical vapor deposition method (CVD method) or a sputtering method.

Next, a desired shape is processed by a dry etching method using a PR mask, and then the PR mask is removed to form a capacitor insulating film made of a high dielectric constant oxide as shown in FIG. 104 is a lower electrode 103 and an upper electrode 10
5 to form a flat capacitor having a laminated structure.

Thereafter, as shown in FIG. 4C, a second interlayer insulating film 106 is formed so as to cover the flat capacitor by the CVD method, and then an adhesion layer 107 made of Ta is formed.
Are sequentially formed.

Next, as shown in FIG.
08 and the second interlayer insulating film 106, a contact opening 1 for a plate contact for leading out to a plate electrode.
07a is formed by a dry etching method using a PR mask so as to reach the upper electrode 105 and expose the upper electrode.

After that, an electrode material layer made of Pt to be the plate electrode 109 is formed on the contact opening 1 by sputtering.
07a are formed so as to be embedded.
Then, the electrode material layer is processed into a desired shape together with the adhesion layer by a dry etching method using a PR mask to form a plate electrode 109 (FIG. 5E).
Here, after forming the contact plug 107 by filling the contact opening 107a with a conductive material, a plate electrode may be formed by forming an electrode material layer. afterwards,
Oxygen annealing is performed as in the first embodiment.

FIGS. 7A and 7B show the evaluation of the resistance of the plate contact and the current-voltage characteristics of the capacitor after the semiconductor memory device according to the above embodiment is annealed in an oxygen atmosphere at 400 ° C., respectively. The results are shown.

As in the first and second embodiments, in the semiconductor memory device according to the present embodiment, good contact resistance values are obtained at all points during the measurement at 25 points, and the driving voltage is 1.5 V. The leakage current density is 1 × 10 ^-8 A
/ Cm ² or less.

[0052]

Other Embodiments In the above three embodiments, the embodiment in which the lower electrode 103 has a laminated structure composed of Ti, TiN, Ru, and RuO ₂ has been described. However, instead of the Ru and RuO ₂ layers, Ru, Ir, Re, Os, Rh
Metal, or at least one or more materials selected from oxides and silicide compounds thereof, or Pt,
A layer made of at least one material selected from Au, Ag, Pd, Ni, and Co may be used. Also, instead of TiN and Ti layers, Ti, TiN, TiSi
It is also effective to use a layer made of at least one material of X, Ta, TaN, W, and WSi.

In the above three embodiments, the upper electrode, the plate electrode, and the contact plug are all formed using Pt, but Ru, Ir, Re, Os,
It may be formed using one or more of a noble metal material such as Rh or an oxide thereof. In addition, the upper electrode, the plate electrode, and the contact plug may be formed from different materials among the above-described materials.

In the above three embodiments, a single-layer structure made of Ti or Ta has been described as the adhesion layer, but Ti, TiN, TiSi _x , Ta, Ta
It may be a single layer made of a material composed of one or more of N, W, and WSi. Further, the adhesion layer may be a laminated adhesion layer in which a layer made of these materials is arranged at least on the insulating film side. For example, a layer made of such a material is used as a lowermost layer, and Pt, Ru, Ir, Re, Os,
It may have a laminated structure in which layers composed of one or more kinds of noble metals such as Rh and oxides thereof are laminated.

Further, in the above three embodiments, the example of (Ba, Sr) TiO ₃ was described as the high dielectric constant oxide, but the present invention relates to the case where the high dielectric constant oxide is represented by the general formula ABO ₃ . And A is Ba, Sr, Pb, Ca, La, L
one or more of i and K, B is Ti, Zr, Ta,
One containing at least one of Nb, Mg, Fe, Zn and W, for example, SrTiO ₃ , (Sr, Ca) TiO ₃ , (B
_{a, Sr, Ca) TiO 3} , PbTiO 3, Pb (Zr,
Ti) O ₃ , (Pb, La) (Zr, Ti) O ₃ , Pb
(Mg, Nb) O ₃ , Pb (Mg, W) O ₃ , Pb (Z
n, Nb) O ₃ , LiTaO ₃ , LiNbO ₃ , KTa
O ₃ , KNbO ₃ , or the general formula (Bi ₂ O ₂ ) (A _m-1
B _m O _{3m + 1} ) (m = 1, 2, 3, 4, 5);
Contains at least one of Ba, Sr, Pb, Ca, K, and Bi, and B contains at least one of Nb, Ta, Ti, and W, for example, Bi ₄ Ti ₃ O ₁₂ and SrBi ₂ Ta ₂ O.
_A similar effect can be obtained with SrBi ₂ Nb ₂ O ₉ or Ta ₂ O ₅ having a chemical composition different from the above general formula.

In the first to third embodiments, the high dielectric
Oxide film is (Ba, Sr) TiO _ThreeSingle-layer structure
Has been described, but different high dielectric constant materials
It may have a multi-layered structure. In addition, the above high dielectric constant acid
If the oxide film is formed, its high dielectric constant
Layers of other dielectric constant materials were stacked
It may have a multilayer structure.

[0057]

As is apparent from the above description, according to the present invention, in the structure of the contact between the plate electrode and the capacitor, there is no adhesion layer such as Ti at the interface between the contact plug and the upper electrode. Even if thermal annealing is performed in an oxygen atmosphere after the formation of the plate electrode, increase in contact resistance and leak current density can be suppressed.

Further, according to the present invention, since the adhesion layer exists at the interface between the plate electrode and the interlayer insulating film, the adhesion between them is ensured. Further, since the contact plug and the upper electrode are in direct contact with each other, good adhesion is obtained. Therefore, adhesion is ensured in all regions below the plate electrode.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor memory device having a planar capacitor cell structure according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step following the step shown in FIG. 1 of the semiconductor memory device having a planar capacitor cell structure according to the present invention;

FIG. 3 is a diagram showing a contact resistance (a) and a leak current density (b) of a semiconductor memory device according to a first embodiment of the present invention and a conventional method after annealing in an oxygen atmosphere at 400 ° C.

FIG. 4 is a cross-sectional view showing another manufacturing step of the semiconductor memory device having the planar capacitor cell structure of the present invention.

5 is a cross-sectional view showing the manufacturing process of the semiconductor memory device having the planar capacitor cell structure according to the present invention, which is subsequent to FIG. 4;

FIG. 6 illustrates a semiconductor memory device according to a second embodiment of the present invention;
FIG. 6 is a diagram showing a contact resistance (a) and a leak current density (b) after annealing treatment in an oxygen atmosphere at 00 ° C.

FIG. 7 illustrates a fourth example of the semiconductor memory device according to the third embodiment of the present invention;
FIG. 6 is a diagram showing a contact resistance (a) and a leak current density (b) after annealing treatment in an oxygen atmosphere at 00 ° C.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a semiconductor memory device having a planar capacitor cell structure according to a conventional method.

FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor memory device having a planar capacitor cell structure according to a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Capacitance contact 102 1st interlayer insulation film 103 Lower electrode 103a Lower electrode layer 104 Capacitance insulation film 104a High dielectric constant oxide layer 105 Upper electrode 105a Upper electrode layer 106 Second interlayer insulation film 107 Plate contact plug 107a Contact opening 108 Adhesion layer 109 plate electrode

Claims (6)

(57) [Claims] 1. A flat capacitor having a laminated structure in which a capacitive insulating film made of a high dielectric constant oxide is sandwiched between an upper electrode and a lower electrode, and a plate electrode formed on the flat capacitor via an interlayer insulating film. A semiconductor memory device having a structure in which the plate electrode and the upper electrode are electrically connected by a contact plug formed in the interlayer insulating film, wherein the interlayer insulating film and the plate electrode In between, Ti, Ti
An adhesion layer including a layer made of a material containing at least one of N, TiSi _x , Ta, TaN, W, and WSi; and the adhesion at an interface of a connection portion between the contact plug and the upper electrode. No layer , the upper electrode, the contact plug and the plate
The electrode is made of Pt, Ru, Ir, Re, Os, Rh and its acid.
A semiconductor memory device comprising at least one of the following compounds . 2. The high dielectric constant oxide has a general formula of ABO ₃
Where A is Ba, Sr, Pb, Ca, La, L
one or more of i and K, B is Ti, Zr, Ta,
One containing at least one of Nb, Mg, Fe, Zn and W, or a compound represented by the general formula (Bi ₂ O ₂ ) (A _m-1 B _m O _{3m + 1} ) (m =
1, 2, 3, 4, 5), where A is Ba, Sr,
At least one of Pb, Ca, K, and Bi, and N as B
b, Ta, Ti, include one or more of W, or a semiconductor memory device according to claim 1, wherein comprising a Ta ₂ O _5. 3. A process according to claim 1 wherein the adhesive layer in the interface is not formed between said interlayer insulating film wherein contact plugs also
Is a semiconductor memory device described in 2 . 4. A capacitor insulating film comprising a high dielectric constant oxide is
Having a laminated structure sandwiched between the base electrode and the lower electrode.
Capacitor and an interlayer insulating film on the flat capacitor
And a plate electrode formed through the plate,
Electrode and the upper electrode are formed on the interlayer insulating film.
It has a structure that is electrically connected by a contact plug.
And Ti, T between the interlayer insulating film and the plate electrode.
one of iN, TiSi _x , Ta, TaN, W, WSi
Having an adhesion layer including a layer made of a material containing at least
One of the connection portions between the contact plug and the upper electrode
A method for manufacturing a semiconductor memory device in which the adhesion layer does not exist at an interface, comprising: forming an interlayer insulating film on a flat capacitor;
Forming a contact opening in the interlayer insulating film to reach the upper electrode, forming an adhesion layer, and removing the adhesion layer formed at the bottom of the contact opening so that the upper electrode is exposed by photolithography. A method for manufacturing a semiconductor memory device, comprising: a step of forming a plate electrode so as to fill the contact opening, or forming a plate electrode after filling the contact opening with a conductive material. 5. A capacitor insulating film comprising a high dielectric constant oxide is
Having a laminated structure sandwiched between the base electrode and the lower electrode.
Capacitor and an interlayer insulating film on the flat capacitor
And a plate electrode formed through the plate,
Electrode and the upper electrode are formed on the interlayer insulating film.
It has a structure that is electrically connected by a contact plug.
And Ti, T between the interlayer insulating film and the plate electrode.
one of iN, TiSi _x , Ta, TaN, W, WSi
Having an adhesion layer including a layer made of a material containing at least
One of the connection portions between the contact plug and the upper electrode
The adhesion layer does not exist at the interface, and the interlayer insulating film and the
The adhesion layer is also formed at the interface with the contact plug.
A method of manufacturing a semiconductor memory device not, a step of forming an interlayer insulating film on a flat capacitor,
Forming an adhesive layer on the interlayer insulating film, forming a contact opening so as to reach an upper electrode in the adhesive layer and the interlayer insulating film and exposing the upper electrode, and filling the contact opening. Forming a plate electrode, or forming a plate electrode after filling the contact opening with a conductive material, and forming the plate electrode
Then, annealing treatment is performed at 300 to 600 ° C. in an oxygen atmosphere.
And a method of manufacturing a semiconductor memory device. 6. The method of manufacturing a semiconductor memory device according to claim 4, further comprising a step of annealing at 300 to 600 ° C. in an oxygen atmosphere after forming the plate electrode.