JP4074734B2 - Ferroelectric capacitor, method of manufacturing the same, and ferroelectric memory - Google Patents

Description

以上列挙した金属元素は、いずれも酸化物の標準生成エンタルピーが酸化イリジウム（IrO₂）よりも低く、イリジウムよりも安定な酸化物を形成する。従って、これらの金属元素のいずれかを用いて緩衝層Ｍ２を形成すれば、イリジウムを用いたコンタクト層Ｍ１に対して酸素が逆流することを防ぐことができる。つまり、緩衝層Ｍ２がコンタクト層Ｍ１の酸化物から酸素を確実に受け取り、その酸素を手放さないようにすることができる。
【００４８】
一方、配線層Ｍ３の酸化を防ぐためには、第２の金属元素は第３の金属元素よりも酸化されやすい元素であることが望ましい。従って、第３の金属元素の種類に応じて第２の金属元素を適宜選択する必要がある。
【００４９】
例えば、配線層Ｍ３を構成する第３の金属元素として、バリアメタルであるチタン（Ti）を採用する場合には、酸化物の標準生成エンタルピーがチタンよりも低い（絶対値が大きい）元素を第２の金属元素として用いることが望ましい。つまり、酸化チタンよりも安定な酸化物を形成する金属元素によって緩衝層Ｍ２を構成すれば、配線層Ｍ３の酸化を防ぎ、または配線層Ｍ３が酸化された場合にもこれを還元することが可能となる。
【００５０】
このような金属元素の一例をチタンのデータと共に以下に列挙する。
【００５１】

チタンの酸化物であるTiOとTiO₂とを比較すると、後者の方が標準生成エンタルピーが低く、安定であることが分かる。しかし、FRAMの製造工程において実際にチタンが酸化される場合を想定すると、プラズマなどに晒された非平衡の状態で酸化が進行する場合も多い。つまり、チタンの酸化物としてTiOが形成され得る場面も多いと考えられる。
【００５２】
このように酸化チタンとして TiOが形成される場合には、上述したいずれの金属元素の酸化物の標準生成エンタルピーは、TiOよりも低く、チタンよりも安定な酸化物を形成する。従って、これらの金属元素のいずれかを用いて緩衝層Ｍ２を形成すれば、チタンを用いた配線層Ｍ３の酸化を防ぐことができる。つまり、緩衝層Ｍ２が配線層Ｍ３よりも優先的に酸化され、または、配線層Ｍ３の酸化物から酸素を確実に受け取り、その酸素を手放さないようにすることができる。
【００５３】
一方、チタンの酸化物としてTiO₂が形成される場合には、TiO₂よりも標準生成エンタルピーが低い金属元素を用いれて緩衝層Ｍ２を形成すれば良い。つまり、上述した金属元素のうちの、ニオブ（Nb）、バナジウム（V）、クロム（Cr）及びレニウム（Re）を用いれば、チタンが酸化されてTiO2が形成され得る場合においても、チタンの酸化を防ぎ、あるいはこれを還元することが可能となる。
【００５４】
また、ここで緩衝層Ｍ２の位置も重要である。すなわち、緩衝層Ｍ２は、コンタクト層Ｍ１と配線層Ｍ３の間に設けられ、強誘電体層Ｆやコンタクト層Ｍ１から解離した酸素を受け止めて配線層Ｍ３の酸化を防止する。後に詳述するように、配線層Ｍ３の上には、極めて酸化されやすいアルミニウム層を形成する場合も多いが、緩衝層Ｍ２をコンタクト層Ｍ１と配線層Ｍ３の上に設けることにより、解離して拡散して来る酸素をこの位置で完全に受け取めることができる。従って、配線層Ｍ３やその上のアルミニウム層の酸化を確実に防ぐことができる。
【００５５】
なお、上述した元素は、一例に過ぎず、この他各種の金属元素を同様に用いることが可能である。また、２種類あるいはそれ以上の金属元素からなる層を積層させて用いても良い。
【００５６】
一方、配線層Ｍ３の材料としては、チタン以外にも窒化チタン（TiN）やその他の各種のバリアメタル或いは配線材料を用いることができるが、いずれの場合にも、配線層Ｍ３よりも酸化されやすい金属元素を第２の金属元素として採用することにより同様の効果を得ることができる。
【００５７】
さて、電極の電気抵抗の観点からは、第２の金属元素の酸化物の電気抵抗が第３の金属元素の電気抵抗よりも低いことが望ましい。つまり、緩衝層Ｍ２は配線層Ｍ３よりも優先的に酸化されることによって配線層Ｍ３の酸化を防止するのであるが、緩衝層Ｍ２の酸化物の電気抵抗が配線層Ｍ３の酸化物よりも低くなるように材料を選択すれば、配線層Ｍ３が酸化された場合よりも電極の抵抗を下げることができる。
【００５８】
例えば、配線層Ｍ３の材料として用いられることが多いチタンを例に挙げて説明すると、チタンの酸化物（TiOなど）の電気伝導性は、半導体的あるいは絶縁体的な特性を有する。すなわち、その比抵抗は極めて高く、且つ温度の上昇に応じて比抵抗が低下する。
【００５９】
これに対して、酸化物が金属伝導性を示し、比抵抗がはるかに低い金属元素が存在する。このような金属元素の一例を以下に列挙と、クロム（Cr）、セシウム（Cs）、モリブデン（Mo）、ニオブ（Nb）、オスミウム（Os）、鉛（Pb）、ルビジウム（Rb）、レニウム（Re）、ロジウム（Rh）、ルテニウム（Ru）、すず（Sn）、 タリウム（Tl）、バナジウム（V）などを挙げることができる。これらの金属元素の酸化物（例えば、CrO2、MoO2、SnO2、V2O3 など）は、比抵抗が低く、温度の上昇に伴って比抵抗が上昇するという金属的な伝導特性を有する。従って、このような金属元素を用いて緩衝層Ｍ２を形成すれば、緩衝層Ｍ２が酸化されても電気抵抗の増加を抑制することができ、コンタクト不良などの問題を解消することができる。
【００６０】
（第１の実施例）
以下、図２〜図７を参照しつつ、本発明の強誘電体キャパシタを用いたFRAMの具体例を、その作成例に従って説明する。
【００６１】
図２〜図７は、本実施例のFRAMの作成の手順を表す概略工程断面図である。
【００６２】
まず、図２に表したように、シリコン基板１０１の上に図示しないCMOS等の半導体素子を形成した後、第１の層間絶縁膜２０１を堆積する。
【００６３】
次に、図３に表したように、強誘電体キャパシタの第１の電極層Ｅ１を形成する。具体的には、前述したように白金（Pt）、イリジウム（Ir）或いはストロンチウムルテニウム酸化物（SRO）との組み合わせが有効である。但し、第１の電極層Ｅ１を形成する前に、チタン（Ti）あるいは窒化チタン（TiN）からなる下地層３００を層間絶縁膜２０１の上に形成し、その上に第１の電極層Ｅ１を形成する方法が有効である。これは、層間絶縁膜２０１の上に第１の電極層Ｅ１として白金などを直接堆積すると密着性が悪く、膜剥がれなどの問題が生じ、これを防ぐ為に実施するものである。
【００６４】
第１の電極Ｅ１の構造としては、Pt単層やlr単層などの他に、絶縁膜２０１から順に、例えば、SRO層／Pt層、lrO_２層／lr層などの積層構造を挙げられる。但し、強誘電体層Ｆを堆積する際に、下地が＜１１１＞配向している方が大きな分極が得られる。この観点からは、自己配向性をもつ白金を第１の電極層Ｅ１の最上層に配置すると有利である。
【００６５】
次に、強誘電体層Ｆを形成する。強誘電体層Ｆの材料としては、PZTやストロンチウムビスマスタイタネイト酸化物（ビスマス系層状ペロブスカイト、以下SBT）などが好適である。また、その堆積方法としては、スパッタ法、ゾルゲル法、或いはMOCVD（metal-organic chemical vapor deposition：有機金属化学気相成長）法などを挙げることができる。このようにして堆積した強誘電体層Ｆに、例えば大気圧の酸素雰囲気中で７００℃で１時間程度のアニールを施すことによって結晶化させる。
【００６６】
次に、第２の電極層Ｅ２のコンタクト層（第１の層）Ｍ１を堆積する。ここで、第２の電極層Ｅ２の構造を第１の電極層と同じにすれば対称性が良好となる。しかし、第２の電極層Ｅ２のコンタクト層Ｍ１に白金を採用すると、前述したように繰り返し書き込み／読み取りの疲労特性が良くない。よって、第２の電極層Ｅ２のコンタクト層Ｍ１は、酸化イリジウム（IrO₂）の単層とするか、または下側から順に酸化イリジウム層とイリジウム層とを積層させた積層体構造とすると良い。図示した具体例では、酸化イリジウム層４３とイリジウム層４４とを積層させた構造を表す。
【００６７】
次に、図４に表したように、コンタクト層Ｍ１、強誘電体層Ｆ、第１の電極層Ｅ１をそれぞれパターニングする。具体的には、フォトリソグラフィ工程により図示しないマスクを順次形成し、RIE（reactive ion etching）などの異方性エッチング法によりコンタクト層Ｍ１、強誘電体層Ｆ、第１の電極層Ｅ１を順次エッチングする。図示した具体例は、３回のフォトリソグラフィ工程とそれぞれのエッチングによりパターニングしたものを表すが、これ以外にも、２回或いは１回のフォトリソグラフィ工程とエッチングで形成するような構造にしても良い。
【００６８】
次に、図５に表したように、第２の層間絶縁膜２０２を堆積し、第１の層Ｍ１及び第１の電極Ｅ１へのコンタクトホール２０２Ｈをエッチングで開口する。そして、コンタクトホール２０２Ｈ内に緩衝層（第２の層）Ｍ２を堆積する。緩衝層Ｍ２の材料は、前述したように、１）コンタクト層Ｍ１を構成する金属元素よりも酸化されやすいこと、２）配線層Ｍ３を構成する金属元素よりも酸化されやすいこと、３）配線層Ｍ３を構成する金属元素の酸化物よりも比抵抗が低いこと、を満たす材料であることが望ましい。具体的には、緩衝層Ｍ２として、例えば、鉛（Pb）、すず（Sn）、ニオブ（Nb）、バナジウム（V）、ビスマス（Bi）、モリブデン（Mo）、クロム（Cr）、レニウム（Re）などの金属を堆積することができる。また、これらの金属のうちの２以上の層を積層させて緩衝層Ｍ２としても良い。
【００６９】
次に、図６に表したように、配線層（第３の層）Ｍ３を堆積する。具体的には、配線層として、例えばバリアメタルとして作用するチタン（Ti）を堆積する。さらに、第２の配線層５００を堆積してコンタクトホール２０２Ｈを埋め、ウェーハ表面に堆積層を形成する。第２の配線層５００の材料としては、アルミニウム（Al）などの比抵抗の低い金属を用いることが望ましい。
【００７０】
ここで、もし仮に緩衝層Ｍ２を形成しなかった場合は、コンタクト層Ｍ１の上に最初に堆積する配線層Ｍ３のチタンが酸化されることになる。というのは、IrO2の酸化物の生成エンタルピーは定常状態で−１６８kJ/mol であり、これは例えばチタンが酸化される生成エンタルピー（−５２０kJ/mol）の３分の１以下にすぎないからである。すなわち、緩衝層Ｍ２が無い状態でチタンを堆積した場合は、以下の反応が容易に起こる。
【００７１】
IrO2 ＋ 2Ti → Ir ＋ 2TiO
ここで、配線層Ｍ３のチタンの酸化を防ぐためには、緩衝層Ｍ２として酸素の拡散を防ぐ材料を用いることも考えられる。つまり、酸素の拡散に対するバリア層を緩衝層Ｍ２として用いれば、配線層Ｍ３の酸化を防ぐことは可能である。しかし、このようなバリア的な材料を堆積してもコンタクトホール２０２Ｈの底のエッジ部分は、スパッタによる堆積だと膜厚が表面の平坦な部分よりもかなり薄くなる場合がある。ここに結晶粒界が存在すると、容易に酸素が緩衝層中を拡散してその上のチタン層を酸化する。したがって、緩衝層Ｍ２の材料として、酸素の拡散を防止するバリア的な材料を採用する場合には、結晶粒界などを介した酸素の拡散を防ぐために、膜厚を厚く形成する必要がある。
【００７２】
仮に、コンタクト層Ｍ１として酸化イリジウム（IrO₂）ではなく、金属イリジウム（Ir）を採用した場合でも、コンタクトホール２０２Ｈを開口した後に、酸素雰囲気中での回復アニールを経ないと、強誘電体層Ｆの分極量は十分には得られない。したがって、コンタクトホール２０２Ｈの底部が酸素に晒されて酸化イリジウムが必ず生成される。つまり、コンタクト層Ｍ１が金属イリジウムであるか酸化イリジウムであるかを問わず、酸化イリジウムから解離した酸素を受け取り、その酸素を手放さない緩衝層Ｍ２が必要になるのである。
【００７３】
次に、図７に表したように、第２の配線層５００をパターニングし、さらに図示しない層間絶縁層を堆積し、配線層を適宜形成することによりFRAMが完成する。なお、シリコン基板１０１には、CMOSなどの図示しない半導体素子が形成されており、図示しない配線経路を介して、強誘電体キャパシタの各電極と接続される。
【００７４】
以上説明したように、本実施例によれば、層間絶縁膜にコンタクトホール２０２Ｈを設けた後に、緩衝層Ｍ２と配線層Ｍ３を堆積することにより、配線層Ｍ３の酸化を防ぐことができる。その結果として、電極抵抗の上昇やコンタクト不良などの問題を解消することができる。
【００７５】
（第２の実施例）
以下、図８〜図１３を参照しつつ、本発明の第２の具体例に係るFRAMの構成をその製造工程に沿って説明する。本具体例のFRAMは、半導体素子が形成されたシリコン基板のコンタクトプラグの上に強誘電体キャパシタが設けられたCOP（Capacitor On Plug）構造を有する。
【００７６】
図８〜図１３は、本具体例のFRAMの作成の手順を表す概略工程断面図である。これらの図については、第１実施例に関して前述したものと同様の部分には同一の符合を付して詳細な説明は省略する。
【００７７】
本具体例においては、まず、シリコン基板１０１の上にCMOSなどの図示しない半導体素子を形成した後、図８に表したように、第１の層間絶縁層２０１を堆積する。そして、層間絶縁層２０１にコンタクトホール形成して導電性材料で充填することにより埋め込みコンタクト２０１Ｐを形成する。
【００７８】
次に、図９に表したように、強誘電体キャパシタ部分を形成する。具体的には、まず、埋め込みコンタクト２０１Ｐを酸化させないようなバリア層３０２を堆積し、その上に、第１の電極層Ｅ１、強誘電体層Ｆ、コンタクト層Ｍ１、緩衝層Ｍ２をこの順に形成する。バリア層３０２の材料としては、窒化チタン（TiN_x）、窒化アルミニウム（AlN_x）、窒化アルミニウムチタン（AlTi_yN_x）窒化タングステン（WN_x）あるいは窒化ニオブ（NbN_x）などを用いることができる。
【００７９】
なお、第１の電極層Ｅ１、強誘電体層Ｆ、コンタクト層Ｍ１及び緩衝層Ｍ２については、それぞれ前述した材料を適宜用いることができる。
【００８０】
本実施例においては、前述した第１実施例と異なり、この段階で予め緩衝層Ｍ２まで堆積する。何故なら、本実施例において、キャパシタがコンタクトプラグ２０１Ｐの上にあるCOP構造をとっており、シリコン基板１０１から第１の電極層Ｅ１への配線が予め形成されており、基板１０１から第２の電極層Ｅ２への配線のみを考慮すれば良いためである。
【００８１】
次に、図１０に表したように、緩衝層Ｍ２、コンタクト層Ｍ１、強誘電体層Ｆ、第１の電極層Ｅ１をそれぞれパターニングする。
【００８２】
次に、図１１に表したように、第２の層間絶縁層２０２を堆積し、キャパシタ電極へのコンタクトホール２０２Ｈをエッチングにより開口する。
【００８３】
次に、図１２に表したように、配線層Ｍ３と、第２の配線層５００をスパッタ等の方法により堆積し、コンタクトホール２０２Ｈの内部を充填してさらに堆積する。
【００８４】
最後に図１３に表したように、配線層Ｍ３と第２の配線層５００をパターニングし、さらに図示しない層間絶縁層を堆積し、配線層を適宜形成することによりFRAMが完成する。
【００８５】
以上具体例を参照しつつ本発明の実施の形態について説明した。しかし、本発明は、これらの具体例に限定されるのではない。例えば、強誘電体キャパシタを構成する各層の材料については、具体的に列挙した材料には限定されず、本発明の趣旨に従って当業者が選択しうるすべての材料を用いて同様の作用効果を得ることができる。
【００８６】
また、強誘電体キャパシタは、強誘電体メモリ（FRAM）に搭載されるものには限定されず、その他のあらゆるデバイスに搭載するものについて同様の作用効果を奏しうる。
【００８７】
その他、本発明の思想に基づいて当業者が選択しうるすべての範囲は、本発明に包含され得る。
【００８８】
【発明の効果】
以上詳述したように、本発明によれば、酸化物強誘電体やこれに接触するコンタクト層から解離される酸素を確実に受け止める緩衝層を設けることにより、金属配線のバリア層などの酸化を確実且つ容易に防ぐことができる。その結果として、電極抵抗の上昇やコンタクト不良を解消することができる。
【００８９】
本発明によれば、特に酸素を放出しやすいイリジウム電極を用いた場合においてもコンタクト抵抗を低下させ、コンタクト歩留まりを顕著に改善し、さらに、繰り返し書き込み・読み出し特性も優れた強誘電体メモリを提供することができる。
【００９０】
すなわち、本発明によれば、信頼性に優れ製造歩留まりも改善された強誘電体キャパシタ、メモリを提供することができるようになり産業上のメリットは多大である。
【図面の簡単な説明】
【図１】本発明の誘電体キャパシタの要部断面構成を表す概念図である。
【図２】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図３】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図４】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図５】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図６】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図７】本発明の第１実施例のFRAMの作成の手順を表す概略工程断面図である。
【図８】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図９】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図１０】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図１１】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図１２】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図１３】本発明の第２実施例のFRAMの作成の手順を表す概略工程断面図である。
【図１４】従来のFRAMの要部断面構造を表す概念図である。
【符号の説明】
１０ 強誘電体キャパシタ
Ｅ１ 第１の電極層
Ｆ 強誘電体層
Ｅ２ 第２の電極層
Ｍ１ 第１の層（コンタクト層）
Ｍ２ 第２の層（緩衝層）
Ｍ３ 第３の層（配線層）
１０１ 基板
２０１ 第１の層間絶縁層
２０１Ｐ 埋め込みプラグ
２０２ 第２の層間絶縁層
２０２Ｈ コンタクトホール
３００、３０２、４００ 下地層
４０１ 下部電極
４０２ 強誘電体層
４０３、４０４ 上部電極
４８０ バリア層
５００ 配線層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric capacitor, a manufacturing method thereof, and a ferroelectric memory. More specifically, the present invention relates to a ferroelectric capacitor, a manufacturing method thereof, and a ferroelectric memory that can eliminate an increase in electrode resistance due to oxidation of a metal wiring layer and a contact failure.
[0002]
[Prior art]
Ferroelectric Random Access Memory (hereinafter referred to as “FRAM”) using a ferroelectric as a capacitor is a non-volatile memory that does not require a battery, that is, does not require a backup power source, and can operate at high speed. Utilizing the features, application to non-contact cards such as RF-ID (Radio Frequency-Identification) cards is being started. There are also great expectations for replacing existing static random access memory (SRAM), flash memory, dynamic random access memory (DRAM), etc. using silicon oxide capacitors.
[0003]
FIG. 14 is a conceptual diagram showing a cross-sectional structure of a main part of a conventional FRAM. The FRAM 100 has a configuration in which a ferroelectric capacitor is provided on a silicon substrate 101. In the formation, a CMOS (Complimant Metal Oxide Semiconductor) portion (not shown) is first formed on the silicon substrate 101, and an interlayer insulating film 201 such as BPSG (Boron-doped Phospho-Silicate Glass) is deposited and a planarization process is performed. After that, a capacitor is formed.
[0004]
In forming the capacitor, first, layers to be the base layer 400, the lower electrode 401, the ferroelectric layer 402, and the upper electrode 403 are deposited in this order. Examples of the material of the ferroelectric layer 402 include lead zirconate titanate (PbZr _x Ti _1-x O _Three : Hereinafter referred to as “PZT”).
[0005]
Next, the upper electrode 403 is etched through a photolithography process. Further, the ferroelectric layer 402 is etched through a resist removal and a photolithography process. Further, the lower electrode 401 and the base layer 400 are etched through a resist removal and photolithography process, and the resist is removed. Thereafter, a second interlayer insulating film 202 is deposited, a contact hole 202H is formed, a wiring layer with the silicon substrate 101 is formed, and the FRAM 100 is completed.
[0006]
Here, as the wiring layer formed inside the contact hole 202H, a layer in which a titanium (Ti) layer 480 serving as a barrier metal and a low-resistance aluminum (Al) layer 500 are stacked in this order is often used.
[0007]
Conventionally, platinum (Pt) has been a common material for the electrodes 401 and 403 of the ferroelectric capacitor. This is because a ferroelectric material such as PZT is an oxide in the first place, and platinum that is not oxidized even in an oxidizing atmosphere is excellent as an electrode material.
[0008]
However, it has been found that platinum has a harmful effect because it has a strong catalytic action. For example, if a ferroelectric capacitor is exposed to a hydrogen atmosphere, active hydrogen (H) is generated by the catalytic action of platinum, reducing oxide ferroelectrics such as PZT and degrading its ferroelectric properties. is there.
[0009]
In addition, repeated writing / reading operations with respect to a ferroelectric capacitor using platinum as an electrode show significant deterioration and exhibit fatigue characteristics that are not suitable for practical use. This is presumably because “oxygen loss” exists in the vicinity of the ferroelectric interface, and platinum cannot compensate for this “oxygen loss”.
[0010]
There is iridium (Ir) as an electrode material replacing platinum. Iridium is advantageous in that it has conductivity even when oxidized. Furthermore, since the catalytic action of iridium is weaker than that of platinum, the possibility of deteriorating the characteristics of the ferroelectric is low. Further, since oxygen is supplied from iridium oxide to the ferroelectric, the fatigue characteristics of the capacitor are also superior to those of the platinum electrode, and the characteristics can be maintained several orders of magnitude longer than the platinum electrode.
[0011]
[Problems to be solved by the invention]
However, as a result of studies by the present inventors, it has been found that when iridium is used as an electrode material, oxygen dissociated from iridium oxide, which is an oxide thereof, oxidizes the wiring metal.
[0012]
That is, the absolute value of the standard enthalpy of formation of iridium oxide (usually a negative value) is, for example, about an order of magnitude smaller than that of aluminum oxide. Ferroelectric capacitors must be annealed several times in an oxygen atmosphere, referred to as “recovery annealing,” because the properties of the ferroelectric material deteriorate during manufacturing. At this time, the outermost surface of iridium, which is an electrode material, is always oxidized, but iridium oxide itself can be easily oxidized by annealing in vacuum or contacting other easily oxidizable substances (for example, titanium or aluminum). There is a strong tendency to oxidize by giving oxygen to other substances.
[0013]
This property becomes a problem, for example, in the process of filling the contact hole 202H. In manufacturing the ferroelectric capacitor, an annealing process in an oxygen atmosphere is required after opening the contact hole 202H. Even if the electrode surface exposed at the bottom of the contact hole 202H is initially metallic iridium, it is inevitably oxidized by this annealing to become iridium oxide. Then, for example, when a titanium (Ti) layer 480 generally used as a barrier metal is deposited thereon by sputtering or the like, titanium is oxidized by the supply of oxygen from iridium oxide, and titanium oxide having a very high specific resistance. As a result, problems such as an increase in electrode resistance or contact failure occur.
[0014]
Even if the titanium layer 480 is sputtered at room temperature to prevent oxidation, it is difficult to prevent oxidation of titanium because the surface temperature reaches several hundred degrees during sputtering because the high temperature plasma contacts the surface. . Even if not oxidized at the time of sputtering, since a heating process of about 400 ° C. is performed in a later process, titanium is easily oxidized.
[0015]
As described above, when an iridium electrode is used for a ferroelectric capacitor, the characteristics of the capacitor alone are good, but the wiring metal is oxidized when integrated on a silicon substrate. Occurs.
[0016]
The present invention has been made based on recognition of such problems. That is, an object of the present invention is to provide a ferroelectric capacitor, a manufacturing method thereof, and a ferroelectric memory capable of preventing oxidation of an electrode of a wiring layer formed on the ferroelectric capacitor.
[0017]
According to one aspect of the invention, a first electrode layer;
A ferroelectric layer provided on the first electrode layer;
A first layer provided on the ferroelectric layer and containing at least one of iridium (Ir) and an oxide thereof;
A second layer provided on the first layer and containing at least one of a second metal element or an oxide thereof;
A third layer which is provided on the second layer and mainly contains a third metal element;
With
The second metal element is thallium (Tl), lead (Pb), rubidium (Rb), cesium (Cs), tin (Sn), ruthenium (Ru), rhodium (Rh), osmium (Os), niobium ( A ferroelectric capacitor is provided that is at least one selected from the group consisting of Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), and rhenium (Re) Is done.
[0018]
According to one embodiment of the present invention, the first electrode layer;
A ferroelectric layer provided on the first electrode layer;
A first layer provided on the ferroelectric layer and containing at least one of a first metal element and an oxide thereof;
A second layer provided on the first layer and containing at least one of a second metal element or an oxide thereof;
A third layer which is provided on the second layer and mainly contains a third metal element;
With
The first metal element is iridium (Ir),
The third metal element is titanium (Ti),
The second metal element is at least selected from the group consisting of chromium (Cr), molybdenum (Mo), niobium (Nb), lead (Pb), rhenium (Re), tin (Sn), and vanadium (V). There is provided a ferroelectric capacitor including any of the above.
[0019]
According to another aspect of the present invention, a step of forming a first layer containing at least one of iridium (Ir) or an oxide thereof on the ferroelectric layer;
Heat-treating the ferroelectric layer in an atmosphere containing oxygen;
Forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer;
Forming a third layer mainly composed of a third metal element on the second layer;
With
The second metal element is thallium (Tl), lead (Pb), rubidium (Rb), cesium (Cs), tin (Sn), ruthenium (Ru), rhodium (Rh), osmium (Os), niobium ( Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), and at least one selected from the group consisting of rhenium (Re) A method is provided.
[0020]
According to one aspect of the present invention, a step of forming a first layer containing at least one of the first metal element or its oxide on the ferroelectric layer;
Heat-treating the ferroelectric layer in an atmosphere containing oxygen;
Forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer;
Forming a third layer mainly composed of a third metal element on the second layer;
With
The first metal element is iridium (Ir),
The third metal element is titanium (Ti),
The second metal element is at least selected from the group consisting of chromium (Cr), molybdenum (Mo), niobium (Nb), lead (Pb), rhenium (Re), tin (Sn), and vanadium (V). A method of manufacturing a ferroelectric capacitor including any of the above is provided.
[0023]
Further, as a preferred embodiment of the present invention, if the specific resistance of the second metal element is lower than the specific resistance of the oxide of the third metal element, the electrode resistance is increased. And contact failure can be eliminated.
[0024]
In addition, if the oxide of the second metal element has metal conductivity at room temperature, the above effect can be obtained with certainty.
[0025]
On the other hand, the method for manufacturing a ferroelectric capacitor of the present invention includes a step of forming a first layer containing at least one of iridium (Ir) or an oxide thereof on the ferroelectric layer, and oxygen. Heat-treating the ferroelectric layer in an atmosphere; forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer; Forming a third layer mainly composed of a third metal element on the third layer, and
The second metal element is more easily oxidized than iridium.
[0026]
Here, the second metal element is thallium (Tl), lead (Pb), rubidium (Rb), cesium (Cs), tin (Sn), ruthenium (Ru), rhodium (Rh), osmium (Os). , Niobium (Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), and rhenium (Re).
[0027]
Alternatively, the method for manufacturing a ferroelectric capacitor according to the present invention includes a step of forming a first layer containing at least one of the first metal element or its oxide on the ferroelectric layer, and oxygen. Heat-treating the ferroelectric layer in a containing atmosphere, and forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer; Forming a third layer mainly composed of a third metal element on the third layer, and
It is desirable that the second metal element is more easily oxidized than the third metal element.
[0028]
Here, the first metal element is preferably iridium (Ir).
[0029]
The third metal element is titanium (Ti), and the second metal element is chromium (Cr), cesium (Cs), molybdenum (Mo), niobium (Nb), osmium (Os), At least one selected from the group consisting of lead (Pb), rubidium (Rb), rhenium (Re), rhodium (Rh), ruthenium (Ru), tin (Sn), thallium (Tl) and vanadium (V) It is desirable to include.
[0030]
In addition, TiO as titanium oxide ₂ When TiO is formed ₂ Alternatively, a metal element having a lower standard generation enthalpy may be used as the second metal element. That is, if niobium (Nb), vanadium (V), chromium (Cr), and rhenium (Re) are used as the second metal elements among the metal elements described above, titanium is oxidized and TiO ₂ Even when can be formed, oxidation of titanium can be prevented or reduced.
[0031]
On the other hand, the ferroelectric memory according to the present invention is provided on a semiconductor substrate on which a semiconductor element is formed, a first interlayer insulating layer provided on the semiconductor substrate, and the first interlayer insulating layer. Further, any one of the above-described ferroelectric capacitors and a low-resistance metal wiring layer provided on the third layer are provided.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0033]
FIG. 1 is a conceptual diagram showing a cross-sectional configuration of a main part of a dielectric capacitor of the present invention.
[0034]
That is, the dielectric capacitor 10 of the present invention has a configuration in which the first electrode layer E1, the ferroelectric layer F, and the second electrode layer E2 are stacked. The second electrode layer E2 includes a first layer M1 mainly composed of the first metal element, a second layer M2 mainly composed of the second metal element, and a third metal element. The third layer M3 as a main component is stacked in this order. Each layer constituting the dielectric capacitor 10 is not necessarily a single layer, and may be a structure in which two or more layers are laminated.
[0035]
The first electrode layer E1 serves as an electrode at one end of the dielectric capacitor. As will be described in detail later with reference to examples, the specific structure thereof is, for example, a single layer made of platinum (Pt), a single layer made of iridium (Ir), a platinum layer and strontium / ruthenium oxide (SrRuO). _Three : Hereinafter referred to as “SRO”), or a laminate of an iridium layer and an iridium oxide layer.
[0036]
When the ferroelectric layer F is formed on the first electrode E1, the polarization can be increased when the base is (111) oriented. From this viewpoint, it is preferable that platinum having self-orientation is disposed on the uppermost layer of the first electrode layer E1 so as to be in contact with the ferroelectric layer F.
[0037]
The ferroelectric layer F is polarized according to the voltage applied between the electrodes E1 and E2, and has a role of accumulating charges. As the material, it is desirable that the physical and chemical characteristics in a thin film state are stable and a large remanent polarization can be obtained. Specifically, in addition to various lead-based oxide ferroelectrics including PZT, Bi _Four Ti _Three O ₁₂ Or SrBi ₂ Ta ₂ O ₉ Various bismuth oxide ferroelectrics such as LiNbO _Three , YMnO _Three , Sr ₂ Nb ₂ O ₇ Various ferroelectrics such as can be used.
[0038]
The second electrode layer E2 serves as an electrode at the other end of the dielectric capacitor. The electrode layer E2 includes at least first to third layers M1 to M3. Each layer of M1 to M3 is not necessarily a single layer.
[0039]
The first layer M1 serves as a contact layer in contact with the ferroelectric layer F. The second layer M2 serves as a buffer layer that prevents oxidation of the third layer M3. The third layer M3 serves as a part of a wiring layer for connecting the dielectric capacitor and the external circuit, and typically, aluminum (Al) or copper (Cu) formed thereon is formed. It functions as a “barrier layer” that prevents the diffusion of low resistance metals such as
[0040]
The first feature of the electrode layer E2 is that the second metal element constituting the buffer layer (second layer) M2 is oxidized more than the first metal element constituting the contact layer (first layer) M1. It is easy to use. In this way, oxygen can be prevented from flowing back from the buffer layer M2 to the contact layer M1. That is, the buffer layer M2 can reliably receive oxygen from the oxide of the contact layer M1, and not release the oxygen.
[0041]
The second feature of the electrode layer E2 is that the second metal element constituting the buffer layer M2 is an element that is more easily oxidized than the third metal element constituting the wiring layer M3. That is, the oxidation of the wiring layer M3 is prevented by preferentially oxidizing the buffer layer M2.
[0042]
Further, the third feature of the electrode layer E2 is that the oxide of the second metal element constituting the buffer layer M2 has better electrical conductivity than the oxide of the third metal element constituting the wiring layer M3. It is in having. That is, the electric resistance of the oxide of the second metal element is made lower than the electric resistance of the oxide of the third metal element.
[0043]
The first to third features described above can prevent unnecessary oxidation of the first layer (contact layer) M1 and the third layer (wiring layer) M3. As a result, an increase in electrode resistance and contact failure caused by oxidation of the wiring layer M3 and the like can be reliably solved.
[0044]
More specifically, the configuration of the layers M1 to M3 illustrated in FIG. 1 will be described. First, the contact layer M1 that is in contact with the ferroelectric layer F is stable in contact with the ferroelectric layer F and has deteriorated characteristics. It is desirable to be made of a material that does not occur. In particular, iridium (Ir) is preferably used as the first metal element in order to improve fatigue characteristics of repeated writing / reading of FRAM. More specifically, the contact layer M1 may be composed of a single iridium layer, or may be a laminate of an iridium oxide layer and an iridium layer.
[0045]
On the other hand, the second metal element constituting the layer M2 is appropriately determined according to the relationship between the first metal element and the third metal element as described above.
[0046]
For example, when iridium is employed as the first metal element, it is desirable to use a metal element that is more easily oxidized than iridium. That is, it is desirable to use an element whose oxide standard generation enthalpy is lower than iridium (having a large absolute value) as the second metal element. Examples of such metal elements are listed below together with iridium data.
[0047]

All of the metal elements listed above have an oxide standard generation enthalpy of iridium oxide (IrO ₂ ) And more stable than iridium. Therefore, if the buffer layer M2 is formed using any of these metal elements, oxygen can be prevented from flowing backward to the contact layer M1 using iridium. That is, the buffer layer M2 can reliably receive oxygen from the oxide of the contact layer M1, and not release the oxygen.
[0048]
On the other hand, in order to prevent oxidation of the wiring layer M3, it is desirable that the second metal element is an element that is more easily oxidized than the third metal element. Therefore, it is necessary to appropriately select the second metal element according to the type of the third metal element.
[0049]
For example, when titanium (Ti), which is a barrier metal, is used as the third metal element constituting the wiring layer M3, an element whose oxide standard generation enthalpy is lower than that of titanium (having a larger absolute value) is used. It is desirable to use it as the second metal element. That is, if the buffer layer M2 is made of a metal element that forms a more stable oxide than titanium oxide, it is possible to prevent the wiring layer M3 from being oxidized or to reduce it even when the wiring layer M3 is oxidized. It becomes.
[0050]
Examples of such metal elements are listed below together with titanium data.
[0051]

TiO and TiO are titanium oxides ₂ , It can be seen that the latter has a lower standard generation enthalpy and is more stable. However, assuming that titanium is actually oxidized in the FRAM manufacturing process, the oxidation often proceeds in a non-equilibrium state exposed to plasma or the like. That is, it is considered that there are many occasions where TiO can be formed as an oxide of titanium.
[0052]
Thus, when TiO is formed as titanium oxide, the standard generation enthalpy of the oxide of any metal element described above is lower than that of TiO and forms an oxide that is more stable than titanium. Accordingly, if the buffer layer M2 is formed using any of these metal elements, the wiring layer M3 using titanium can be prevented from being oxidized. That is, the buffer layer M2 is preferentially oxidized over the wiring layer M3, or oxygen can be reliably received from the oxide of the wiring layer M3 and the oxygen can be prevented from being released.
[0053]
On the other hand, TiO as titanium oxide ₂ When TiO is formed ₂ Alternatively, the buffer layer M2 may be formed using a metal element having a lower standard generation enthalpy. In other words, if niobium (Nb), vanadium (V), chromium (Cr), and rhenium (Re) are used among the above-described metal elements, titanium is oxidized even when titanium can be oxidized to form TiO2. Can be prevented or reduced.
[0054]
Here, the position of the buffer layer M2 is also important. That is, the buffer layer M2 is provided between the contact layer M1 and the wiring layer M3, receives oxygen dissociated from the ferroelectric layer F and the contact layer M1, and prevents the wiring layer M3 from being oxidized. As will be described in detail later, an aluminum layer that is very easily oxidized is often formed on the wiring layer M3. However, the buffer layer M2 is dissociated by being provided on the contact layer M1 and the wiring layer M3. The diffusing oxygen can be completely received at this position. Therefore, oxidation of the wiring layer M3 and the aluminum layer thereon can be surely prevented.
[0055]
Note that the above-described elements are merely examples, and various other metal elements can be used in the same manner. Further, a layer made of two or more kinds of metal elements may be stacked.
[0056]
On the other hand, as the material of the wiring layer M3, titanium nitride (TiN) and other various barrier metals or wiring materials can be used in addition to titanium. In any case, the wiring layer M3 is more easily oxidized than the wiring layer M3. A similar effect can be obtained by employing a metal element as the second metal element.
[0057]
From the viewpoint of the electrical resistance of the electrode, it is desirable that the electrical resistance of the oxide of the second metal element is lower than the electrical resistance of the third metal element. In other words, the buffer layer M2 is preferentially oxidized over the wiring layer M3 to prevent the wiring layer M3 from being oxidized, but the electric resistance of the oxide of the buffer layer M2 is lower than that of the wiring layer M3. If the material is selected in such a manner, the resistance of the electrode can be lowered as compared with the case where the wiring layer M3 is oxidized.
[0058]
For example, taking titanium as an example of the material of the wiring layer M3 as an example, the electrical conductivity of an oxide of titanium (such as TiO) has semiconductor or insulating properties. That is, the specific resistance is extremely high, and the specific resistance decreases as the temperature increases.
[0059]
On the other hand, there are metal elements whose oxide exhibits metal conductivity and whose resistivity is much lower. Examples of such metal elements are listed below: chromium (Cr), cesium (Cs), molybdenum (Mo), niobium (Nb), osmium (Os), lead (Pb), rubidium (Rb), rhenium ( Re), rhodium (Rh), ruthenium (Ru), tin (Sn), thallium (Tl), vanadium (V), and the like. These metal element oxides (eg, CrO 2, MoO 2, SnO 2, V 2 O 3, etc.) have metallic conductivity characteristics such that the specific resistance is low and the specific resistance increases with increasing temperature. Therefore, if the buffer layer M2 is formed using such a metal element, an increase in electrical resistance can be suppressed even if the buffer layer M2 is oxidized, and problems such as contact failure can be solved.
[0060]
(First embodiment)
Hereinafter, a specific example of the FRAM using the ferroelectric capacitor of the present invention will be described with reference to FIGS.
[0061]
2 to 7 are schematic process cross-sectional views showing the procedure for creating the FRAM of this embodiment.
[0062]
First, as shown in FIG. 2, after forming a semiconductor element such as a CMOS (not shown) on the silicon substrate 101, a first interlayer insulating film 201 is deposited.
[0063]
Next, as shown in FIG. 3, the first electrode layer E1 of the ferroelectric capacitor is formed. Specifically, as described above, a combination with platinum (Pt), iridium (Ir), or strontium ruthenium oxide (SRO) is effective. However, before forming the first electrode layer E1, a base layer 300 made of titanium (Ti) or titanium nitride (TiN) is formed on the interlayer insulating film 201, and the first electrode layer E1 is formed thereon. The forming method is effective. This is performed in order to prevent problems such as poor adhesion and film peeling when platinum or the like is directly deposited on the interlayer insulating film 201 as the first electrode layer E1.
[0064]
The structure of the first electrode E1 includes, for example, an SRO layer / Pt layer, lrO, in order from the insulating film 201 in addition to a Pt single layer, an lr single layer, etc. ₂ A laminated structure such as a layer / lr layer may be mentioned. However, when the ferroelectric layer F is deposited, a larger polarization is obtained when the base is oriented in the <111> direction. From this point of view, it is advantageous to dispose platinum having self-orientation in the uppermost layer of the first electrode layer E1.
[0065]
Next, the ferroelectric layer F is formed. As the material of the ferroelectric layer F, PZT, strontium bismaster titanate oxide (bismuth-based layered perovskite, hereinafter referred to as SBT) or the like is suitable. Examples of the deposition method include a sputtering method, a sol-gel method, and a MOCVD (metal-organic chemical vapor deposition) method. The ferroelectric layer F thus deposited is crystallized, for example, by annealing at 700 ° C. for about one hour in an oxygen atmosphere at atmospheric pressure.
[0066]
Next, a contact layer (first layer) M1 of the second electrode layer E2 is deposited. Here, if the structure of the second electrode layer E2 is the same as that of the first electrode layer, the symmetry is good. However, when platinum is used for the contact layer M1 of the second electrode layer E2, fatigue characteristics of repeated writing / reading are not good as described above. Therefore, the contact layer M1 of the second electrode layer E2 is made of iridium oxide (IrO ₂ ) Or a laminated structure in which an iridium oxide layer and an iridium layer are laminated in order from the bottom. The illustrated example shows a structure in which an iridium oxide layer 43 and an iridium layer 44 are stacked.
[0067]
Next, as shown in FIG. 4, the contact layer M1, the ferroelectric layer F, and the first electrode layer E1 are patterned. Specifically, a mask (not shown) is sequentially formed by a photolithography process, and the contact layer M1, the ferroelectric layer F, and the first electrode layer E1 are sequentially etched by anisotropic etching such as RIE (reactive ion etching). To do. The illustrated example shows a pattern formed by three photolithography processes and respective etchings. However, in addition to this, the structure may be formed by two or one photolithography process and etching. .
[0068]
Next, as shown in FIG. 5, a second interlayer insulating film 202 is deposited, and a contact hole 202H to the first layer M1 and the first electrode E1 is opened by etching. Then, a buffer layer (second layer) M2 is deposited in the contact hole 202H. As described above, the material of the buffer layer M2 is 1) more easily oxidized than the metal element constituting the contact layer M1, 2) more easily oxidized than the metal element constituting the wiring layer M3, and 3) the wiring layer. A material satisfying that the specific resistance is lower than the oxide of the metal element constituting M3 is desirable. Specifically, as the buffer layer M2, for example, lead (Pb), tin (Sn), niobium (Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), rhenium (Re ) And the like can be deposited. Also, two or more layers of these metals may be stacked to form the buffer layer M2.
[0069]
Next, as shown in FIG. 6, a wiring layer (third layer) M3 is deposited. Specifically, for example, titanium (Ti) that acts as a barrier metal is deposited as the wiring layer. Further, the second wiring layer 500 is deposited to fill the contact hole 202H, and a deposited layer is formed on the wafer surface. As a material of the second wiring layer 500, it is desirable to use a metal having a low specific resistance such as aluminum (Al).
[0070]
Here, if the buffer layer M2 is not formed, the titanium of the wiring layer M3 deposited first on the contact layer M1 is oxidized. This is because the enthalpy of formation of the oxide of IrO2 is -168 kJ / mol in a steady state, which is, for example, less than one third of the formation enthalpy (-520 kJ / mol) at which titanium is oxidized. . That is, when titanium is deposited without the buffer layer M2, the following reaction easily occurs.
[0071]
IrO2 + 2Ti → Ir + 2TiO
Here, in order to prevent oxidation of titanium in the wiring layer M3, it is also conceivable to use a material that prevents oxygen diffusion as the buffer layer M2. That is, if the barrier layer against oxygen diffusion is used as the buffer layer M2, it is possible to prevent the wiring layer M3 from being oxidized. However, even when such a barrier material is deposited, the bottom edge portion of the contact hole 202H may be considerably thinner than the flat portion of the surface when deposited by sputtering. If a crystal grain boundary exists here, oxygen easily diffuses in the buffer layer and oxidizes the titanium layer thereon. Therefore, when a barrier material that prevents oxygen diffusion is used as the material of the buffer layer M2, it is necessary to increase the film thickness in order to prevent oxygen diffusion through crystal grain boundaries and the like.
[0072]
Assuming that the contact layer M1 is iridium oxide (IrO ₂ However, even when metal iridium (Ir) is used, the polarization amount of the ferroelectric layer F cannot be sufficiently obtained unless recovery annealing is performed in an oxygen atmosphere after opening the contact hole 202H. . Therefore, the bottom of the contact hole 202H is exposed to oxygen, and iridium oxide is always generated. That is, regardless of whether the contact layer M1 is metallic iridium or iridium oxide, a buffer layer M2 that receives oxygen dissociated from iridium oxide and does not release the oxygen is required.
[0073]
Next, as shown in FIG. 7, the second wiring layer 500 is patterned, an interlayer insulating layer (not shown) is further deposited, and a wiring layer is appropriately formed to complete the FRAM. A semiconductor element (not shown) such as a CMOS is formed on the silicon substrate 101 and is connected to each electrode of the ferroelectric capacitor via a wiring path (not shown).
[0074]
As described above, according to the present embodiment, the oxidation of the wiring layer M3 can be prevented by depositing the buffer layer M2 and the wiring layer M3 after providing the contact hole 202H in the interlayer insulating film. As a result, problems such as an increase in electrode resistance and contact failure can be solved.
[0075]
(Second embodiment)
Hereinafter, the configuration of the FRAM according to the second specific example of the present invention will be described along the manufacturing process with reference to FIGS. The FRAM of this specific example has a COP (Capacitor On Plug) structure in which a ferroelectric capacitor is provided on a contact plug of a silicon substrate on which a semiconductor element is formed.
[0076]
8 to 13 are schematic process cross-sectional views showing the procedure for creating the FRAM of this example. In these drawings, the same parts as those described above with reference to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.
[0077]
In this specific example, first, a semiconductor element (not shown) such as CMOS is formed on the silicon substrate 101, and then a first interlayer insulating layer 201 is deposited as shown in FIG. A buried contact 201P is formed by forming a contact hole in the interlayer insulating layer 201 and filling it with a conductive material.
[0078]
Next, as shown in FIG. 9, a ferroelectric capacitor portion is formed. Specifically, first, a barrier layer 302 that does not oxidize the buried contact 201P is deposited, and a first electrode layer E1, a ferroelectric layer F, a contact layer M1, and a buffer layer M2 are formed thereon in this order. To do. As a material of the barrier layer 302, titanium nitride (TiN _x ), Aluminum nitride (AlN _x ), Aluminum titanium nitride (AlTi) _y N _x ) Tungsten nitride (WN) _x ) Or niobium nitride (NbN) _x ) Etc. can be used.
[0079]
For the first electrode layer E1, the ferroelectric layer F, the contact layer M1, and the buffer layer M2, the materials described above can be used as appropriate.
[0080]
In this embodiment, unlike the first embodiment described above, the buffer layer M2 is previously deposited at this stage. This is because, in this embodiment, the capacitor has a COP structure on the contact plug 201P, and the wiring from the silicon substrate 101 to the first electrode layer E1 is formed in advance. This is because only the wiring to the electrode layer E2 needs to be considered.
[0081]
Next, as shown in FIG. 10, the buffer layer M2, the contact layer M1, the ferroelectric layer F, and the first electrode layer E1 are patterned.
[0082]
Next, as shown in FIG. 11, a second interlayer insulating layer 202 is deposited, and a contact hole 202H to the capacitor electrode is opened by etching.
[0083]
Next, as shown in FIG. 12, the wiring layer M3 and the second wiring layer 500 are deposited by a method such as sputtering, and the contact hole 202H is filled and further deposited.
[0084]
Finally, as shown in FIG. 13, the wiring layer M3 and the second wiring layer 500 are patterned, an interlayer insulating layer (not shown) is further deposited, and the wiring layer is appropriately formed to complete the FRAM.
[0085]
The embodiments of the present invention have been described with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the material of each layer constituting the ferroelectric capacitor is not limited to the specifically listed materials, and similar effects can be obtained by using all materials that can be selected by those skilled in the art according to the gist of the present invention. be able to.
[0086]
Further, the ferroelectric capacitor is not limited to the one mounted on the ferroelectric memory (FRAM), and the same function and effect can be obtained for the one mounted on all other devices.
[0087]
In addition, all the ranges that can be selected by those skilled in the art based on the idea of the present invention can be included in the present invention.
[0088]
【The invention's effect】
As described above in detail, according to the present invention, by providing a buffer layer that reliably receives oxygen dissociated from the oxide ferroelectric and the contact layer in contact therewith, oxidation of the barrier layer and the like of the metal wiring is performed. It can be reliably and easily prevented. As a result, an increase in electrode resistance and contact failure can be eliminated.
[0089]
According to the present invention, there is provided a ferroelectric memory that reduces contact resistance and significantly improves contact yield even when using an iridium electrode that easily releases oxygen, and also has excellent repetitive write / read characteristics. can do.
[0090]
That is, according to the present invention, it is possible to provide a ferroelectric capacitor and a memory that are excellent in reliability and improved in manufacturing yield.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing a cross-sectional configuration of a main part of a dielectric capacitor of the present invention.
FIG. 2 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a first embodiment of the present invention.
FIG. 3 is a schematic process cross-sectional view showing the procedure for creating the FRAM according to the first embodiment of the present invention.
FIG. 4 is a schematic process cross-sectional view showing the procedure for creating the FRAM according to the first embodiment of the present invention.
FIG. 5 is a schematic process cross-sectional view showing the procedure for creating the FRAM according to the first embodiment of the present invention.
FIG. 6 is a schematic cross-sectional process diagram illustrating a procedure for creating the FRAM according to the first embodiment of the present invention.
FIG. 7 is a schematic process cross-sectional view showing the procedure for creating the FRAM according to the first embodiment of the present invention.
FIG. 8 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 9 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 10 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 11 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 12 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 13 is a schematic cross-sectional process diagram illustrating a procedure for creating an FRAM according to a second embodiment of the present invention.
FIG. 14 is a conceptual diagram showing a cross-sectional structure of a main part of a conventional FRAM.
[Explanation of symbols]
10 Ferroelectric capacitor
E1 first electrode layer
F Ferroelectric layer
E2 Second electrode layer
M1 first layer (contact layer)
M2 second layer (buffer layer)
M3 Third layer (wiring layer)
101 substrate
201 first interlayer insulating layer
201P embedded plug
202 Second interlayer insulating layer
202H Contact hole
300, 302, 400 Underlayer
401 Lower electrode
402 Ferroelectric layer
403, 404 Upper electrode
480 Barrier layer
500 Wiring layer

Claims (6)

A first electrode layer;
A ferroelectric layer provided on the first electrode layer;
A first layer provided on the ferroelectric layer and containing at least one of iridium (Ir) and an oxide thereof;
A second layer provided on the first layer and containing at least one of a second metal element or an oxide thereof;
A third layer which is provided on the second layer and mainly contains a third metal element;
With
The second metal element includes thallium (Tl), lead (Pb), rubidium (Rb), cesium (Cs), tin (Sn), ruthenium (Ru), rhodium (Rh), osmium (Os), niobium ( A ferroelectric capacitor characterized by being at least one selected from the group consisting of Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), and rhenium (Re). A first electrode layer;
A ferroelectric layer provided on the first electrode layer;
A first layer provided on the ferroelectric layer and containing at least one of a first metal element and an oxide thereof;
A second layer provided on the first layer and containing at least one of a second metal element or an oxide thereof;
A third layer which is provided on the second layer and mainly contains a third metal element;
With
The first metal element is iridium (Ir),
The third metal element is titanium (Ti),
The second metal element is at least selected from the group consisting of chromium (Cr), molybdenum (Mo), niobium (Nb), lead (Pb), rhenium (Re), tin (Sn), and vanadium (V). A ferroelectric capacitor comprising any one of the above.   3. The ferroelectric capacitor according to claim 1, wherein the second metal element has a specific resistance of an oxide lower than a specific resistance of the oxide of the third metal element. 4. Forming a first layer containing at least one of iridium (Ir) or an oxide thereof on the ferroelectric layer;
Heat-treating the ferroelectric layer in an atmosphere containing oxygen;
Forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer;
Forming a third layer mainly composed of a third metal element on the second layer;
With
The second metal element includes thallium (Tl), lead (Pb), rubidium (Rb), cesium (Cs), tin (Sn), ruthenium (Ru), rhodium (Rh), osmium (Os), niobium ( Nb), vanadium (V), bismuth (Bi), molybdenum (Mo), chromium (Cr), and at least one selected from the group consisting of rhenium (Re) Method. Forming a first layer containing at least one of the first metal element and its oxide on the ferroelectric layer;
Heat-treating the ferroelectric layer in an atmosphere containing oxygen;
Forming a second layer containing at least one of a second metal element or an oxide thereof on the first layer;
Forming a third layer mainly composed of a third metal element on the second layer;
With
The first metal element is iridium (Ir),
The third metal element is titanium (Ti),
The second metal element is at least selected from the group consisting of chromium (Cr), molybdenum (Mo), niobium (Nb), lead (Pb), rhenium (Re), tin (Sn), and vanadium (V). A method of manufacturing a ferroelectric capacitor comprising any of the above. A semiconductor substrate on which a semiconductor element is formed;
A first interlayer insulating layer provided on the semiconductor substrate;
The ferroelectric capacitor according to any one of claims 1 to 3 , provided on the first interlayer insulating layer;
A low resistance metal wiring layer provided on the third layer;
A ferroelectric memory characterized by comprising:

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