JP2000228506A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, together with a method for manufacturing it, wherein oxidation of a contact plug is prevented to realize a low- resistance contact. SOLUTION: With an inter-layer insulating film 2 on a semiconductor substrate 1 as well as a contact 3 formed on a desired position of the inter-layer insulating film 2, a lower part electrode 5, capaciatance film 6, and upper part electrode 7 are laminated in this order on the inter-layer film 2 and the contact 3 to constitute a thin-film capacitor. Here, the lower part electrode 5 includes at least one hetero interfaces 10-1, 10-2, 10-3...10-n.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a dynamic random access memory (DRAM).
Alternatively, the present invention relates to a semiconductor device such as a nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view showing a capacitance portion of a memory cell of a conventional DRAM device. In FIG. 4, a transistor including a source, a drain, and a gate is omitted, and the source is connected to the bit line, the gate is connected to the word line, and the drain is connected to the contact plug 3, respectively.

A semiconductor substrate 1 on which an interlayer insulating film 2 is formed
The contact plug 3 is formed at a desired position for connecting the drain of the transistor to the capacitor. A barrier metal 4 and a lower electrode 5 which are three-dimensionally processed are provided on the contact plug 3, and a capacitance film 6 and an upper electrode 7 are formed thereon. Japanese Patent Laid-Open No. 5-2, which is a prior art
No. 35264 describes that a conductive oxide film is used as an electrode material. Further, between the lower electrode 5 made of a conductive oxide film and a portion made of silicon, the conductive oxide film is used. Structures with included metal silicides are described.

On the other hand, Japanese Patent Laid-Open Publication No.
657 describes a semiconductor device using palladium, an alloy of palladium and platinum, or a conductive oxide as an electrode material. If the area of the memory cell section is reduced to increase the degree of integration of the DRAM, the projected area of the capacitor section decreases accordingly.

[0005] Even if the area of the capacitor portion is reduced, it is effective to use a capacitor film having a high dielectric constant in order not to reduce the amount of charge stored in the capacitor portion. Ta ₂ O ₅ , SrTiO ₃ or (Ba, S
r) High permittivity films such as TiO ₃ are widely known. On the other hand, in recent years, Pb (Z
Ferroelectric films such as (r, Ti) O ₃ and SrBi ₂ Ta ₂ O ₉ are widely known. The conventional technology described above is
This is for applying the high dielectric constant film or the ferroelectric constant film mentioned here to a semiconductor device.

[0006]

Generally, since the high dielectric constant film or the ferroelectric constant film is an oxide dielectric containing oxygen, the lower electrode is formed during the formation of the capacitance film or the subsequent heat treatment process. Exposed to an oxidizing atmosphere. In Japanese Patent Application Laid-Open No. 5-235264, a conductive oxide film is used as an electrode material, and a conductive oxide film is provided between a lower electrode made of a conductive oxide film and a portion made of silicon. Although it has a metal silicide contained in the material film, the metal silicide is oxidized at the time of forming the capacitor film or by a heat treatment process in a later step.

Alternatively, there has been a problem that the silicon substrate itself is oxidized and the contact resistance is significantly increased. Similarly, in Japanese Patent Application Laid-Open No. 4-349657, which is a conventional technique, a semiconductor device using palladium, an alloy of palladium and platinum, or a conductive oxide as an electrode material is used. The oxidation resistance of these alloys is not sufficient, and there has been a problem that the contact plugs and the silicon substrate themselves are oxidized and the contact resistance is significantly increased.

Further, even when a conductive oxide is used as an electrode material, diffusion of oxygen at the time of forming a capacitance film or a subsequent heat treatment process or diffusion of oxygen of a conductive oxide film electrode results in There was a problem that the contact resistance was significantly increased. Japanese Patent Application Laid-Open No. 8-330544 discloses a structure of a high dielectric constant capacitor, and discloses that a RuO ₂ film layer is used as an intermediate layer of a lower electrode. There is no description of a technique for preventing oxygen permeation.

Japanese Patent Application Laid-Open Nos. 9-148535 and 10-173138 describe the use of a laminated film of IrO ₂ / Ir for a lower electrode of a capacitor in a semiconductor memory device. However, there is no description about a technique for forming a hetero interface formed by a Ru / IrO ₂ Ru film layer in an intermediate layer of a lower electrode to prevent oxygen from permeating.

Accordingly, an object of the present invention is to improve the above-mentioned disadvantages of the prior art, prevent oxidation of a contact plug,
An object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device which do not cause a decrease in the operation speed of a DRAM operation and a decrease in the amount of charge written to a capacitor portion by realizing a low-resistance contact.

[0011]

In order to achieve the above-mentioned object, the present invention employs the following basic technical structure. That is, a first aspect of a semiconductor device according to the present invention is an interlayer insulating film on a semiconductor substrate, a contact formed at a desired position on the interlayer insulating film, a lower electrode, a capacitor film on the interlayer film and the contact. And a thin film capacitor in which an upper electrode is laminated in this order, the lower electrode is a semiconductor device including at least one heterointerface in a part thereof, and a second aspect according to the present invention is as follows. A thin film capacitor in which an interlayer insulating film on a semiconductor substrate, a contact formed at a desired position on the interlayer insulating film, a lower electrode, a capacitor film, and an upper electrode are laminated in this order on the interlayer film and the contact. When manufacturing, a metal oxide selected from a group of metal elements which exhibit properties of a conductive metal oxide when oxidized is formed on the interlayer insulating film and at a position where the contact exists. To a method of manufacturing a semiconductor device alternately stacking individual film layers containing different metal elements.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device according to the present invention employs the above-described technical configuration, and thus includes a step of finely processing a lower electrode, a step of forming an oxide high dielectric constant thin film, and the like. In the process of forming the capacitor portion, or in the heat treatment process after the electrode wiring process after forming the capacitor portion, the barrier metal and the contact plug under the lower electrode are oxidized via the lower electrode. By forming at least one hetero interface in the present invention,
Oxygen is trapped at the hetero interface and does not pass through the inside of the lower electrode, thereby preventing the barrier metal layer and the contact layer from being oxidized and having a high resistance.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a specific example of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. That is, FIG. 1 is a cross-sectional view showing a configuration of a specific example of the semiconductor device according to the present invention. In the drawing, an interlayer insulating film 2 on a semiconductor substrate 1 In the thin film capacitor in which the lower electrode 5, the capacitor film 6, and the upper electrode 7 are laminated in this order on the formed contact 3, the interlayer film 2, and the contact 3, the lower electrode 5 is partially formed. At least one heterointerface 10-1, 10-
A semiconductor device 20 including 2, 10-3,..., 10-n is shown.

In the present invention, the hetero interface 10 preferably has a function of trapping an oxygen component. Therefore, the hetero interface 10 in the present invention is:
This is a bonding surface formed by bonding individual film layers containing different metal elements selected from a group of metal elements that exhibit properties of a conductive metal oxide when oxidized.

In the present invention, the metal element which exhibits the properties of a conductive metal oxide when oxidized is, for example, Ru, I
Desirably, it is a plurality of metals selected from r and Os. In the present invention, the hetero interface 10 in the lower electrode 5 may be formed by laminating a plurality of stages parallel to the surface of the substrate 1 or may be formed in the lower electrode 5. The hetero interface 10 may be a multi-layered structure surrounding the film layer 15 made of a metal element exhibiting the properties of the conductive metal oxide which forms the lowermost stage of the lower electrode 5.

That is, the plurality of heterointerfaces 10-1, 10-2, 10-3,..., 10-n according to the present invention.
Is desirably formed by alternately stacking film layers made of metal elements exhibiting different properties of the conductive metal oxide. For example, Ru / Ir / Ru / Ir /
It is configured like Ru. The thickness, size, and the like of each film layer according to the present invention are not particularly limited.

Further, as another specific example of the present invention, a film layer 10-1 or 1 made of a metal element having a property of a plurality of mutually different conductive metal oxides constituting the hetero interface is provided.
At least a part of 0-2, 10-3,..., 10-n is a film composed of the metal previously oxidized, for example, Ru.
It may contain O ₂ . Specifically, the film layer composed of the pre-oxidized conductive metal oxide,
It is desirable to be arranged so as to be in contact with the capacitance film 6.

In the semiconductor device 20 according to the present invention, an appropriate barrier metal layer 4 may be present between the lower electrode 5 and the contact 3. Hereinafter, a specific example of the semiconductor device 20 according to the present invention will be described in more detail. That is, FIG. 1 is a cross-sectional view of a capacitance section for explaining one embodiment of the present invention. On the semiconductor substrate 1 on which the interlayer insulating film 2 is formed, there is a contact plug 3 made of polysilicon for connecting the drain region of the transistor and the capacitor at a desired position on the interlayer insulating film 2. Is formed with a barrier metal 4 having good adhesion to an interlayer insulating film and a barrier metal of silicon and oxygen, and a lower electrode 5.

In this embodiment, the barrier metal is TiN / T
i laminated film (Ti / Si interface is TiSix), lower electrode is 50 nm thick Ru and 10 nm Ir
Are sequentially laminated, and the total thickness of the lower electrode is 650.
nm. The lower electrode and the barrier metal are three-dimensionally processed by a dry etching method. A capacitance film 6 and an upper electrode 7 are formed so as to cover the lower electrode 5 and the barrier metal 4.

In this embodiment, (Ba _0.5 ,
An Sr _0.5 ) TiO ₃ film was used and Ru was used as an upper electrode. As a method of forming the capacitance portion of the present embodiment, a hole is formed at a desired position of the interlayer insulating film 2 so as to reach the drain region of the transistor by using a normal photolithography technique and a dry etching technique, and the polysilicon is formed. A contact plug is formed by silicon film formation and an etch-back technique.

Thereafter, a barrier metal 4 of TiN / Ti is formed by a normal sputtering method, and after heat treatment, a lower electrode 5 in which Ru / Ir is alternately laminated by a sputtering method is formed by a sputtering method. Thereafter, the lower electrode is finely processed by a normal photolithography technique and a dry etching technique. Subsequently, a (Ba _0.5 , Sr _0.5 ) TiO ₃ capacitance film was formed by a sputtering method at a film formation temperature of 400 ° C., and a Ru upper electrode was formed by a sputtering method.

Thereafter, the upper electrode 7 was dry-etched to a desired size. After processing the lower electrode 5, the contact plug 3 and the lower electrode 5 are set as one set for the sample after processing.
00, 2000, and 3000 contact measurement series patterns were formed, and the contact resistance was measured. Similarly, after forming up to the upper electrode 7, an interlayer film was formed and a thermal process assumed in a DRAM process was applied. Then, a series pattern for contact measurement was formed, and the contact resistance was measured.

As a result, the contact resistance is changed to the capacity film formation,
In addition, it did not change at all even after the heat treatment process, and showed low resistance depending only on the initial contact plug formation process. Next, the semiconductor device 2 according to the present invention
Another specific example of 0 will be described. That is, FIG. 2 is a cross-sectional view of the capacitor for explaining the second embodiment of the present invention.

On the semiconductor substrate 1 on which the interlayer insulating film 2 is formed, there is a contact plug 3 formed of polysilicon for connecting the drain region of the transistor and the capacitor at a desired position on the interlayer insulating film 2. On the plug 3, a barrier metal 4 having good adhesion to the interlayer insulating film and a barrier metal for silicon and oxygen and a lower electrode 5 are formed.

In this embodiment, the barrier metal is TiN / T
i-layer film (Ti / Si interface is TiSix)
After a Ru film having a thickness of 500 nm was formed thereon, Ru and a barrier metal were three-dimensionally finely processed. Subsequently, a structure in which Ru with a film thickness of 20 nm and Ir with a thickness of 10 nm are sequentially laminated so as to cover the lower electrode / barrier metal processed three-dimensionally.

A capacitance film 6 and an upper electrode 7 are formed so as to cover the lower electrode 5 and the barrier metal 4. In this embodiment, a (Ba _0.5 , Sr _0.5 ) TiO ₃ film is used as the capacitor film, and Ru is used as the upper electrode. As a method of forming the capacitance portion of the present embodiment, a hole is formed at a desired position of the interlayer insulating film 2 so as to reach the drain region of the transistor by using a normal photolithography technique and a dry etching technique, and the polysilicon is formed. A contact plug is formed by silicon film formation and an etch-back technique.

Thereafter, a barrier metal 4 of TiN / Ti is formed by a normal sputtering method, and after heat treatment, Ru is formed to a thickness of 500 nm by the sputtering method. Thereafter, the lower electrode is finely processed by a normal photolithography technique and a dry etching technique. Then, Ru is sputtered.
/ Ir is sequentially formed, and then Ru / Ir deposited on the interlayer insulating film 2 by etch back by dry etching.
The laminated film was removed. A (Ba _0.5 , Sr _0.5 ) TiO ₃ capacitance film is formed by a sputtering method at a film formation temperature of 400 ° C.
The u upper electrode was formed by a sputtering method.

Thereafter, the upper electrode was dry-etched to a desired size. The contact resistance of this sample was compared and measured using the same method as in Example 1. As a result, the contact resistance did not change at all even after the formation of the capacitor film and the heat treatment process, and depended only on the initial contact plug formation process. Low resistance was realized. next,
A third specific example according to the present invention will be described with reference to FIG.

FIG. 3 illustrates a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of a capacitor unit for the second embodiment. Different from the second embodiment
Is that the lower electrode 5 of the second embodiment is Ru / Ir / Ru / Ir /
In contrast to the case where it was formed of a Ru laminated film,
Is RuO_Two / Ir / Ru / Ir / Ru
It is. That is, the electrode in contact with the capacitance film 6 and the lower electrode 5 is
RuO, a conductive oxide film electrode _TwoIt has become. Other
Is the same as that of the second embodiment.

However, when forming the capacitance section 6, a (Ba _0.5 , Sr _0.5 ) TiO ₃ capacitance film was formed by a sputtering method at a film formation temperature of 550 ° C. (Ba _0.5 , S
( _0.5 ) As a result of increasing the film formation temperature of the TiO ₃ capacitor film, a very high dielectric constant was shown, and it was confirmed that there was no increase in contact resistance due to the film formation of the capacitor film and the subsequent thermal process.

Next, a fourth embodiment according to the present invention will be described with reference to FIG. That is, FIG. 5 is a cross-sectional view showing a configuration of a fourth specific example according to the present invention.
A first interlayer insulating film 2 above, a contact 3 formed at a desired position on the first interlayer insulating film 2, the first interlayer insulating film 2, and a second interlayer insulating film provided on the contact 3 8, a thin film capacitor in which a wiring groove 11 formed at a position facing the contact 3 and a lower electrode 5, a capacitor film 6, and an upper electrode 7 are laminated in this order along the inner wall 9 of the wiring groove 11. 1 shows a semiconductor device 20 in which the lower electrode 5 includes at least one heterointerface 10 in a part thereof.

In the present embodiment, the configuration and material of each of the main components including the formation of the hetero interface 10 may be the same as those in the above-described embodiment. , In each embodiment described above, as a capacitor film 6 (Ba, Sr) was used TiO _3, the present invention is Ta ₂
A widely known high dielectric constant oxide film or ferroelectric constant oxide film such as O ₅ or Pb (Zr, Ti) O ₃ may be used.

Further, in the present invention, a Ru / Ir laminated structure is used, but the present invention is not limited to this, but Ru, Ir, Os
Rux Ir1-x, Ru composed of an element forming a conductive metal oxide such as, or an element forming a conductive metal oxide.
A combination of at least non-identical metal films such as alloys having different mixed crystal compositions such as yIr1-y, RuxOs1-x, and RuyOs1-y may be used.

Further, in the present invention, the barrier metal 4
Although TiN / Ti and polysilicon were used for the contact plug 3 and the contact plug 3, respectively, the present invention is not limited to this, and a single-layer film made of Ta, Ti, W, or a nitride film thereof, or two or more kinds is used as a barrier metal. A stacked film may be used in combination, and the contact plug may be a single-layer film made of Ta, Ti, W or a nitride film thereof, or a silicide film, or a stacked film formed by combining two or more types.

Further, a barrier metal and a contact plug
May be the same material, as shown in this embodiment.
Barrier metal and contact plug on top of interlayer insulating film
It is not necessary to divide them clearly. In the present invention, the conductive
RuO as an oxide film_TwoBut the present invention is not limited to this.
Not SrRuO_Three Perovskite oxidation
Membrane, Pb_TwoRu_TwoO ₇Pyrochlore-type oxidation
Thing, RuO_TwoAnd IrO_TwoAcid such as metal oxide film represented by
What is necessary is just to show electroconductivity even after formation.

In the present invention, the sputtering method is used for forming the electrode and the capacitor film. However, the present invention is not limited to this, and a vapor phase growth method or a sol-gel method may be used. As described above, for example, Ru and Ir as metal elements which exhibit the properties of a conductive oxide film even when oxidized, oxygen hardly stays in the crystal phase when oxidized, and TiN or Ti formed under Ru is used. Reaches the barrier contact plugs of the barrier metal and the polycrystalline silicon, which are oxidized to increase the resistance.

On the other hand, when different kinds of elements are stacked as in the present invention, a hetero interface (Ru / Ir) between different element layers is formed.
An interface is formed and oxygen is trapped at this interface. Therefore, the oxygen atoms that have entered the lower electrode are prevented from reaching the barrier metal below the electrode. Further, as in the second embodiment of the present invention, the side surface of the three-dimensionally processed lower electrode 5 also has a hetero interface (Ru) between different element layers.
/ Ir interface can also be prevented from oxidizing from the side surface.

Further, in the third embodiment of the present invention, a conductive oxide film is used as an electrode layer in which the capacitance film 6 and the lower electrode 5 are in contact with each other. In particular, a dielectric oxide film is used as the capacitance film. When the lower electrode is directly exposed to an oxidizing atmosphere at the time of forming the capacitor film, as in the case where the capacitor is used, the oxidation resistance is improved and is effective.

[0039]

In the step of finely processing the lower electrode, the step of forming a capacitor such as the step of forming an oxide high dielectric constant thin film, or the heat treatment step after the electrode wiring step after the formation of the capacitor, There is a problem that the barrier metal and the contact plug under the lower electrode are oxidized via the lower electrode and the conductivity is deteriorated. However, this oxidation is prevented and a low-resistance contact is realized. The increase in the contact resistance causes problems such as a reduction in the operation speed of the DRAM operation and a reduction in the amount of charge written to the capacitor portion. The present invention prevents this.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a specific example of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing a configuration of another specific example of the semiconductor device of the present invention.

FIG. 3 is a sectional view showing a configuration of another specific example of the semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 5 is a sectional view showing the configuration of still another specific example of the semiconductor device of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 interlayer insulating film, first interlayer insulating film 3 contact plug 4 barrier metal 5 lower electrode 6 capacitance film 7 upper electrode 8 second interlayer insulating film 9 inner wall 10 hetero Interface 11: Wiring groove 15: Film layer 20: Semiconductor device

Claims (16)

[Claims] An interlayer insulating film on a semiconductor substrate, a contact formed at a desired position on the interlayer insulating film, a lower electrode, a capacitor film, and an upper electrode are laminated in this order on the interlayer film and the contact. Thin film capacitors,
A semiconductor device, wherein the lower electrode includes at least one heterointerface in a part thereof. 2. The semiconductor device according to claim 1, wherein the hetero interface has a function of trapping an oxygen component. 3. The heterointerface is formed by joining individual film layers containing different metal elements selected from a group of metal elements that exhibit properties of a conductive metal oxide when oxidized. 3. A joint surface according to claim 2,
13. The semiconductor device according to claim 1. 4. The metal element exhibiting the property of a conductive metal oxide when oxidized is a plurality of metals selected from Ru, Ir, and Os. 3. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein said hetero interface in said lower electrode is formed by laminating a plurality of stages in parallel with said substrate surface. . 6. The hetero interface in the lower electrode is multi-layered so as to surround a film layer made of a metal element exhibiting the properties of the conductive metal oxide forming the lowermost stage of the lower electrode. The semiconductor device according to claim 1, wherein: 7. The plurality of heterointerfaces are formed by alternately laminating film layers made of metal elements exhibiting different properties of the conductive metal oxide. 7. The semiconductor device according to 5 or 6. 8. At least a part of a film layer made of a metal element exhibiting properties of a plurality of mutually different conductive metal oxides constituting the hetero interface is a film made of the metal which has been oxidized in advance. The semiconductor device according to claim 7, wherein the semiconductor device includes: 9. The semiconductor device according to claim 8, wherein the film layer made of the pre-oxidized conductive metal oxide is arranged so as to be in contact with the capacitance film. 10. The semiconductor device according to claim 1, wherein a barrier metal layer exists between said lower electrode and said contact. 11. An interlayer insulating film on a semiconductor substrate, wherein the first
A contact formed at a desired position of the interlayer insulating film, a wiring groove formed at a position facing the contact in the first interlayer insulating film and a second interlayer insulating film provided on the contact, and the wiring A lower electrode along the inner wall of the groove,
In a thin film capacitor in which a capacitance film and an upper electrode are stacked in this order, the lower electrode partially includes at least one hetero interface. 12. The device according to claim 1, wherein the hetero interface has a function of trapping an oxygen component.
2. The semiconductor device according to 1. 13. The heterointerface is formed by joining individual film layers containing different metal elements selected from a group of metal elements exhibiting properties of a conductive metal oxide when oxidized. 2. A joint surface according to claim 1,
3. The semiconductor device according to 2. 14. The metal element exhibiting the property of a conductive metal oxide when oxidized is a plurality of metals selected from Ru, Ir, and Os.
The semiconductor device according to any one of the above. 15. An interlayer insulating film on a semiconductor substrate, a contact formed at a desired position on the interlayer insulating film, a lower electrode, a capacitor film, and an upper electrode laminated in this order on the interlayer film and the contact. In manufacturing the thin film capacitor, a different metal selected from a group of metal elements exhibiting the properties of a conductive metal oxide when oxidized is formed on the interlayer insulating film and at a position where the contact exists. A method for manufacturing a semiconductor device, wherein individual film layers containing elements are alternately stacked. 16. The semiconductor device according to claim 15, wherein the metal element exhibiting the property of a conductive metal oxide when oxidized is a plurality of metals selected from Ru, Ir, and Os. Manufacturing method.