JPH10189886A - Dielectric capacitor and ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent diffusion into a lower electorde of Si, etc. and oxidation at the time of heat treatment by composting a dielectric capacitor of the lower electrode consisting of a material, in which composition formula is expressed by, formula I and a composition range in expressed by a formula II, a ferroelectric film made up of a Bi-based layer structure perovskite type ferroelectric and an upper electrode. SOLUTION: A Ti Film 2 as a junction layer, a Pti-x Rux film 3 as a lower electrode, an STB film 4 of a Bi layer-structure perovskite type ferroelectric as a ferroelectric film, and a Pt film 5 at an upper electrode are laminated on a conductive Si substrate 1, thus constituting a capacitor. The lower electorde is composed of a material, in which composition formula is expressed by a formula I and a composition range by a formula II. The Pt1-x Rux film 3 is formed within the composition range of 0.3<=x<=1 and y=z=0 in an embodiment. Accordingly, when heat treatment is conducted for crystallization at the time of the formation of the SBT film 4, reaching onto the top face of the Pt1-x Rux film 3 by a thermal diffusion of Si from the Si substrate 1 is prevented, and the deterioration of the capacitor characteristic is obviated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric capacitor and a ferroelectric memory.

[0002]

2. Description of the Related Art A ferroelectric memory is a high-speed rewritable nonvolatile memory utilizing a high-speed polarization reversal of a ferroelectric film and its residual polarization. FIG. 4 shows an example of a conventional ferroelectric memory.

As shown in FIG. 4, in this conventional ferroelectric memory, a field insulating film 102 is selectively provided on the surface of a p-type Si substrate 101, thereby performing element isolation. On the surface of the active region in a portion surrounded by the field insulating film 102, the gate insulating film 1 is formed.
03 is provided. Symbol WL indicates a word line. The p-type Si substrate 10 on both sides of the word line WL
In 1, an n ⁺ type source region 104 and a drain region 105 are provided. The word line WL, the source region 104 and the drain region 105 form a transistor Q.

Reference numeral 106 denotes an interlayer insulating film. Interlayer insulating film 106 in a portion above field insulating film 102
On top, for example, a Ti layer having a thickness of about 30 nm is used as a bonding layer.
Through the film 107, for example, a film thickness of 200 as a lower electrode
Pt film 108 having a thickness of about 200 nm, such as a Pb (Zr, Ti) O ₃ (PZT) film or SrBi ₂ Ta having a thickness of about 200 nm.
_A ferroelectric film 109 such as a ₂ O ₉ (SBT) film and a Pt film 110 having a thickness of, for example, about 200 nm as an upper electrode.
Are sequentially laminated, and the Pt film 108 and the ferroelectric film 1 are stacked.
09 and the Pt film 110 constitute a capacitor C. With the transistor Q and this capacitor C,
One memory cell is configured.

Reference numeral 111 denotes an interlayer insulating film. A contact hole 112 is provided in the interlayer insulating film 106 and the interlayer insulating film 111 above the source region 104. Further, a contact hole 113 is provided in the interlayer insulating film 111 at a portion above one end of the Pt film 108. Further, a contact hole 114 is provided in the interlayer insulating film 111 above the Pt film 110. Then, through the contact holes 112 and 113, the source region 104 of the transistor Q and the Pt film 10 serving as the lower electrode of the capacitor C are formed.
8 are connected by a wiring 115. Further, a wiring 116 is connected to the Pt film 110, which is the upper electrode of the capacitor C, through the contact hole 114. Reference numeral 117 denotes a passivation film.

In the conventional ferroelectric memory shown in FIG. 4, the transistor Q and the capacitor C are arranged side by side (in a direction parallel to the substrate surface). In order to increase the number, it is necessary to adopt a structure in which the transistor Q and the capacitor C are arranged side by side in the vertical direction (the direction perpendicular to the substrate surface). An example is shown in FIG. Here, in FIG. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals.

In FIG. 5, reference numerals WL1 to WL4 denote word lines, and 118 denotes an interlayer insulating film. Drain region 105
A contact hole 119 is formed in the interlayer insulating film 118 in the upper portion of the transistor Q through the contact hole 119 to connect the bit line BL to the drain region 1 of the transistor Q.
05. Reference numerals 120 and 121 indicate interlayer insulating films. A contact hole 122 is provided in the interlayer insulating film 121 above the source region 104, and a polycrystalline Si plug 123 is formed in the contact hole 122.
Is embedded. And this polycrystalline Si plug 1
Through 23, the source region 104 of the transistor Q and the Pt film 108, which is the lower electrode of the capacitor C, are electrically connected.

[0008]

The ferroelectric film 10 will now be described.
9 is usually formed at 600 to
It is necessary to perform a heat treatment at a high temperature of 800 ° C. in an oxidizing atmosphere.
Thermally diffuses into the Pt film 108, which is the lower electrode of the capacitor C, and the Si reaches the upper surface of the Pt film 108 and is oxidized.
There is a problem that i further diffuses into the ferroelectric film 109 and the characteristics of the capacitor C are remarkably deteriorated.

When the material of the ferroelectric film 109 is PZT, the firing temperature is about 600 ° C., and it is reported that a nitride film such as TiN can be used as a Si diffusion preventing layer. There are (Abstracts of the JSAP,
Spring 1995, 30p-D-20, 30p-D-1
0). However, the nitride-based film is oxidized by heat treatment in an oxidizing atmosphere at a high temperature and loses conductivity. Therefore, in order to further improve the ferroelectric characteristics of the ferroelectric film 109, the nitride-based film has a sufficient heat treatment atmosphere. When oxygen is introduced and heat treatment is performed at a higher temperature, there is a problem that surface roughness and electrical resistance increase due to oxidation.

On the other hand, as a material of the ferroelectric film 109, P
When using SBT which is considered to have better fatigue characteristics than ZT, the heat treatment temperature for obtaining good ferroelectric characteristics is 7 ° C.
The temperature is about 50 to 800 ° C., which is higher than that of PZT. Therefore, when SBT is used as the material of the ferroelectric 109, the diffusion prevention layer made of the above-mentioned nitride-based film has a completely insufficient heat resistance and cannot be used. For these reasons, a stack-type capacitor structure using SBT as a material for the ferroelectric film 109 has not been reported so far, and a highly integrated nonvolatile memory using such a capacitor has not been realized. It was said to be difficult.

The same problem as described above can also occur when a W plug is used instead of a polycrystalline Si plug.

Therefore, an object of the present invention is to provide a case where a transistor and a dielectric capacitor are arranged vertically and a lower electrode of the dielectric capacitor is connected to a diffusion layer of the transistor by a plug made of Si or W. Even if a high-temperature heat treatment is performed in an oxidizing atmosphere during the formation of the body film, it is possible to prevent Si or W from diffusing from the plug into the lower electrode, reaching the upper surface thereof and being oxidized. To provide a dielectric capacitor that can use a Bi-based layered structure perovskite ferroelectric such as SBT as a material for a ferroelectric film of a dielectric capacitor, and a ferroelectric memory using such a dielectric capacitor. is there.

[0013]

Means for Solving the Problems The present inventor has made intensive studies in order to solve the above-mentioned problems of the prior art. The outline is described below.

In order to arrange the transistor and the dielectric capacitor side by side in the vertical direction and connect the lower electrode of the dielectric capacitor to the diffusion layer of the transistor by using a polycrystalline Si plug, the polycrystalline Si plug must be connected to the upper surface of the lower electrode. Si
Is required to be prevented, but as described above, this cannot be prevented by the lower electrode made of the Pt film.

As a result of various studies, the present inventor has found that the lower electrode is formed of Ru or an alloy of Ru and a noble metal such as Pt, Ir, Rh, etc., so that the transistor and the dielectric capacitor are vertically connected. When the lower electrodes of the dielectric capacitors are arranged side by side and connected to the diffusion layer of the transistor by a polycrystalline Si plug, even if a high-temperature heat treatment is performed in an oxidizing atmosphere for crystallization of SBT, the polycrystalline Si plug It has been found that diffusion of Si into the upper surface of the lower electrode can be prevented. This is considered to be because Ru is selectively oxidized on the upper surface of the lower electrode during the heat treatment, and as a result, diffusion of Si to the upper surface of the lower electrode is prevented. That is, the Si of the polycrystalline Si plug diffuses into the lower electrode but does not reach the upper surface thereof. Therefore, the material of the ferroelectric film of the dielectric capacitor is S
Even when BT is used, a good operation of the dielectric capacitor can be achieved.

As a material for the ferroelectric film, (Ba, S
r) In a dielectric capacitor using TiO ₃ (BST), a transistor and a dielectric capacitor are vertically arranged using a lower electrode made only of Ru, and a lower electrode of the dielectric capacitor is formed by a polycrystalline Si plug. (IEEE, IED)
M95-115-118). However, in a dielectric capacitor using SBT having a higher heat treatment temperature for crystallization as compared with BST as a material of a ferroelectric film, a lower electrode made of only Ru is used to form such a polycrystalline Si plug. It has not been reported that a stack structure in which the lower electrode of the dielectric capacitor is connected to the diffusion layer of the transistor has been realized.

The present invention has been devised based on the above study.

That is, in order to achieve the above object, a dielectric capacitor according to the present invention has a composition formula of Pt _{1 -xyz} I
represented by r _y Rh _z Ru _x, the composition range 0 <x ≦
1, 0 ≦ y <1, 0 ≦ z <1, 0.3 ≦ x + y + z ≦ 1
And a ferroelectric film made of a Bi-based layered perovskite ferroelectric on the lower electrode, and an upper electrode on the ferroelectric film.

Further, according to the present invention, in a ferroelectric memory having a memory cell comprising a transistor and a dielectric capacitor, the dielectric capacitor has a composition formula of Pt _{1 -xyz}
It is represented by Ir _y Rh _z Ru _x , and its composition range is 0 <x ≦
1, 0 ≦ y <1, 0 ≦ z <1, 0.3 ≦ x + y + z ≦ 1
And a ferroelectric film made of a Bi-based layered perovskite ferroelectric on the lower electrode, and an upper electrode on the ferroelectric film.

In the present invention, a specific example of a Bi-based layered structure perovskite ferroelectric used as a material for a ferroelectric film is represented by a composition formula Bi _x (Sr, Ca, B).
a) _y (Ta, Nb) ₂ O _z (where x = 1.70-
2.50, y = 0.60-1.20, z = 9 ± d, 0 ≦
ferroelectric crystal layer represented containing 85% or more d ≦ 1.0) (may contain an oxide or a composite oxide of some Bi and Ta or Nb) or composition formula Bi _x Sr _y Ta ₂
O _z (x = 1.70 to 2.50, y = 0.60
~ 1.20, z = 9 ± d, 0 ≦ d ≦ 1.0) A ferroelectric material containing 85% or more of a crystal layer (some Bi and T
a or Nb oxide or composite oxide may be contained)
It is. A typical example of the latter is SrBi ₂ Ta ₂ O ₉ .

In the ferroelectric memory according to the present invention, when the transistor and the dielectric capacitor are arranged vertically in order to achieve high integration, the lower electrode of the dielectric capacitor is typically connected to the lower electrode of the transistor. It is provided on a plug made of Si or W provided on the diffusion layer. In this case, the periphery of the plug is usually made of an insulator such as SiO _2, but the composition formula Pt _{1 -xyz} Ir _y
Rh _z R _x , whose composition range is 0 <x ≦ 1, 0
In general, adhesion between a material satisfying ≦ y <1, 0 ≦ z <1, 0.3 ≦ x + y + z ≦ 1 and SiO ₂ is not very good, and in some cases, peeling of the lower electrode may occur. Therefore, in order to prevent this, preferably, for example, Ti or T is provided between the plug and the lower electrode.
A bonding layer made of a is provided.

According to the present invention configured as described above, the lower electrode of the dielectric capacitor is composed of the composition formula Pt
_1-xyz Ir _y Rh _z Ru represented by _x, the composition range 0 <x ≦ 1,0 ≦ y < 1,0 ≦ z <1,0.3 ≦ x + y
+ Z ≦ 1, the transistor and the dielectric capacitor are arranged vertically and the lower electrode of the dielectric capacitor is connected to a diffusion layer of the transistor by a plug made of Si or W. Even when a high-temperature heat treatment is performed in an oxygen atmosphere for crystallization during the formation of a ferroelectric film made of a Bi layered structure perovskite ferroelectric, Si or W diffuses from the plug to the upper surface of the lower electrode. Therefore, the problem that Si or W reaching the upper surface of the lower electrode is oxidized and the conductivity of the lower electrode is lost can be prevented.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a dielectric capacitor according to one embodiment of the present invention.

As shown in FIG. 1, in the dielectric capacitor according to this embodiment, a Ti film 2 as a bonding layer and a Pt as a lower electrode are formed on a conductive Si substrate 1.
_1-x Ru _x film 3 (where, 0.3 ≦ x ≦ 1), Pt film 5 as SBT film 4 and the upper electrode of the ferroelectric film
Are sequentially laminated. As an example of the film thickness of these films, Ti film 2 20nm, Pt _1-x Ru x film 3 is 2
00 nm, the SBT film 4 is 250 nm, and the Pt film 5 is 200 nm.
nm.

Next, a description will be given of a method of manufacturing the dielectric capacitor having the above-described structure according to the embodiment.

That is, in order to manufacture the dielectric capacitor according to the embodiment, first, the Si substrate 1 is treated with dilute hydrofluoric acid to remove the SiO ₂ film (not shown) on the surface, and then the Si substrate 1 is removed. A Ti film 2 is formed on 1 by a sputtering method.

Next, forming a Pt _1-x Ru x film 3 by sputtering on the Ti film 2. This Pt _1-x R
As an example of film forming conditions of u _x film 3, using the DC2 pole magnetron sputtering device, used after placing six Ru chips 1cm square on the Pt target 4 inch angle as a target, as a sputtering gas Is Ar, the flow rate is 10 SCCM, the total pressure is 4 mTorr,
The input power was 0.4 A DC, 340 V, and the deposition rate was 2
00 nm / 2 minutes. Pt thus formed
Toro analysis of a composition of _1-x Ru _x film 3 by EPMA method, P
t ₆₀ Ru ₄₀ (however, the composition was atomic%).

[0029] Next, Pt _1-x Ru x film 3 on the example sol - forming the SBT film 4 by gel spin coating. Next, after heat treatment in an oxygen atmosphere at 750 ° C. for one hour for crystallization of the SBT film 4, a Pt film 5 is formed by, for example, a sputtering method. After this, another 75
Heat treatment at 0 ° C. for 10 minutes in an oxygen atmosphere.

FIG. 2 shows the result of measuring the amount of accumulated charge by applying a voltage between the Si substrate 1 and the Pt electrode 5 of the dielectric capacitor thus manufactured. As is clear from FIG. 2, the important residual polarization value in the ferroelectric memory is 2P.
_r = 17 μC / cm ² This remanent polarization value is SB
T was a good value, which was obtained by measurement through the Si substrate 1.

On the other hand, as a comparative example, in FIG.
Tried to measure the same amount of charge _1-x Ru _x film 3 instead of the sample using the Pt film produced separately, it can not be obtained a hysteresis curve as shown in FIG. 2, as capacitor Turned out not to work.

[0032] FIG. 3, changing the Pt _1-x Ru _x film 3 of Ru composition ratio x to prepare a ferroelectric capacitor shown in FIG. 1 shows the results of measuring the residual polarization value 2P _r. From FIG. 3, Pt
_1-x Ru _x film 3 of Ru composition ratio x 1 in the range of 0.3 or more
5 [mu] C / cm ² or more residual polarization value 2P _r is obtained, it can be seen that desirable.

As described above, according to this embodiment,
By uses a Pt _1-x Ru _x film 3 of 0.3 ≦ x ≦ 1 as a lower electrode, a heat treatment in an oxidizing atmosphere at a high temperature of about 750 ° C. for its crystallization during the formation of the SBT film 4 even if the, it is possible to prevent the from the Si substrate 1 Si reaches the upper surface of the Pt _1-x Ru _x film 3 by thermal diffusion, thus the upper surface of the Si is Pt _1-x Ru _x film 3 in is oxidized, it is possible to prevent the conductivity of the Pt _1-x Ru _x film 3 are lost, also, SBT film 4
In addition, the problem that Si is diffused into the capacitor and the characteristics of the capacitor are significantly deteriorated can be prevented. For this reason, this dielectric capacitor has a structure in which a transistor and a dielectric capacitor are arranged vertically, and a lower electrode of the dielectric capacitor is connected to a diffusion layer of the transistor by a polycrystalline Si plug. Therefore, a highly integrated ferroelectric memory using an SBT film as a dielectric film of a dielectric capacitor can be realized.

Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. .

For example, the film thicknesses and film forming conditions described in the above embodiment are merely examples, and different film thicknesses and film forming conditions may be used as needed.

[0036]

As described above, according to the present invention, the lower electrode of the dielectric capacitor has the composition formula Pt
_1-xyz Ir _y Rh _z Ru represented by _x, the composition range 0 <x ≦ 1,0 ≦ y < 1,0 ≦ z <1,0.3 ≦ x + y
+ Z ≦ 1, the transistor and the dielectric capacitor are arranged side by side in the vertical direction, and when the lower electrode of the dielectric capacitor is connected to the diffusion layer of the transistor by a plug made of Si or W, the ferroelectric Even if a high-temperature heat treatment is performed in an oxidizing atmosphere at the time of forming the film, Si or W can be prevented from reaching the upper surface of the lower electrode by diffusion from the plug, and thereby the dielectric film of the dielectric capacitor can be prevented. As a material of the material, a Bi-based layered structure perovskite ferroelectric such as SBT can be used.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a dielectric capacitor according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a result of measuring a stored charge amount of a dielectric capacitor according to an embodiment of the present invention.

FIG. 3 shows Pt _1-x Ru _x used as a lower electrode in a dielectric capacitor according to an embodiment of the present invention.
It is a schematic diagram illustrating a residual change in polarization value 2P _r by Ru composition ratio x of the membrane.

FIG. 4 is a cross-sectional view showing a conventional ferroelectric memory in which transistors and capacitors are arranged in a horizontal direction.

FIG. 5 is a sectional view showing a conventional ferroelectric memory in which transistors and capacitors are arranged in a vertical direction.

[Explanation of symbols]

1 ... Si substrate, 2 ... Ti film, 3 ... Pt _1-x
Ru _x film, 4 ··· SBT film, 5 ··· Pt film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/108 H01L 29/78 371 21/8242 21/8247 29/788 29/792

Claims (13)

[Claims] 1. A composition formula _{Pt 1-xyz Ir y Rh z} Ru x
Wherein the composition range is 0 <x ≦ 1, 0 ≦ y <1, 0
≦ z <1, 0.3 ≦ x + y + z ≦ 1, a lower electrode made of a material satisfying 0.3 ≦ x + y + z ≦ 1, a ferroelectric film made of a Bi-based layered perovskite ferroelectric on the lower electrode, A dielectric capacitor having an upper electrode. 2. The method according to claim 1, wherein the lower electrode has a composition formula of Pt _1-x Ru.
_2. The dielectric capacitor according to claim 1, wherein the dielectric capacitor is made of a material represented by _x (where 0.3 ≦ x ≦ 1). Wherein said dielectric film, Bi _x (Sr, Ca,
Ba) _y (Ta, Nb) ₂ O _z (where x = 1.70
~ 2.50, y = 0.60-1.20, z = 9 ± d, 0
2. The dielectric capacitor according to claim 1, comprising a ferroelectric containing 85% or more of a crystal layer represented by ≦ d ≦ 1.0). Wherein said dielectric film, Bi _x Sr _y Ta ₂ O
_z (however, x = 1.70-2.50, y = 0.60-
2. The dielectric capacitor according to claim 1, comprising a ferroelectric material containing 85% or more of a crystal layer represented by 1.20, z = 9 ± d, 0 ≦ d ≦ 1.0). 5. The dielectric capacitor according to claim 1, wherein said dielectric film is made of a ferroelectric material represented by SrBi ₂ Ta ₂ O ₉ . 6. A ferroelectric memory having a memory cell comprising a transistor and a dielectric capacitor, the dielectric capacitor is represented by the composition formula _{Pt 1-xyz Ir y Rh z} Ru x, the composition range 0 <X ≦ 1, 0 ≦ y <1, 0 ≦ z <1, 0.
A lower electrode made of a material satisfying 3 ≦ x + y + z ≦ 1; a ferroelectric film made of a Bi-based layered perovskite ferroelectric on the lower electrode; and an upper electrode made of the ferroelectric film. Characteristic ferroelectric memory. 7. The lower electrode has a composition formula of Pt _1-x Ru.
7. The ferroelectric memory according to claim 6, comprising a material represented by _x (where 0.3 ≦ x ≦ 1). 8. The ferroelectric film according to claim 1, wherein the composition formula is Bi _x (S
r, Ca, Ba) _y (Ta, Nb) ₂ O _z (where x
= 1.70-2.50, y = 0.60-1.20, z =
7. The ferroelectric memory according to claim 6, comprising a ferroelectric material containing 85% or more of a crystal layer represented by 9 ± d, 0 ≦ d ≦ 1.0). 9. The ferroelectric film composition formula Bi _x Sr _y
Ta ₂ O _z (where x = 1.70 to 2.50, y =
7. The ferroelectric material according to claim 6, comprising a ferroelectric material containing 85% or more of a crystal layer represented by 0.60 to 1.20, z = 9 ± d, 0 ≦ d ≦ 1.0). Body memory. 10. The ferroelectric film is made of SrBi ₂ Ta ₂ O.
7. The ferroelectric memory according to claim 6, wherein the ferroelectric memory is made of a ferroelectric material represented by the formula ( ₉ ). 11. The ferroelectric memory according to claim 6, wherein said lower electrode is provided on a plug made of Si or W provided on a diffusion layer of said transistor. 12. The ferroelectric memory according to claim 6, further comprising a bonding layer between said plug and said lower electrode. 13. The ferroelectric memory according to claim 6, wherein said bonding layer is made of Ti or Ta.