JPH10242408A - Dielectric capacitor, non-volatile memory and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent diffusion of Si or W from a plug to a lower electrode by introducing a small quantity of rare earth elements and oxygen in noble metal such as Pt and Ir, forming a metallic film containing rare earth oxide and providing it between the lower electrode and the polycrystalline Si plug as a diffusion preventing layer. SOLUTION: A Ti film 2 as a junction layer, an Ir-Y-O film 3 as the diffusion preventing layer, for example, a Ti film 4 as a junction layer, a PT film 5 as the lower electrode, an SBT film 6 as a ferroelectric film and a Pt film 7 as an upper electrode are sequentially stacked on a conductive Si substrate 1. In the diffusion preventing layer 3, a dielectric capacitor is shown by a composition formula M1a M11b Oc (but (a), (b) and (c) are composition shown by atom %, M1 is at least one type of noble metal selected from a group constituted of Pt, Ir, Ru, Rh and Pd, and M11 shows at least one type of rare earth element) and the layer is formed of a material whose composition range is 90>=a>=40, 15>=b>=2, 4<=c and a+b+c=100.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dielectric capacitor, a nonvolatile memory, and a semiconductor device.

[0002]

2. Description of the Related Art A ferroelectric memory is a high-speed rewritable nonvolatile memory utilizing a high-speed polarization reversal of a ferroelectric film and its residual polarization. FIG. 6 shows an example of a conventional ferroelectric memory.

As shown in FIG. 6, in this conventional ferroelectric memory, a field insulating film 102 is selectively provided on the surface of a p-type Si substrate 101, thereby performing element isolation. On the surface of the active region in a portion surrounded by the field insulating film 102, the gate insulating film 1 is formed.
03 is provided. Symbol WL indicates a word line. The p-type Si substrate 10 on both sides of the word line WL
In 1, an n ⁺ type source region 104 and a drain region 105 are provided. The word line WL, the source region 104 and the drain region 105 form a transistor Q.

Reference numeral 106 denotes an interlayer insulating film. Interlayer insulating film 106 in a portion above field insulating film 102
On top, for example, a Ti layer having a thickness of about 30 nm is used as a bonding layer.
Through the film 107, for example, a film thickness of 200 as a lower electrode
Pt film 108 having a thickness of about 200 nm, such as a Pb (Zr, Ti) O ₃ (PZT) film or SrBi ₂ Ta having a thickness of about 200 nm.
_A ferroelectric film 109 such as a ₂ O ₉ (SBT) film and a Pt film 110 having a thickness of, for example, about 200 nm as an upper electrode.
Are sequentially laminated, and the Pt film 108 and the ferroelectric film 1 are stacked.
09 and the Pt film 110 constitute a capacitor C. With the transistor Q and this capacitor C,
One memory cell is configured.

Reference numeral 111 denotes an interlayer insulating film. A contact hole 112 is provided in the interlayer insulating film 106 and the interlayer insulating film 111 above the source region 104. Further, a contact hole 113 is provided in the interlayer insulating film 111 at a portion above one end of the Pt film 108. Further, a contact hole 114 is provided in the interlayer insulating film 111 above the Pt film 110. Then, through the contact holes 112 and 113, the source region 104 of the transistor Q and the Pt film 10 serving as the lower electrode of the capacitor C are formed.
8 are connected by a wiring 115. Further, a wiring 116 is connected to the Pt film 110, which is the upper electrode of the capacitor C, through the contact hole 114. Reference numeral 117 denotes a passivation film.

In the conventional ferroelectric memory shown in FIG. 6, a transistor Q and a capacitor C are arranged side by side (in a direction parallel to the substrate surface). In order to increase the number, it is necessary to adopt a structure in which the transistor Q and the capacitor C are arranged side by side in the vertical direction (the direction perpendicular to the substrate surface). An example is shown in FIG. Here, in FIG. 7, the same parts as those in FIG. 6 are denoted by the same reference numerals.

In FIG. 7, reference numerals WL1 to WL4 denote word lines, and 118 denotes an interlayer insulating film. Drain region 105
A contact hole 119 is formed in the interlayer insulating film 118 in the upper portion of the transistor Q through the contact hole 119 to connect the bit line BL to the drain region 1 of the transistor Q.
05. Reference numerals 120 and 121 indicate interlayer insulating films. A contact hole 122 is provided in the interlayer insulating film 121 above the source region 104, and a polycrystalline Si plug 123 is formed in the contact hole 122.
Is embedded. And this polycrystalline Si plug 1
Through 23, the source region 104 of the transistor Q and the Pt film 108, which is the lower electrode of the capacitor C, are electrically connected.

When the ferroelectric film 109 is formed, it is usually necessary to perform a heat treatment at a high temperature of 600 to 800 ° C. in an oxidizing atmosphere for crystallization. 123 is thermally diffused into the Pt film 108, which is the lower electrode of the capacitor C, and the Si
The Pt film 10 is oxidized on the upper layer of the film
8 loses conductivity or Si further increases the ferroelectric film 10
9, and the characteristics of the capacitor C are significantly deteriorated.

When the material of the ferroelectric film 109 is PZT, the firing temperature is about 600 ° C., and it is reported that a nitride film such as TiN can be used as a Si diffusion preventing layer. There are (Abstracts of the JSAP,
Spring 1995, 30p-D-20, 30p-D-1
0). However, the nitride-based film is oxidized by heat treatment in an oxidizing atmosphere at a high temperature and loses conductivity. Therefore, in order to further improve the ferroelectric characteristics of the ferroelectric film 109, the nitride-based film has a sufficient heat treatment atmosphere. When oxygen is introduced and heat treatment is performed at a higher temperature, there is a problem that surface roughness and electrical resistance increase due to oxidation.

On the other hand, as a material of the ferroelectric film 109, P
When using SBT which is considered to have better fatigue properties than ZT, the heat treatment temperature for obtaining good ferroelectric properties is 8
The temperature is about 00 ° C., which is higher than that of PZT. Therefore, when SBT is used as the material of the ferroelectric 109, the diffusion prevention layer made of the above-mentioned nitride-based film has a completely insufficient heat resistance and cannot be used.

There has been no report on the structure of a stacked capacitor using SBT as the material of the ferroelectric film 109, and it is difficult to realize a highly integrated nonvolatile memory using such a capacitor. And it was.

The same problem as described above can also occur when a W plug is used instead of a polycrystalline Si plug.

On the other hand, conventionally, the minimum processing size is 0.50
As an example of an ultra-highly integrated semiconductor integrated circuit device having a 0.35 μm multilayer wiring structure, there is one as shown in FIG.
50-57 and Nikkei Microdevice, September 1995
Monthly name, pp. 70-77).

As shown in FIG. 8, in this conventional semiconductor integrated circuit device, a p-well 202 and an n-well 203 are provided in an n-type Si substrate 201. A recess 204 is provided on the surface of the n-type Si substrate 201 in a portion to be an element isolation region, and a field insulating film 205 made of a SiO ₂ film is embedded in the recess 204.
On the surface of the active region surrounded by the field insulating film 205, a gate insulating film 206 made of a SiO ₂ film is provided. Reference numeral 207 denotes polycrystalline Si doped with impurities.
Film, 208 denotes a metal silicide film such as WSi _x film. These polycrystalline Si film 207 and metal silicide film 208 form a gate electrode having a polycide structure. Sidewall spacers 209 made of SiO ₂ are provided on the side walls of the polycrystalline Si film 207 and the metal silicide film 208. n-well 203
Among them, a polycrystalline Si film 207 and a metal silicide film 2
P ⁺ -type diffusion layers 210 and 211 used as a source region or a drain region are provided in a self-alignment manner with respect to the gate electrode made of 08. A p-channel MOS is formed by these gate electrodes and diffusion layers 210 and 211.
A transistor is formed. Similarly, p well 20
2, an n-channel MOS transistor is formed. Reference numerals 212 and 213 denote n ⁺ -type diffusion layers used as source or drain regions of the n-channel MOS transistor.

An interlayer insulating film 214 is provided to cover these p-channel MOS transistors and n-channel MOS transistors. In the interlayer insulating film 214, connection holes 215 and 216 are provided in a portion corresponding to the diffusion layer 211 of the p-channel MOS transistor and a portion corresponding to the gate electrode on the field insulating film 205, respectively. W plugs 219 are embedded in these connection holes 215 and 216 via a Ti film 217 and a TiN film 218.

On the connection holes 215 and 216, a Ti film 2
20, an Al—Cu alloy wiring 222 is provided via the TiN film 221, and a TiN film 223 is provided thereon. Reference numeral 224 indicates an interlayer insulating film. In the interlayer insulating film 224, connection holes 225 and 226 are provided in portions corresponding to the Al-Cu alloy wiring 222. Inside these connection holes 225 and 226, Ti film 227 and T
A W plug 229 is embedded via an iN film 228.

Further, on the connection holes 225 and 226,
Al—Cu through the Ti film 230 and the TiN film 231
An alloy wiring 232 is provided, and a TiN film 233 is provided thereon.

In the semiconductor integrated circuit device shown in FIG. 8, the Ti film 217 (having a thickness of usually 5 to 50 nm) provided on the diffusion layer 211 in the portion of the connection hole 215 is mainly used for the W plug 219. It is used to obtain good electrical connection with the diffusion layer 211 and to improve adhesion to the base. This is because the surface of the diffusion layer 211 is chemically active, so that when exposed to moisture or air, the surface of the diffusion layer 211 has a thickness of 0.5 to 5 nm in a very short time (considered to be less than 2 to 3 minutes). This is because a thin SiO _x film is formed, and electrical connection and adhesion with the diffusion layer 211 are deteriorated. On the other hand, when the Ti film 217 is provided on the diffusion layer 211, a chemical reaction occurs between the Ti film 217 and the SiO _x film formed on the surface of the diffusion layer 211, resulting in electrical connection. Properties and mechanical adhesion can be improved.

However, the Ti film 2 is formed on the diffusion layer 211.
17 through the W plug 219 (the film thickness is usually 50 to 700).
nm), Si of the diffusion layer 211 and the W plug 219 are formed by a heat treatment at the time of forming the W plug 219 (typically 300 to 500 ° C.) or a heat treatment performed in a subsequent step (typically 350 to 450 ° C.). WSi _x is formed undergoes a chemical reaction. At this time, the movement of the substance (mainly, the movement of Si from the diffusion layer 211 into the W plug 219) occurs, so that a gap is formed between the diffusion layer 211 and the W plug 219, and good electrical connection is achieved. There is a problem to be lost. Therefore, the diffusion layer 211 and the W plug 2
In order to prevent a chemical reaction with the TiN film 19, a TiN film 218 (having a thickness of usually 5 to 5) is provided between the Ti film 217 and the W plug 219.
0 nm). Therefore, this TiN film 2
Reference numeral 18 is called a barrier metal. In addition to the TiN film, there is a TiON film as a barrier metal.

Next, the Ti film 220 provided on the W plug 219 is used for making good electrical and mechanical connections between the W plug 219 and the Al--Cu alloy wiring 222. Also, the Ti on the Ti film 220
The N film 221 is composed of the W plug 219 and the Al-Cu alloy wiring 2
It has been used to suppress the transfer of substances between and the chemical reaction with 22. The same applies to the Ti film 230 and the TiN film 231 provided on the W plug 229 in the portions of the connection holes 225 and 226.

However, when the W plug 219 is formed via the Ti film 217 and the TiN film 218 in the above-described manufacturing of the semiconductor integrated circuit device, the upper limit of the process temperature in the post-process is lower than the heat-resistant temperature of the TiN film 218. You will be restricted. The heat resistant temperature of this TiN film 218 is 50
0 ° C. (when formed by a sputtering method) to 650
° C (in the case of forming a film by the CVD method), it can be said that there is almost no freedom in the process temperature and time after the formation of the W plug 219. The problem is that the W plug 21
The same applies to the case where a Si plug or an Al plug is used instead of 9.

[0022]

As described above, as in the conventional ferroelectric memory shown in FIG. 7, the transistor Q and the capacitor C are arranged vertically and the capacitor C
When the Pt film 108 is connected to the source region 104 of the transistor Q by the polycrystalline Si plug 123 or the W plug, as the material of the ferroelectric film 109 of the capacitor C, SBT or the like which requires a high-temperature heat treatment is used. It was difficult to use.

Further, in the conventional semiconductor integrated circuit device as shown in FIG. 8, there is almost no freedom in the process temperature and time in the process after the formation of the W plug 219.

Accordingly, an object of the present invention is to arrange a transistor and a dielectric capacitor side by side in the vertical direction, and to connect the lower electrode of the dielectric capacitor to a diffusion layer of the transistor by a plug made of Si or W. To prevent the diffusion of Si or W from the lower electrode into the lower electrode, thereby making it possible to use not only PZT but also SBT or the like that requires a high-temperature heat treatment as a material of the dielectric film of the dielectric capacitor. An object of the present invention is to provide a capacitor and a nonvolatile memory using such a dielectric capacitor.

Another object of the present invention is to provide a semiconductor device capable of increasing the degree of freedom in the process temperature and time after the plug is formed in the manufacture of a semiconductor device such as a semiconductor integrated circuit device. is there.

[0026]

Means for Solving the Problems The present inventor has made intensive studies in order to solve the above-mentioned problems of the prior art. The outline is described below.

In order to prevent diffusion of Si from the polycrystalline Si plug to the lower electrode made of a Pt film or the like, a diffusion preventing layer may be provided between the lower electrode and the polycrystalline Si plug. What is required of this diffusion prevention layer is that after diffusion of Si can be prevented, and after heat treatment in an oxidizing atmosphere at a high temperature of about 800 ° C. for crystallization of the ferroelectric film, This also ensures that the conductivity of the lower electrode can be ensured.

In this regard, generally, Pt, Ir, R
A film consisting only of a noble metal such as u cannot prevent the diffusion of Si. When a conductive noble metal oxide such as IrO ₂ or RuO ₂ is used, oxygen diffuses from the IrO ₂ or RuO ₂ into the polycrystalline Si plug during the heat treatment, and the polycrystalline Si plug becomes It is oxidized and loses conductivity. This is because the bonding force with oxygen is S
This is because i is stronger. Furthermore, TiN and T
As described above, conductive nitrides such as aN have problems in heat resistance and oxidation resistance.

In view of such circumstances, the present inventor has conducted intensive studies, and as a result, introduced a small amount of rare earth element and oxygen into a noble metal such as Pt and Ir to form a rare earth oxide-containing noble metal film. By providing this as a diffusion preventing layer between the lower electrode and the polycrystalline Si plug, it is possible to prevent the diffusion of Si from the polycrystalline Si plug to the lower electrode while securing conduction between the polycrystalline Si plug and the lower electrode. I found what I could do. In the rare-earth oxide-containing noble metal film, since the self-diffusion of the noble metal is suppressed by the introduced oxygen, the diffusion of Si through the rare-earth oxide-containing noble metal film can be prevented. Further, since a rare earth element having a strong bonding force with oxygen is introduced, it is possible to prevent oxygen from diffusing into the polycrystalline Si plug and oxidizing the polycrystalline Si plug. Further, since the rare earth oxide-containing noble metal film is mainly composed of a noble metal, the conductivity is sufficiently ensured.

Further, as a result of research conducted by the present inventors, in some cases, a lower electrode may be constituted only by the rare earth oxide-containing noble metal film, and practical problems may not occur even if no noble metal such as Pt is used. Also found.

This rare earth oxide-containing noble metal film is formed by introducing a rare earth element having a strong bonding force with oxygen into the noble metal, and forming the noble metal by sputtering while introducing oxygen (O ₂ ) or water vapor (H ₂ O). By doing so, it can be easily formed. Alternatively, a rare-earth oxide chip may be placed on a noble metal target and formed by a sputtering method.

FIG. 1 shows the result of X-ray diffraction of an Ir ₈₀ Y ₅ O ₁₅ film (composition is atomic%) as an example of the rare earth oxide-containing noble metal film. Here, FIG.
FIG. 1B shows the state after the heat treatment at 800 ° C.

As shown in FIG. 1A, the crystal grain size was 10 immediately after the film formation.
It is in the form of microcrystals of nm or less, and almost no iridium oxide such as IrO ₂ is found. Further, from Figure 1B, the crystal grains are slightly larger, but still grain size are kept fine crystalline state of about 17 nm, the Ir ₈₀ Y
_This shows that the ₅ O ₁₅ film is thermally stable. IrO
Almost no peak due to iridium oxide such as ₂ is observed.

Here, Japanese Patent Application Laid-Open No. 7-245237 discloses that iridium oxide is used as a material for a lower electrode of a dielectric capacitor.
Although the r ₈₀ Y ₅ O ₁₅ film contains Ir and O,
By containing Y in addition to this, it does not become iridium oxide such as IrO ₂ and the crystal structure is that of metal iridium. That is, it is clear that the Ir ₈₀ Y ₅ O ₁₅ film is a material that is significantly different from the material described in JP-A-7-245237.

According to the study of the present inventor, the composition range of the noble metal, the rare earth element and the oxygen in the rare earth oxide-containing noble metal film is desirably the range indicated by the hatched region in FIG. . If the amount of the noble metal is more than this range, a stable microcrystalline state cannot be obtained. If the amount is too small, the electric resistance increases and the crystalline state becomes unstable. Further, when the composition of the rare earth element and oxygen is within this range, the state of the microcrystal is stabilized.

In order to obtain this microcrystalline state, it is desirable to use a reactive sputtering method which is a high energy film forming method as a method of forming the rare earth oxide-containing noble metal film. At this time, in order to supply oxygen, it is necessary to mix O ₂ or H ₂ O into the sputtering gas. Or,
A ceramic chip of a rare earth oxide such as Y ₂ O ₃ is placed on a noble metal target, and the chip is filled with O ₂ gas or H _2.
The film may be formed by a sputtering method in a ₂ O gas atmosphere.

The present invention has been devised based on the above study.

That is, in order to achieve the above object, a dielectric capacitor according to a first aspect of the present invention has a composition formula M _Ia M _IIb O _c (where a, b, and c are compositions represented by atomic%, M _I is represented by at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M _II is represented by at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b +
It has a diffusion prevention layer made of a material with c = 100, a lower electrode on the diffusion prevention layer, a dielectric film on the lower electrode, and an upper electrode on the dielectric film.

The dielectric capacitor according to the second aspect of the present invention has a composition formula M _Ia M _IIb O _c (where a, b, and c are compositions expressed in atomic%, and M _I is Pt, Ir, Ru, Rh. And at least one noble metal selected from the group consisting of Pd and Pd, M _II represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4
≦ c, a + b + c = 100, characterized by having a lower electrode, a dielectric film on the lower electrode, and an upper electrode on the dielectric film.

According to a third aspect of the present invention, there is provided a nonvolatile memory having a memory cell comprising a transistor and a dielectric capacitor, wherein the dielectric capacitor has a composition formula M _Ia M
_IIb O _c (where a, b, and c are compositions expressed in atomic%,
M _I is at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M _II is at least one rare earth element.
0 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b + c = 1
00, a diffusion prevention layer made of a material, a lower electrode on the diffusion prevention layer, a dielectric film on the lower electrode, and an upper electrode on the dielectric film.

According to a fourth aspect of the present invention, there is provided a nonvolatile memory having a memory cell including a transistor and a dielectric capacitor, wherein the dielectric capacitor has a composition formula M _Ia M
_IIb O _c (where a, b, and c are compositions expressed in atomic%,
M _I is at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M _II is at least one rare earth element.
0 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b + c = 1
And a lower electrode made of a material No. 00, a dielectric film on the lower electrode, and an upper electrode on the dielectric film.

According to a fifth aspect of the present invention, there is provided a semiconductor device having a first conductive layer and a second conductive layer on the first conductive layer, wherein the first conductive layer, the second conductive layer, In the formula, the composition formula M _Ia M _IIb O _c (where a, b, and c are compositions expressed in atomic%, M _I is at least one kind selected from the group consisting of Pt, Ir, Ru, Rh, and Pd) The noble metal, M _II represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a +
A diffusion prevention layer made of a material with b + c = 100 is provided.

[0043] In this invention, the composition range of material expressed by M _Ia M _IIb O _c is substantially the same as those represented by the hatched area in FIG.

[0044] In this invention, the composition range of material expressed by M _Ia M _IIb O _c is preferably, 85 ≧ a ≧ 65,1
0 ≧ b ≧ 2, 10 ≦ c, a + b + c = 100.

[0045] In the present invention, M _Ia M _IIb O diffusion preventing layer or the lower electrode made of a material represented by _c, e.g., Ir-Y-O, Ir -Ce-O, Ir-Dy-O,
Ir-Gd-O, Ru-YO, Pt-YO, Pd-
YO, Rh-YO, and the like. Also, this M _Ia M
_IIb O made of a material represented by _c diffusion barrier layer or the lower electrode is suitably formed by reactive sputtering using oxygen or water vapor.

In the first and third aspects of the present invention, the lower electrode comprises Pt, Ir, Ru, Rh and Pt.
and at least one noble metal selected from the group consisting of d. This lower electrode is, for example, Pt, I
a film made of r, Ru, Rh or Pd, Pt, Ir,
It is formed by an alloy film of two or more kinds of noble metals selected from the group consisting of Ru, Rh or Pd, and a composite film thereof.

In the present invention, a Bi-based layered perovskite ferroelectric is typically used as a material for the dielectric film. A specific example thereof is a composition formula Bi _x
(Sr, Ca, Ba) _y (Ta, Nb) ₂ O _z (where 2.50 ≧ x ≧ 1.70, 1.20 ≧ y ≧ 0.6
0, z = 9 ± d, 1.0 ≧ d ≧ 0) Ferroelectric substance containing 85% or more of a crystal layer (even if a small amount of Bi and Ta or Nb oxides or composite oxides are contained) good) or composition formula _{Bi x Sr y Ta 2 O z} ( however, 2.50 ≧ x ≧
1.70, 1.20 ≧ y ≧ 0.60, z = 9 ± d, 1.
It is a ferroelectric substance (may contain some Bi and Ta or Nb oxides or composite oxides) containing 85% or more of a crystal layer represented by 0 ≧ d ≧ 0). A typical example of the latter is SrB
i ₂ Ta ₂ O ₉ . The material of the dielectric film is Pb
A ferroelectric substance represented by (Zr, Ti) O ₃ may be used. These ferroelectrics are suitable for use as ferroelectric film materials for ferroelectric memories. Further, as a material of the dielectric film, for example, a high dielectric material represented by (Ba, Sr) TiO ₃ can be used, which is suitable for use as a dielectric film material of a capacitor in a DRAM, for example. .

In the nonvolatile memory according to the third or fourth aspect of the present invention, when a transistor and a dielectric capacitor are arranged in a vertical direction for high integration, the diffusion preventing layer or the lower electrode is Typically, it is provided on a plug made of Si or W provided on a diffusion layer of a transistor. In this case, in order to reduce the contact resistance between the plug and the diffusion prevention layer or the lower electrode, a bonding layer made of Ti or Ta is preferably provided between the plug and the diffusion prevention layer or the lower electrode. In the third aspect, the bonding layer may be provided between the diffusion preventing layer and the lower electrode. It is known that when a Bi-based layered structure perovskite ferroelectric, for example, SBT is used as the material of the ferroelectric film, Bi diffuses during the heat treatment for crystallization. When the bonding layer made of Ti or Ta is provided between the diffusion preventing layer and the lower electrode in the nonvolatile memory according to the invention, the bonding layer serves as a trap for Bi diffusion. The smoothness of the surface of the dielectric film can be improved.

[0049] According to the first invention and the third aspect of the invention configured as described above, the lower side of the lower electrode of the ferroelectric capacitor is represented by a composition formula M _Ia M _IIb O _c, the The composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a
Since it has a diffusion prevention layer made of a material having sufficient heat resistance and oxidation resistance in which + b + c = 100, the transistor and the dielectric capacitor are vertically arranged, and the lower electrode of the dielectric capacitor is made of Si or W. When connecting to a transistor diffusion layer by a plug, even if high-temperature heat treatment is performed in an oxygen atmosphere for crystallization during formation of a dielectric film, diffusion of Si or W from the plug to the lower electrode is prevented. Then, the Si or W diffuses into the upper layer of the lower electrode and is oxidized, so that the conductivity of the lower electrode is lost or the Si or W further diffuses into the dielectric film to deteriorate the capacitor characteristics. Problems can be prevented. For this reason, not only PZT but also SBT or the like that requires high-temperature heat treatment in an oxygen atmosphere for crystallization can be used as the material of the dielectric film.

According to the second and fourth aspects of the present invention configured as described above, the lower electrode of the dielectric capacitor is represented by the composition formula M _Ia M _IIb O _c , and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b +
Since the transistor and the dielectric capacitor are made of a material having sufficient heat resistance and oxidation resistance where c = 100, the transistor and the dielectric capacitor are arranged in the vertical direction, and the lower electrode of the dielectric capacitor is connected to the transistor by a plug made of Si or W. In the case of connection with the diffusion layer, even if a high-temperature heat treatment is performed in an oxygen atmosphere for crystallization during the formation of the dielectric film, diffusion of Si or W from the plug to the lower electrode can be prevented, whereby To prevent the Si or W from diffusing into the upper layer of the lower electrode and being oxidized, thereby losing the conductivity of the lower electrode, or preventing Si or W from further diffusing into the dielectric film and deteriorating the capacitor characteristics. Can be.
Therefore, not only PZT as a material of the dielectric film but also S which requires a high-temperature heat treatment in an oxygen atmosphere for crystallization.
BT or the like can also be used.

According to the fifth aspect of the present invention configured as described above, the distance between the first conductive layer and the second conductive layer is
It is represented by the composition formula M _Ia M _IIb O _c , and its composition range is 90 ≧
a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b + c = 100
Since the diffusion prevention layer made of a material having sufficient heat resistance and oxidation resistance is provided, diffusion of Si or the like can be prevented even at a high temperature.

[0052]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 3 shows a dielectric capacitor according to the first embodiment of the present invention.

As shown in FIG. 3, in the dielectric capacitor according to the first embodiment, the conductive Si substrate 1
On top, a Ti film 2 as a bonding layer and I as a diffusion prevention layer
An r-Y-O film 3, a Ti film 4 as a bonding layer, a Pt film 5 as a lower electrode, an SBT film 6 as a ferroelectric film, and a Pt film 7 as an upper electrode are sequentially stacked. To give an example of the film thickness of these films, the Ti film 2 has a thickness of 25n.
m, the Ir-YO film 3 is 100 nm, and the Ti film 4 is 20 n
m, Pt film 5 is 200 nm, SrBi ₂ Ta ₂ O ₉ film 6
Is 200 nm, and the Pt film 7 is 200 nm. Also, I
The composition of the r-Y-O film 3 is selected in a range indicated by a hatched region in FIG.

Next, a method of manufacturing the dielectric capacitor according to the first embodiment configured as described above will be described.

That is, in order to manufacture the dielectric capacitor according to the first embodiment, first, the Si substrate 1 is treated with dilute hydrofluoric acid to remove the SiO ₂ film (not shown) on the surface. Ti on a Si substrate 1 by sputtering
The film 2 is formed.

Next, an Ir—YO film 3 is formed on the Ti film 2 by a reactive sputtering method. This Ir
As an example of the film forming conditions of the —YO film 3, a DC bipolar magnetron sputtering apparatus is used, and the target is 4 μm.
Six Y chips each having 5 mm × 6 mm square were placed on an inch square Ir target, and a mixed gas of Ar and O ₂ was used as a sputtering gas, and their flow rates were 5.6 SCCM and 0.7 SCCM, respectively. , Total pressure is 4m
Torr, input power is DC 0.4 A, 450 V, and film formation speed is 100 nm / 2 minutes. When the composition of the thus-formed Ir-YO film 3 was analyzed by the EPMA method, it was found to be Ir ₈₀ Y ₅ O ₁₅ (however, the composition was atomic%). Next, a Ti film 4 and a Pt film 5 are sequentially formed on the Ir-YO film 3 by a sputtering method.

Next, an SBT film 6 is formed on the Pt film 5 by, for example, a sol-gel spin coating method. Next, SBT
After heat treatment in an oxygen atmosphere at 800 ° C. for one hour for crystallization of the film 6,
The t film 7 is formed. Thereafter, heat treatment is further performed at 800 ° C. for 10 minutes in an oxygen atmosphere.

FIG. 4 shows the result of measuring the amount of accumulated charge by applying a voltage between the Si substrate 1 and the Pt electrode 7 of the dielectric capacitor manufactured as described above. As is apparent from FIG. 4, the important residual polarization value in the ferroelectric memory is 2P.
_r = 19 μC / cm ² This remanent polarization value is SB
T was a good value, which was obtained by measurement through the Si substrate 1. Also, Ir- made of Ir ₈₀ Y ₅ O ₁₅
As a result of measuring the electric resistance of the YO film 3, 60 μΩ · cm
Met. This value is a value sufficiently applicable to a semiconductor memory.

On the other hand, as a comparative example, FIG.
Although a sample without the YO film 3 was separately manufactured and the same charge amount was measured, a hysteresis curve as shown in FIG. 4 could not be obtained, and it was found that the capacitor did not operate. did.

[0061] Table 1 shows the residual polarization value 2P _r in the case of using the lower electrode made of Ir ₈₀ Y ₅ O ₁₅ various diffusion barrier layer and various consisting of the material of the noble metals including. Table 2
Shows the measurement results for the comparative example.

Table 1 Example Diffusion preventing layer Lower electrode Residual polarization 2P _r ( ^{atomic%) (μC / cm 2)} --------------------------------- 1 Ir 80 Y 5 O 15 Pt _{19 2 Ir 80 Dy 5 O 15} Pt 19 3 Ir 80 Gd 5 O 15 Pt 19 4 Ru 80 Y 5 O 15 Pt 19 5 Pt 75 Y 8 O 17 Pt 19 6 Pd 85 Y 5 O 10 Pt 19 7 Rh 85 Y _{5 O 10 Pt 19 8 Ir 80} Y 5 O 15 Ir 19 9 Ir 80 Y 5 O 15 Ru 17 10 Ir 80 Y 5 O 15 Rh 14 11 Ir 80 Y 5 O 15 Pd 18 --------- −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −−−−−−−−−− Ratio Example diffusion prevention layer lower electrode residual polarization 2P _r ^{(atomic%) (μC / cm 2)} ------------------------------ --- 1 None Pt 0 2 TiN Pt Unavailable due to short-circuit ------------------------------------------------------------ As described above, according to the first embodiment, the Ir-YO film 3 having the composition shown in the shaded region in FIG. 2 is provided below the Pt film 5 as the lower electrode. Since the Ir-YO film 3 is used, the SB
Even if the heat treatment is performed in an oxidizing atmosphere at a high temperature of about 800 ° C. for crystallization when forming the T film 6, the Si substrate 1
Can be prevented from being thermally diffused into the Pt film 5, so that Si is oxidized in the upper layer of the Pt film 5 and Pt
Loss of conductivity of the film 5, ie, the lower electrode, can be prevented. Therefore, this dielectric capacitor
A transistor and a dielectric capacitor are arranged in a vertical direction,
It can be used as a dielectric capacitor in a ferroelectric memory in which a lower electrode of the dielectric capacitor is connected to a diffusion layer of a transistor by a polycrystalline Si plug, thereby achieving high integration using an SBT film as a dielectric film of the dielectric capacitor. Can be realized.

FIG. 5 shows a semiconductor integrated circuit device having a multilayer wiring structure according to a second embodiment of the present invention.

As shown in FIG. 5, in the semiconductor integrated circuit device according to the second embodiment, the n-type Si substrate 11
A p-well 12 and an n-well 13 are provided therein. A recess 14 is selectively provided on the surface of the n-type Si substrate 11 at a portion to be an element isolation region, and a field insulating film 15 made of a SiO ₂ film is embedded in the recess 14. On the surface of the active region surrounded by the field insulating film 15, a gate insulating film 16 made of a SiO ₂ film is provided. Reference numeral 17 denotes a polycrystalline S doped with impurities.
i film, 18 denotes a metal silicide film such as WSi _x film. The polycrystalline Si film 17 and the metal silicide film 18 form a gate electrode having a polycide structure. Sidewall spacers 19 made of SiO ₂ are provided on the side walls of the polycrystalline Si film 17 and the metal silicide film 18. In the n-well 13, p ⁺ -type diffusion layers 20 and 21 used as a source region or a drain region are provided in a self-alignment manner with respect to a gate electrode composed of a polycrystalline Si film 17 and a metal silicide film 18. I have. These gate electrode and diffusion layer 20,
21 form a p-channel MOS transistor. Similarly, an n-channel MOS transistor is formed in p well 12. Reference numerals 22 and 23 denote n ⁺ -type diffusion layers used as a source region or a drain region of the n-channel MOS transistor.

An interlayer insulating film 24 such as a boron phosphorus silicate glass (BPSG) film is provided so as to cover these p-channel MOS transistors and n-channel MOS transistors. In the interlayer insulating film 24, connection holes 25 and 26 are provided in a portion corresponding to the diffusion layer 21 of the p-channel MOS transistor and a portion corresponding to the gate electrode on the field insulating film 15, respectively. Inside these connection holes 25 and 26, Ir-C
A W plug 28 is buried via an EO film 27.

On the connection holes 25 and 26, Ir-Ce-
An Al—Cu alloy wiring 31 is provided via an O film 29 and a Ti film 30, and a Ti film 32 and Ir—Ce
-O films 33 are sequentially provided. The code 34 is, for example, B
1 shows an interlayer insulating film such as a PSG film. This interlayer insulating film 3
In 4, connection holes 35 and 36 are provided in portions corresponding to the Al—Cu alloy wiring 31. These connection holes 35,
A W plug 38 is buried inside 36 through an Ir-Ce-O film 37.

Further, on the connection holes 35 and 36, Ir
-Al-Cu via the Ce-O film 39 and the Ti film 40
An alloy wiring 41 is provided, and a Ti film 42 and I
An r-Ce-O film 43 is sequentially provided.

Here, the Ir—Ce—O films 27, 29, 3
The compositions of 3, 37, 39, and 43 are selected in the range indicated by the hatched area in FIG. Al-
Ti films 30 and 32 provided above and below Cu alloy wiring 31
Is provided for the purpose of improving the adhesion between the Ir—Ce—O films 29 and 33 and the Al—Cu alloy wiring 31. I provided above and below the Al-Cu alloy wiring 41
The same applies to the r-Ce-O films 39 and 43.

As described above, according to the second embodiment, the heat resistance inside the connection holes 25 and 26 is sufficiently higher than that of a TiN film or TiON film conventionally used as a barrier metal. Since the W plug 28 is formed via the Ir—Ce—O film 27 that can prevent diffusion of Si or the like even at a high temperature, the process temperature in the process after the formation of the W plug 28 is more restricted than in the related art. And the degree of freedom of the process temperature and time in the subsequent process can be increased. An Ir—Ce—O film 29 is provided between the W plug 28 and the Al—Cu alloy wiring 31 thereon.
Since the Ir—Ce—O film 33 is provided between the l-Cu alloy wiring 31 and the W plug 38 thereon, the W
Diffusion between the plugs 28 and 38 and the Al-Cu alloy wiring 31 can be prevented. Similarly, between the W plug 38 and the Al-Cu alloy wiring 41 thereon, Ir-Ce-
By providing the O film 39, diffusion between the W plug 38 and the Al—Cu alloy wiring 41 can be prevented.

The semiconductor integrated circuit device according to the second embodiment is suitable for application to MOS LSIs such as DRAMs and MPUs and various other semiconductor integrated circuit devices.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, in the first embodiment described above, the case where the SBT is used as the material of the dielectric film of the dielectric capacitor has been described. A dielectric or a high dielectric can be used, and specifically, for example, PZT or BST may be used.

Further, the Ir in the second embodiment described above.
An Ir-YO film may be used instead of the -Ce-O films 27, 29, 33, 39 and 43, and an Ir-Ce film is used instead of the Ir-YO film 3 in the first embodiment. An -O film may be used.

Further, in the above-described second embodiment, the Al-Cu alloy wiring 31 and the Ir-Ce-O film 29,
33, Ti films 30 and 32 are provided respectively.
Ti films 40 and 42 are provided between the Cu alloy wiring 41 and the Ir—Ce—O films 39 and 43, respectively, but these Ti films 30, 32, 40 and 42 are omitted as necessary. Is also good.

[0075]

As described above, according to the first, second, third or fourth aspect of the present invention, the composition formula is formed below the lower electrode of the dielectric capacitor. M _Ia
M _IIb O _c (where a, b and c are compositions expressed in atomic%, M _I is at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M _II is at least one Which represents a rare earth element), and whose composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b + c
= 100 or the lower electrode is made of this material, so that the transistor and the dielectric capacitor are arranged vertically and the lower electrode of the dielectric capacitor is made of Si or W
In the case of connection with the diffusion layer of the transistor by a plug consisting of, the diffusion of Si or W from the plug to the lower electrode can be prevented, whereby PZT as well as high-temperature material can be used as a material of the dielectric film of the dielectric capacitor. SBT or the like which requires a heat treatment may be used.

According to the fifth aspect of the present invention, the composition formula M _Ia M _IIb O is provided between the first conductive layer and the second conductive layer.
_c (where a, b and c are compositions expressed in atomic%, M _I is at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, and M _II is at least one rare earth element. And the composition range is 90 ≧ a
Since the diffusion preventing layer made of a material satisfying ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, and a + b + c = 100 is provided, the degree of freedom in the process temperature and time in the process after forming the plug is increased. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing the results of X-ray diffraction of an Ir ₈₀ Y ₅ O ₁₅ film.

2 is a schematic diagram illustrating the optimal range of composition in M _Ia M _IIb O _c used as a material for the diffusion preventing layer or the lower electrode in the present invention.

FIG. 3 is a sectional view showing the dielectric capacitor according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram showing a result of measuring a stored charge amount of the dielectric capacitor according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a conventional ferroelectric memory in which transistors and capacitors are arranged in a horizontal direction.

FIG. 7 is a cross-sectional view showing a conventional ferroelectric memory in which transistors and capacitors are arranged in a vertical direction.

FIG. 8 is a sectional view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 ... Si substrate, 2, 4 ... Ti film, 3 ... Ir
-YO film, 5, 7 ... Pt film, 6 ... SBT film,
27, 29, 33, 39, 43 ... Ir-Ce-O
Membrane, 28, 38 ... W plug

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/822 H01L 27/10 651 27/108 29/78 371 21/8242 21/8247 29/788 29/792 (72) Inventor Hitoshi Tanaka Hiroshi 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (60)

[Claims] A composition formula M _Ia M _IIb O _c (where a,
b, composition c is expressed in atomic%, M _I is Pt, Ir, R
at least one noble metal selected from the group consisting of u, Rh and Pd, and M _II represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧
a diffusion prevention layer made of a material satisfying b ≧ 2, 4 ≦ c, a + b + c = 100, a lower electrode on the diffusion prevention layer, a dielectric film on the lower electrode, and an upper electrode on the dielectric film A dielectric capacitor comprising: Wherein said M _Ia M _IIb O composition range of material expressed by _c is 85 ≧ a ≧ 65,10 ≧ b ≧ 2,10 ≦ c, a
2. The dielectric capacitor according to claim 1, wherein + b + c = 100. 3. The diffusion preventing layer is made of Ir-YO, Ir-
Ce-O, Ir-Dy-O, Ir-Gd-O, Ru-Y
-O, Pt-YO, Pd-YO or Rh-YO
2. The dielectric capacitor according to claim 1, comprising: 4. The dielectric capacitor according to claim 1, wherein said diffusion preventing layer is formed by a reactive sputtering method using oxygen or water vapor. 5. The lower electrode is composed of Pt, Ir, Ru, Rh.
2. The dielectric capacitor according to claim 1, comprising at least one noble metal selected from the group consisting of Pd and Pd. 6. The dielectric capacitor according to claim 1, wherein said dielectric film is made of a Bi-based layered structure perovskite ferroelectric. 7. The dielectric film, Bi _x (Sr, Ca,
Ba) _y (Ta, Nb) ₂ O _z (where 2.50 ≧ x
≧ 1.70, 1.20 ≧ y ≧ 0.60, z = 9 ± d,
2. The dielectric capacitor according to claim 1, comprising a ferroelectric containing 85% or more of a crystal layer represented by 1.0 ≧ d ≧ 0). 8. The dielectric film, Bi _x Sr _y Ta ₂ O
_z (However, 2.50 ≧ x ≧ 1.70, 1.20 ≧ y ≧
2. The dielectric capacitor according to claim 1, comprising a ferroelectric containing a crystal layer represented by 0.60, z = 9 ± d, 1.0 ≧ d ≧ 0) by 85% or more. 9. The dielectric capacitor according to claim 1, wherein said dielectric film is made of a ferroelectric material represented by SrBi ₂ Ta ₂ O ₉ . 10. The dielectric film is made of Pb (Zr, Ti) O.
_2. The dielectric capacitor according to claim 1, comprising a ferroelectric material represented by ₃ . 11. The dielectric film is made of (Ba, Sr) TiO.
_2. The dielectric capacitor according to claim 1, wherein the dielectric capacitor is made of a high dielectric substance represented by the following formula ( ₃ ). 12. A composition formula M _Ia M _IIb O _c (where a,
b, composition c is expressed in atomic%, M _I is Pt, Ir, R
at least one noble metal selected from the group consisting of u, Rh and Pd, and M _II represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧
A dielectric capacitor, comprising: a lower electrode made of a material satisfying b ≧ 2, 4 ≦ c, and a + b + c = 100; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. 13. The M _Ia M _IIb O composition range of material expressed by _c is 85 ≧ a ≧ 65,10 ≧ b ≧ 2,10 ≦ c,
13. The system according to claim 12, wherein a + b + c = 100.
The dielectric capacitor as described in the above. 14. The lower electrode is made of Ir-YO, Ir-
Ce-O, Ir-Dy-O, Ir-Gd-O, Ru-Y
-O, Pt-YO, Pd-YO or Rh-YO
13. The dielectric capacitor according to claim 12, comprising: 15. The dielectric capacitor according to claim 12, wherein said lower electrode is formed by a reactive sputtering method using oxygen or water vapor. 16. The dielectric film according to claim 1, wherein said dielectric film is made of a Bi-based layered structure perovskite ferroelectric.
3. The dielectric capacitor according to item 2. 17. The dielectric film, Bi _x (Sr, C
a, Ba) _y (Ta, Nb) ₂ O _z (however, 2.50
≧ x ≧ 1.70, 1.20 ≧ y ≧ 0.60, z = 9 ±
13. The dielectric capacitor according to claim 12, comprising a ferroelectric containing 85% or more of a crystal layer represented by d, 1.0 ≧ d ≧ 0). 18. The dielectric film, Bi _x Sr _y Ta ₂
O _z (However, 2.50 ≧ x ≧ 1.70, 1.20 ≧ y
13. The dielectric capacitor according to claim 12, comprising a ferroelectric material containing 85% or more of a crystal layer represented by ≧ 0.60, z = 9 ± d, 1.0 ≧ d ≧ 0). 19. The dielectric film is made of SrBi ₂ Ta ₂ O _9.
2. A ferroelectric material represented by the following formula:
3. The dielectric capacitor according to item 2. 20. The dielectric film according to claim 1, wherein the dielectric film is Pb (Zr, Ti) O.
13. The dielectric capacitor according to claim 12, comprising a ferroelectric material represented by ₃ . 21. The dielectric film is made of (Ba, Sr) TiO.
13. The dielectric capacitor according to claim 12, comprising a high dielectric substance represented by ₃ . 22. A nonvolatile memory having a memory cell comprising a transistor and a dielectric capacitor, wherein the dielectric capacitor has a composition formula M _Ia M _IIb O _c (where a, b, and c are represented by atomic%). composition, M _I is Pt, Ir, Ru, Rh and Pd
At least one noble metal selected from the group consisting of: M _II
Represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a
A non-volatile layer comprising: a diffusion prevention layer made of a material satisfying + b + c = 100; a lower electrode on the diffusion prevention layer; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. Sex memory. 23. The M _Ia M _IIb O composition range of material expressed by _c is 85 ≧ a ≧ 65,10 ≧ b ≧ 2,10 ≦ c,
23. The condition of a + b + c = 100 is satisfied.
The non-volatile memory according to claim 1. 24. The diffusion preventing layer is made of Ir—YO, Ir.
-Ce-O, Ir-Dy-O, Ir-Gd-O, Ru-
YO, Pt-YO, Pd-YO or Rh-Y-
23. The nonvolatile memory according to claim 22, comprising O. 25. The nonvolatile memory according to claim 22, wherein said diffusion preventing layer is formed by a reactive sputtering method using oxygen or water vapor. 26. The lower electrode comprises Pt, Ir, Ru, R
23. The nonvolatile memory according to claim 22, comprising at least one noble metal selected from the group consisting of h and Pd. 27. The dielectric film according to claim 2, wherein said dielectric film is made of a Bi-based layered structure perovskite ferroelectric.
2. The nonvolatile memory according to 2. 28. The method according to claim 28, wherein the dielectric film has a composition formula of Bi _x (S
r, Ca, Ba) _y (Ta, Nb) ₂ O _z (where
2.50 ≧ x ≧ 1.70, 1.20 ≧ y ≧ 0.60, z
= 9 ± d, 1.0 ≧ d ≧ 0) 85%
23. A ferroelectric material comprising the above.
The non-volatile memory according to claim 1. 29. The dielectric film composition formula Bi _x Sr _y
Ta ₂ O _z (However, 2.50 ≧ x ≧ 1.70, 1.2
23. The non-volatile memory according to claim 22, comprising a ferroelectric material containing 85% or more of a crystal layer represented by 0 ≧ y ≧ 0.60, z = 9 ± d, 1.0 ≧ d ≧ 0). memory. 30. The dielectric film is made of SrBi ₂ Ta ₂ O _9.
3. A ferroelectric material represented by the following formula:
2. The nonvolatile memory according to 2. 31. The dielectric film is made of Pb (Zr, Ti) O
23. The nonvolatile memory according to claim 22, comprising a ferroelectric material represented by ₃ . 32. The dielectric film is made of (Ba, Sr) TiO.
23. The nonvolatile memory according to claim 22, comprising a high dielectric substance represented by ₃ . 33. The nonvolatile memory according to claim 22, wherein the diffusion prevention layer is provided on a plug made of Si or W provided on the diffusion layer of the transistor. 34. The nonvolatile memory according to claim 22, further comprising a bonding layer between said diffusion preventing layer and said lower electrode. 35. The nonvolatile memory according to claim 22, further comprising a bonding layer between said plug and said diffusion preventing layer. 36. The nonvolatile memory according to claim 34, wherein said bonding layer is made of Ti or Ta. 37. The non-volatile memory according to claim 35, wherein said bonding layer is made of Ti or Ta. 38. A nonvolatile memory having a memory cell comprising a transistor and a dielectric capacitor, wherein the dielectric capacitor has a composition formula M _Ia M _IIb O _c (where a, b, and c are represented by atomic%). composition, M _I is Pt, Ir, Ru, Rh and Pd
At least one noble metal selected from the group consisting of: M _II
Represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a
A non-volatile memory, comprising: a lower electrode made of a material satisfying + b + c = 100; a dielectric film on the lower electrode; and an upper electrode on the dielectric film. 39. The M _Ia M _IIb O composition range of material expressed by _c is 85 ≧ a ≧ 65,10 ≧ b ≧ 2,10 ≦ c,
39. The system according to claim 38, wherein a + b + c = 100.
The non-volatile memory according to claim 1. 40. The lower electrode is made of Ir-YO, Ir-
Ce-O, Ir-Dy-O, Ir-Gd-O, Ru-Y
-O, Pt-YO, Pd-YO or Rh-YO
39. The non-volatile memory according to claim 38, comprising: 41. The nonvolatile memory according to claim 38, wherein the lower electrode is formed by a reactive sputtering method using oxygen or water vapor. 42. The dielectric film according to claim 3, wherein the dielectric film is made of a Bi-based layered structure perovskite ferroelectric.
8. The nonvolatile memory according to 8. 43. The dielectric film according to claim 42, wherein the composition formula is Bi _x (S
r, Ca, Ba) _y (Ta, Nb) ₂ O _z (where
2.50 ≧ x ≧ 1.70, 1.20 ≧ y ≧ 0.60, z
= 9 ± d, 1.0 ≧ d ≧ 0) 85%
39. A ferroelectric material comprising the above.
The non-volatile memory according to claim 1. 44. The dielectric film composition formula Bi _x Sr _y
Ta ₂ O _z (However, 2.50 ≧ x ≧ 1.70, 1.2
39. The non-volatile memory according to claim 38, comprising a ferroelectric material containing 85% or more of a crystal layer represented by 0 ≧ y ≧ 0.60, z = 9 ± d, 1.0 ≧ d ≧ 0). memory. 45. The dielectric film is made of SrBi ₂ Ta ₂ O ₉
4. A ferroelectric material represented by the following formula:
8. The nonvolatile memory according to 8. 46. The dielectric film is made of Pb (Zr, Ti) O.
39. The nonvolatile memory according to claim 38, comprising a ferroelectric material represented by ₃ . 47. The dielectric film is made of (Ba, Sr) TiO.
39. The non-volatile memory according to claim 38, wherein the non-volatile memory is made of a high dielectric substance represented by ₃ . 48. The nonvolatile memory according to claim 38, wherein said lower electrode is provided on a plug made of Si or W provided on a diffusion layer of said transistor. 49. The nonvolatile memory according to claim 38, further comprising a bonding layer between said plug and said lower electrode. 50. The nonvolatile memory according to claim 49, wherein said bonding layer is made of Ti or Ta. 51. A semiconductor device having a first conductive layer and a second conductive layer on the first conductive layer, wherein: between the first conductive layer and the second conductive layer, Compositional formula M _Ia M _IIb O _c (where a, b and c are compositions expressed in atomic%, M _I is at least one noble metal selected from the group consisting of Pt, Ir, Ru, Rh and Pd, M _II Represents at least one rare earth element), and its composition range is 90 ≧ a ≧ 40, 15 ≧ b ≧ 2, 4 ≦ c, a + b +
A semiconductor device provided with a diffusion prevention layer made of a material having c = 100. 52. The M _Ia M _IIb O composition range of material expressed by _c is 85 ≧ a ≧ 65,10 ≧ b ≧ 2,10 ≦ c,
52. The equation a + b + c = 100.
13. The semiconductor device according to claim 1. 53. The diffusion preventing layer is made of Ir—YO, Ir
-Ce-O, Ir-Dy-O, Ir-Gd-O, Ru-
YO, Pt-YO, Pd-YO or Rh-Y-
52. The semiconductor device according to claim 51, comprising O. 54. The semiconductor device according to claim 51, wherein said diffusion preventing layer is formed by a reactive sputtering method using oxygen or water vapor. 55. The semiconductor device according to claim 51, wherein said first conductive layer is a diffusion layer made of Si, and said second conductive layer is a plug made of a conductive material. 56. The semiconductor device according to claim 55, wherein said plug is made of Si, W or Al. 57. The semiconductor device according to claim 51, wherein said first conductive layer is a plug made of a conductive material, and said second conductive layer is an Al alloy wiring. 58. The semiconductor device according to claim 57, wherein said plug is made of Si, W or Al. 59. The semiconductor device according to claim 51, wherein said first conductive layer is an Al alloy wiring, and said second conductive layer is a plug made of a conductive material. 60. The semiconductor device according to claim 59, wherein said plug is made of Si, W or Al.