JP3597328B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a memory cell in which a capacitive insulating film of a capacitive element (capacitor) is made of a high dielectric material. It is.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a large-capacity dynamic random access memory (DRAM) has a stacked capacitor in which a capacitor is arranged above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the capacitor due to miniaturization of a memory cell. It employs a stacked capacitor structure. Further, a lower electrode (storage electrode) of the capacitor is processed into a fin or a cylinder to increase its surface area, or a capacitor insulating film is made of a material having a high dielectric constant. In particular, tantalum oxide (Ta) which is one of high dielectric materials ₂ O ₅ ) Has a high dielectric constant of 20 to 25 and is highly compatible with the conventional DRAM process, and is therefore being applied to a capacitive element of a DRAM.
[0003]
When the capacitor insulating film of the capacitor is formed of the above-described tantalum oxide, it is necessary to select a material that does not deteriorate the film quality of the tantalum oxide as a material of the upper electrode (plate electrode) formed on the capacitor insulating film. As such an upper electrode material, a refractory metal such as W (tungsten), Pt (platinum), and Mo (molybdenum) or a refractory metal nitride such as TiN (titanium nitride) is considered to be suitable.
[0004]
"Applied physics (Jpn. J. Appl. Phys. Vol. 33 (1994) Pt. 1, No. 3A)", which examined the effect of the upper electrode material on the leak current before and after annealing on the tantalum oxide film, Based on the experimental results that the work function of the upper electrode material and the stability of the upper electrode / tantalum oxide interface determine the electrical properties of the tantalum oxide film, the optimum upper electrode material is obtained by annealing at a low temperature (about 400 ° C.). It is reported to be TiN when performed and Mo or MoN (molybdenum nitride) when performed at high temperatures (about 800 ° C.).
[0005]
Since the lower electrode of the capacitor element of the DRAM has a complicated surface shape as described above, when depositing a tantalum oxide film thereon, a CVD (Chemical Vapor Deposition) method having better step coverage than the sputtering method is used. Is required. However, a tantalum oxide film deposited by the CVD method cannot obtain a desired dielectric constant as it is, and therefore it is necessary to crystallize the film by performing annealing at a high temperature of about 700 to 800 ° C. after film formation. However, when this annealing is performed, an oxide film is formed at the interface with the underlying lower electrode material (polycrystalline silicon film), which lowers the effective dielectric constant of the capacitive insulating film and reduces the oxygen in the tantalum oxide film. Insufficiency causes a problem that the withstand voltage of the film is reduced and the leak current is increased.
[0006]
Japanese Patent Application Laid-Open No. 61-3548 discloses that a surface of a tantalum oxide film deposited on a semiconductor substrate by a CVD method is annealed in a dry oxygen atmosphere to recover defects caused by oxygen vacancies in the film. A technique for improving the dielectric strength is disclosed.
[0007]
"International Conference on Solidstate Devices and Materials 1992" (p521 to p523) uses a polycrystalline silicon film constituting a lower electrode of a capacitor element by NH. ₃ It discloses a technique for preventing an oxide film from being formed on the surface of a polycrystalline silicon film when a tantalum oxide film is deposited by annealing in an (ammonia) atmosphere to form a nitride film on the surface. .
[0008]
A DRAM described in Japanese Patent Application Laid-Open No. 7-66300 discloses a tantalum oxide and a strontium titanate (SrTiO) in which a capacitive insulating film of a capacitive element is deposited by a CVD method. ₃ ) Or barium titanate (BaTiO) ₃ ), And the upper electrode is made of W, Pt, TiN or the like deposited by the CVD method or the sputtering method. Then, the lower electrode is made of zinc oxide (ZnO) or tin oxide (SnO). ₂ By using a material having a strong resistance to oxidation as in (1), formation of an oxide film at the interface with the lower electrode during annealing of the capacitive insulating film is prevented.
[0009]
In the DRAM described in Japanese Patent Application Laid-Open No. 7-66369, a capacitive insulating film of a capacitive element is made of tantalum oxide deposited by a CVD method. Then, annealing after film formation is performed at a temperature lower than the crystallization temperature (about 600 ° C. or less), and by maintaining the film in an amorphous structure, generation of crystal grain boundaries, cracks, and micro defects serving as a path of a leak current is performed. This improves the leakage current characteristics.
[0010]
In the DRAM described in Japanese Patent Application Laid-Open No. 1-222469, tantalum oxide or hafnium oxide (HfO) in which a capacitive insulating film of a capacitive element is deposited by a CVD method. ₂ ), And a barrier film of TiN is formed between the tantalum oxide (or hafnium oxide) and the polycrystalline silicon electrodes (upper and lower electrodes) to prevent the reaction between silicon and tantalum oxide. I have.
[0011]
In the DRAM described in Japanese Patent Application Laid-Open No. 6-232344, a capacitive insulating film of a capacitive element is made of tantalum oxide or hafnium oxide deposited by a CVD method, and an upper electrode is made of TiN. Then, by forming a non-metallic buffer film such as polycrystalline silicon on the TiN, the BPSG (Boron-doped Phospho Silicate Glass) film deposited on the capacitor is reflowed at a high temperature (about 850 ° C., 30 minutes). This prevents the capacitive element from deteriorating during the operation.
[0012]
[Problems to be solved by the invention]
The present inventors have deposited a conductive film such as polycrystalline silicon on a semiconductor substrate, deposited a tantalum oxide film thereon, ₄ (Titanium tetrachloride), TDAT (tetraxydimethylaminotitanium), TDEAT (tetraxydiethylaminotitanium) or other titanium-containing source gas; ₃ A TiN film was deposited on the tantalum oxide film by a CVD method using a nitrogen-containing reducing gas such as MMH (monomethylhydrazine). Then, a capacitor was formed by patterning these films, and the withstand voltage of the capacitor insulating film (tantalum oxide film) was examined. As a result, a phenomenon in which the withstand voltage was deteriorated and the leak current increased was observed.
[0013]
Although the cause has not been fully elucidated yet, when the surface of the tantalum oxide film contacts the reducing gas at a high temperature, some of the oxygen (O) atoms in the film react with the reducing gas and are separated. The present inventors speculate that one of the causes is an increase in dangling bonds (unbonded bonds) of Ta and O in the film.
[0014]
An object of the present invention is to provide a method of depositing an upper electrode material by a CVD method using a reactive gas containing a reducing gas on a capacitive insulating film formed of a high dielectric material such as tantalum oxide. It is an object of the present invention to provide a technique capable of preventing a problem that the breakdown voltage is deteriorated.
[0015]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0017]
A semiconductor integrated circuit device according to the present invention includes a lower electrode, a capacitor insulating film including one or more films including a high dielectric film formed on the lower electrode, and titanium formed on the capacitor insulating film. A capacitor composed of a single electrode or a plurality of films including a nitride film, wherein the upper electrode of the capacitor is formed by a low-temperature CVD method under a condition not containing a reducing gas. It is formed on the high dielectric film with a protective film interposed.
[0018]
In the semiconductor integrated circuit device according to the present invention, the capacitance insulating film includes a tantalum oxide film.
[0019]
In the semiconductor integrated circuit device according to the present invention, the capacitance element is disposed above a memory cell selection MISFET constituting a memory cell of the DRAM.
[0020]
A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
[0021]
(A) forming a first conductive film constituting a lower electrode of a capacitor on a main surface of a semiconductor substrate;
(B) forming a capacitance insulating film composed of a single film or a plurality of films including a high dielectric film on the first conductive film;
(C) forming a protective film on the capacitive insulating film by a low-temperature CVD method under a condition not containing a reducing gas;
(D) forming a second conductive film made of a single or plural films including a titanium nitride film constituting an upper electrode of the capacitor on the protective film;
[0022]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the capacitance insulating film includes a tantalum oxide film.
[0023]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the protective film includes an amorphous titanium film or a polycrystalline titanium film.
[0024]
In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the capacitance element is arranged above a memory cell selecting MISFET constituting a memory cell of a DRAM.
[0025]
The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a step of patterning at least a part of a lower electrode of the capacitor into a fin shape or a cylindrical shape.
[0026]
A method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.
[0027]
(A) forming a MISFET on a main surface of a semiconductor substrate;
(B) forming a first conductive film composed of a single film or a plurality of films on the MISFET;
(C) patterning at least a part of the first conductive film into a fin shape or a cylindrical shape to form a lower electrode of the capacitor;
(D) forming a capacitive insulating film composed of a single or a plurality of films including a high dielectric film on the lower electrode;
(E) forming a protective film on the capacitive insulating film by a low-temperature CVD method under a condition including a titanium-containing source gas and no nitrogen-containing reducing gas;
(F) forming a second conductive film composed of a single film or a plurality of films including a titanium nitride film on the protective film by a low-temperature CVD method under a condition including a titanium-containing source gas and a nitrogen-containing reducing gas; Process,
(G) forming an upper electrode of the capacitive element by patterning the second conductive film, the protective film, and the capacitive insulating film.
[0028]
In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the protective film and the second conductive film are formed by introducing the titanium-containing source gas into a chamber of a CVD device and then introducing the nitrogen-containing reducing gas. Are continuously formed.
[0029]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the capacitance insulating film includes a tantalum oxide film.
[0030]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the protective film includes an amorphous titanium film or a polycrystalline titanium film.
[0031]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the titanium-containing source gas contains titanium tetrachloride, tetraxydimethylaminotitanium, tetraxydiethylaminotitanium, or a mixed gas thereof.
[0032]
In the method for manufacturing a semiconductor integrated circuit device according to the present invention, the nitrogen-containing reducing gas contains ammonia, monomethylhydrazine, or a mixed gas thereof.
[0033]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0034]
(Embodiment 1)
In this embodiment, a memory having a capacitor over bitline (COB) structure in which a bit line is arranged above a memory cell selection MISFET and an information storage capacitor is arranged above the bit line. This is applied to a DRAM having cells.
[0035]
In order to form this memory cell, first, as shown in FIG. 1, a p-type impurity (boron) was ion-implanted into a main surface of a semiconductor substrate 1 made of p-type single crystal silicon to form a p-type well 2. Thereafter, a field oxide film 3 for element isolation and a gate oxide film 4 are formed on the surface of the p-type well 2 by a known LOCOS method. Next, a p-type impurity (boron) is ion-implanted into the p-type well 2 including the lower portion of the field oxide film 3 to form a p-type channel stopper layer 5 for element isolation.
[0036]
Next, as shown in FIG. 2, the gate electrode 6 of the memory cell selecting MISFET (and the word line WL integrally formed with the gate electrode 6) is formed on the p-type well 2. As the gate electrode 6 (word line WL), a polycrystalline silicon film (or a polycide film in which a polycrystalline silicon film and a high melting point metal silicide film are laminated) and a silicon oxide film 7 are deposited on the p-type well 2 by the CVD method. Then, these films are patterned and formed by etching using a photoresist as a mask.
[0037]
Next, as shown in FIG. 3, an n-type impurity (phosphorus) is ion-implanted into the p-type well 2 to form an n-type semiconductor region 8 (source region, drain region) of the memory cell selecting MISFET. Subsequently, as shown in FIG. 4, after forming a sidewall spacer 9 on the side wall of the gate electrode 6 (word line WL), a silicon oxide film 10 is deposited by a CVD method. The sidewall spacer 9 is formed by patterning a silicon oxide film deposited by a CVD method by a reactive ion etching method.
[0038]
Next, as shown in FIG. 5, the silicon oxide film 10 and the gate oxide film 4 on one of the source and drain regions (the n-type semiconductor region 8) of the memory cell selecting MISFET are opened to form the connection holes 11. After the formation, an n-type polycrystalline silicon film 12 is deposited on the silicon oxide film 10 by a CVD method, and then, as shown in FIG. 6, the polycrystalline silicon film 12 is patterned.
[0039]
Next, as shown in FIG. 7, after the BPSG film 13 deposited by the CVD method is reflowed to flatten its surface, the other of the source and drain regions (n-type semiconductor regions 8) of the memory cell selecting MISFET is formed. The connection hole 14 is formed by opening the upper BPSG film 13, the silicon oxide film 10, and the gate oxide film 4.
[0040]
Next, as shown in FIG. 8, an n-type polycrystalline silicon film deposited by a CVD method on the BPSG film 13 is patterned to form a bit line BL connected to the n-type semiconductor region 8 through the connection hole 14. Form. The bit line BL may be formed of a laminated film of a TiN film and a W film deposited by a sputtering method.
[0041]
Next, as shown in FIG. 9, after a silicon oxide film 15, a silicon nitride film 16 and a silicon oxide film 17 are sequentially deposited on the BPSG film 13 by the CVD method, as shown in FIG. The silicon oxide film 17, the silicon nitride film 16 and the silicon oxide film 15 on the upper portion of the substrate are opened to form a connection hole 18 reaching the polycrystalline silicon film 12.
[0042]
Next, as shown in FIG. 11, an n-type polycrystalline silicon film 19 is deposited on the silicon oxide film 17 by a CVD method, and then a silicon oxide film 20 is deposited on the polycrystalline silicon film 19 by a CVD method. I do. Subsequently, as shown in FIG. 12, after patterning the silicon oxide film 20 in a columnar shape and leaving it only inside and above the connection hole 18, an n-type polycrystalline silicon film 21 is deposited by a CVD method.
[0043]
Next, as shown in FIG. 13, after the polycrystalline silicon film 21 is patterned by the reactive ion etching method and left only on the side wall of the cylindrical silicon oxide film 20, the lower polycrystalline silicon film 21 is polycrystalline. The silicon film 19 is patterned so as to remain only under the silicon oxide film 20 and the polycrystalline silicon film 21 on the side wall thereof.
[0044]
Next, as shown in FIG. 14, the silicon oxide film 20 and the underlying silicon oxide film 17 are removed using a wet etching solution such as a hydrofluoric acid aqueous solution. At this time, since the silicon nitride film 16 under the silicon oxide film 17 serves as an etching stopper, the silicon oxide film 15 and the BPSG film 13 below the silicon nitride film 16 are not removed. As a result, a cylindrical (crown-shaped) lower electrode 22 composed of three layers of polycrystalline silicon films 12, 19, and 20 is obtained.
[0045]
Next, as shown in FIG. 15, a thin silicon nitride film 23 is deposited on the surface of the lower electrode 22 by the CVD method, and a thin tantalum oxide film 24 is deposited on the surface of the silicon nitride film 23 by the CVD method. A capacitance insulating film 25 of an information storage capacitor composed of a laminated film of a silicon nitride film 23 and a tantalum oxide film 24 is formed. The tantalum oxide film 24 is made of, for example, Ta (OC ₂ H ₅ ) (Ethoxy tantalum) is deposited as a reaction gas at a temperature of about 400 ° C., and then annealed at a temperature of about 700 to 1000 ° C. using an electric furnace or a lamp annealing apparatus. Since the silicon nitride film is provided between the tantalum oxide film 24 and the storage electrode, the tantalum oxide film 24 and the lower electrode 22 (polycrystalline silicon film) react during this high-temperature annealing to oxidize the interface between them. No objects are formed.
[0046]
Next, the semiconductor substrate 1 is carried into the chamber 41 of the CVD apparatus 40 shown in FIG. 18 in order to form an upper electrode of the information storage capacitor element on the capacitor insulating film 25.
[0047]
As shown in FIG. ₄ , TDMAT, TDEAT, etc., and NH used to make the composition ratio of Ti and N in the TiN film close to 1: 1. ₃ , MMH or other nitrogen-containing reducing gas, and He (helium), Ar (argon), N ₂ Inert gas such as (nitrogen) is introduced into the chamber 41 through individual gas supply pipes. With such a structure, it is possible to prevent a problem that gases react with each other in the middle of the gas supply pipe and a reactant is deposited in the pipe.
[0048]
The CVD apparatus 40 selectively opens or closes only one of the nitrogen-containing reducing gas and the inert gas in the chamber 41 by adjusting the opening and closing of the valves 42 and 43 provided in the middle of the gas supply pipe. It has a structure that can be introduced.
[0049]
Further, in the CVD apparatus 40, a vacuum pump 45 different from the vacuum pump 44 for adjusting the degree of vacuum in the chamber 41 is connected in the middle of a gas supply pipe for introducing a nitrogen-containing reducing gas into the chamber 41. Have been. With such a structure, a part of the gas in the gas supply pipe is evacuated by the vacuum pump 45 in the initial stage of introducing the nitrogen-containing reducing gas into the chamber 41, so that the excess nitrogen is instantaneously introduced into the chamber 41. The disadvantage that the contained reducing gas is introduced can be prevented.
[0050]
In this embodiment, after the semiconductor substrate 1 is carried into the chamber 41 of the CVD apparatus 40, the inside of the chamber 41 is first evacuated to a predetermined degree of vacuum by the vacuum pump 44, and then the predetermined amount is By introducing a flow rate of a titanium-containing source gas and an inert gas and thermally decomposing the titanium-containing source gas at about 300 to 600 ° C., more preferably at about 400 to 450 ° C., as shown in FIG. A thin amorphous Ti film 26 is deposited along the surface of the film 24. Note that N is used as an inert gas. ₂ Or N ₂ When a mixed gas of TiO 2 and another inert gas is used, the amorphous Ti film 26 partially containing amorphous TiN may be formed, but this does not cause any problem.
[0051]
Next, predetermined flow rates of a titanium-containing source gas, a nitrogen-containing reducing gas, and an inert gas are introduced into the chamber 41 of the CVD apparatus 40, and as shown in FIG. Is deposited to form a TiN film 27 on top of the amorphous Ti film 26, thereby forming an upper electrode 28 of the information storage capacitor composed of a laminated film of the amorphous Ti film 26 and the TiN film 27.
[0052]
According to the above method, since the surface of the tantalum oxide film 24 is covered with the amorphous Ti film 26, the nitrogen-containing reducing gas does not come into contact with the tantalum oxide film 24. Therefore, the deterioration of the pressure resistance of the tantalum oxide film due to the nitrogen-containing reducing gas is reliably prevented. Further, in the initial stage of introducing the nitrogen-containing reducing gas into the chamber 41, a part of the gas in the gas supply pipe is exhausted by the vacuum pump 45, so that the excessive nitrogen-containing reducing gas is not instantaneously introduced into the chamber 41. By doing so, the composition of Ti and N in the TiN film 27 can be made closer to the optimum value (Ti: N = 1: 1).
[0053]
As described above, according to the present embodiment, when the TiN film 27 is deposited by the CVD method on the tantalum oxide film 24 constituting the capacitive insulating film 25 of the information storage capacitor element to form the upper electrode 28, By forming the amorphous Ti film 26 that does not allow the nitrogen-containing reducing gas to pass through the surface of the tantalum oxide film 24 in advance, it is possible to reliably prevent the withstand voltage deterioration (increase in leak current) of the tantalum oxide film 24. A DRAM with improved refresh characteristics can be realized.
[0054]
(Embodiment 2)
FIG. 19 is a block diagram of the DRAM of the present embodiment, and FIG. 20 is a circuit diagram of a memory array and a sense amplifier of the DRAM.
[0055]
In the DRAM of the present embodiment, a memory array MARY occupying a main portion of a main surface of a semiconductor substrate is a basic component. As shown in FIG. 20, the memory array MARY has m + 1 word lines (W0-Wm) arranged in parallel in the vertical direction and n + 1 pairs of complementarity arranged in parallel in the horizontal direction. Bit lines (non-inverted bit lines BOT-BNT and inverted bit lines BOB-BNB). At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) memory cells each composed of an information storage capacitance element (Cs) and a memory cell selection MISFET Qa are arranged in a lattice.
[0056]
The drain regions of the memory cell selecting MISFETs Qa of the m + 1 memory cells arranged in the same column of the memory array MARY are alternately connected to the corresponding non-inverted or inverted signal lines of complementary bit lines with a predetermined regularity. I have. Further, the gate electrodes of the memory cell selecting MISFETs Qa of the n + 1 memory cells arranged in the same row of the memory array MARY are integrally coupled to the corresponding word lines. A predetermined plate voltage VP is commonly supplied to the other electrodes of the information storage capacitance elements (Cs) of all the memory cells constituting the memory array MARY.
[0057]
The word lines (W0-Wm) constituting the memory array MARY are coupled to the X address decoder XD below the memory array MARY, and are selectively selected. The X address decoder XD is supplied with an (i + 1) -bit internal address signal (X0-Xi) from the X address buffer XB, and is supplied with an internal control signal XDG from the timing generation circuit TG. The X address buffer (XB) is supplied with an X address signal (XA0-XAi) in a time-division manner via an address input terminal (A0-Ai), and is supplied with an internal control signal XL from a timing generation circuit TG.
[0058]
The X address buffer XB takes in and holds an X address signal (XA0-XAi) supplied via an address input terminal (A0-Ai) in accordance with the internal control signal XL, and based on these X address signals, an internal address. A signal (X0-Xi) is formed and supplied to the X address decoder XD. Further, X address decoder XD is selectively activated in response to the high level of internal control signal XDG, decodes internal address signals (X0-Xi), and responds to corresponding word lines (W0-X) of memory array MARY. Wm) is alternatively set to a high-level selection state.
[0059]
Complementary bit lines (BOT-BNT, BOB-BNB) constituting the memory array MARY are coupled to a sense amplifier SA, and are alternatively connected to a complementary common data line CD via the sense amplifier SA. To the sense amplifier SA, a bit line selection signal (YS0-YSn) of n + 1 bits is supplied from the Y address decoder YD, and an internal control signal PA is supplied from the timing generation circuit TG. The Y address decoder YD is supplied with an (i + 1) -bit internal address signal (Y0-Yi) from the Y address buffer YB, and is supplied with an internal control signal YDG from the timing generation circuit TG. Further, a Y address signal (AY0-AYi) is supplied to the Y address buffer YB via an address input terminal (A0-Ai) in a time-division manner, and an internal control signal YL is supplied from a timing generation circuit TG.
[0060]
The Y address buffer YB captures and holds a Y address signal (AY0-AYi) supplied via an address input terminal (A0-Ai) in accordance with an internal control signal YL, and based on these Y address signals, an internal address. A signal (Y0-Yi) is formed and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated when the internal control signal YDG is set to the high level, decodes the internal address signal (Y0-Yi), and outputs the corresponding bit line select signal (YS0-Yi). YSn) is alternatively set to a high level selection state.
[0061]
The sense amplifier SA includes n + 1 unit circuits provided corresponding to the complementary bit lines of the memory array MARY. Although these unit circuits are not particularly limited, as illustrated in FIG. 20, a pair of n-channel MISFETs N1 provided between the non-inverting and inverting signal lines of the complementary bit lines are provided. ₅ , N ₆ -Line MISFET P ₁ And n-channel MISFETN ₁ Inverter and p-channel type MISFETP ₂ And n-channel MISFETN ₂ And a unit amplifier circuit formed by cross-coupled CMOS inverters. Among them, the n-channel MISFET N constituting the bit line precharge circuit of each unit circuit ₅ , N ₆ The internal voltage HV is commonly supplied to the source regions which are commonly coupled, and the internal control signal PC is commonly supplied to its gate electrode. The internal voltage HV is an intermediate potential between the power supply voltage of the circuit and the ground potential. Further, the internal control signal PC is selectively set to a high level when the memory cell is set to the non-selected state. Thereby, the n-channel MISFET N ₅ , N ₆ Are selectively and simultaneously turned on when the memory cell is in the non-selected state and the internal control signal PC is set to the high level, and the non-inverted and inverted signal lines of the corresponding complementary bit lines of the memory array MARY are Is precharged to the internal voltage HV.
[0062]
On the other hand, a p-channel type MISFET P constituting a unit amplifier circuit of each unit circuit ₁ , P ₂ Are commonly coupled to a common source line SP. The common source line SP is a p-channel type driving MISFET P receiving at its gate electrode an inverted signal of the internal control signal PA by the inverter Vl, that is, an inverted internal control signal PAB. ₃ To the power supply voltage of the circuit. Similarly, an n-channel MISFET N constituting a unit amplifier circuit of each unit circuit ₁ , N ₂ Are commonly coupled to a common source line SN. The common source line SN is an n-channel driving MISFET N receiving an internal control signal PA at its gate electrode. ₇ To the ground potential of the circuit. As a result, each unit amplifier circuit is selectively and simultaneously activated by the internal control signal PA being set to the high level and the inverted internal control signal PAB being set to the low level, and the memory array MARY is selected. The small read signal output from the (n + 1) memory cells coupled to the word line via the corresponding complementary bit line is amplified to be a high level or low level binary read signal.
[0063]
Further, each unit circuit of the sense amplifier SA includes a pair of n-channel switches MISFETN provided between the non-inverted and inverted input / output nodes of the unit amplifier circuit and the complementary common data line CD. ₃ , N ₄ Respectively. The gate electrodes of these switch MISFET pairs are commonly coupled, and corresponding bit line selection signals (YS0-YSn) are supplied from the Y address decoder YD. Thereby, the switch MISFETN of each unit circuit ₃ , N ₄ Are selectively turned on when the corresponding bit line selection signal (YS0-YSn) is set to the high level, and the corresponding unit amplifier circuit of the sense amplifier SA, that is, the corresponding l sets of complementary bits of the memory array MARY. The line and the complementary common data line CD are selectively connected.
[0064]
A complementary common data line CD to which a designated pair of complementary bit lines of the memory array MARY are alternatively connected is connected to a data input / output circuit IO. The data input / output circuit IO includes a write amplifier and a main amplifier (not shown), a data input buffer, and a data output buffer. Among these, the output terminal of the write amplifier and the input terminal of the main amplifier are commonly connected to a complementary common data line CD. The input terminal of the write amplifier is coupled to the output terminal of the data input buffer, and the input terminal of the data input buffer is coupled to the data input terminal Din. The output terminal of the main amplifier is connected to the input terminal of the data output buffer, and the output terminal of the data output buffer is connected to the data output terminal Dout.
[0065]
When the memory cell is selected in the write mode, the data input buffer of the data input / output circuit IO takes in the write data supplied via the data input terminal Din and transmits it to the write amplifier. This write data is converted into a predetermined complementary write signal by the write amplifier, and then written to the selected one memory cell of the memory array MARY via the complementary common data line CD. On the other hand, when the memory cell is selected in the read mode, the main amplifier of the data input / output circuit IO outputs a binary read signal output from the selected memory cell of the memory array MARY via the complementary common data line CD. Is further amplified and transmitted to the data output buffer. The read data is sent from the data output buffer to the outside via the data output terminal Dout.
[0066]
The timing generation circuit TG selectively forms the above various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB and a write enable signal WEB supplied from the outside as a start control signal, and Supply to each part.
[0067]
Next, a method of manufacturing the DRAM of the present embodiment will be described with reference to FIGS.
[0068]
In order to manufacture this DRAM, first, as shown in FIG. ⁻ After oxidizing the surface of the semiconductor substrate 1 made of type single crystal silicon to form a thin silicon oxide film 53, a silicon nitride film 54 is deposited on the silicon oxide film 53 using a CVD method, and then using a photoresist as a mask. The silicon nitride film 54 in the element isolation region is removed by etching the lever silicon nitride film 54.
[0069]
Next, as shown in FIG. 22, the field oxide film 3 is formed by annealing the semiconductor substrate 1 using the silicon nitride film 54 as a mask. Next, after removing the silicon nitride film 54, as shown in FIG. 23, a p-type impurity (boron (B)) is added to the semiconductor substrate 1 in the region where the memory array is formed and the region where the n-channel MISFET of the peripheral circuit is formed. ) Is implanted to form a p-type well 2. Further, an n-type well (55) is formed by ion-implanting an n-type impurity (phosphorus (P)) into the semiconductor substrate 1 in a region where a p-channel MISFET of a peripheral circuit is formed. Subsequently, a p-type impurity (B) is ion-implanted into the p-type well 2 to form a p-type channel stopper layer 5, and an n-type impurity (P) is ion-implanted into the n-type well 55 to form an n-type channel stopper layer. 6 is formed. Thereafter, the surfaces of the active regions of the p-type well 2 and the n-type well 55 surrounded by the field oxide film 3 are thermally oxidized to form the gate oxide film 4.
[0070]
Next, as shown in FIG. 24, the gate electrode 6A (word line WL) of the memory cell selecting MISFET, the gate electrode 6B of the n-channel MISFET of the peripheral circuit, and the gate electrode 6C of the p-channel MISFET are formed. The gate electrode 6A (word line WL) and the gate electrodes 6B and 6C are formed by depositing a tungsten (W) film on the semiconductor substrate 1 using a CVD method, and then forming a silicon nitride film on the W film using a plasma CVD method. After the films 57 are deposited, these films are patterned and formed simultaneously by etching using a photoresist as a mask.
[0071]
Next, as shown in FIG. 25, an n-type impurity (P) is ion-implanted into the p-type well 2 and a p-type impurity (B) is ion-implanted into the n-type well 55. By annealing performed in a later step, the n-type impurity (P) causes the n-type semiconductor region 8 (source region and drain region) of the memory cell selecting MISFET and the n-type MISFET n of the peripheral circuit to be formed. ⁻ Semiconductor region 58 is formed, and p-type impurity (B) is used to form p-type MISFETs of the peripheral circuit. ⁻ A type semiconductor region 59 is formed.
[0072]
Next, as shown in FIG. 26, after sidewall spacers 9 are formed on the respective side walls of the gate electrode 6A (word line WL) and the gate electrodes 6B and 6C, the n-type impurities ( P) is ion-implanted, and a p-type impurity (B) is ion-implanted into the n-type well 55. The side wall spacer 9 is formed by depositing a silicon nitride film on the semiconductor substrate 1 by using a plasma CVD method and then processing the silicon nitride film by anisotropic etching.
[0073]
Next, as shown in FIG. 27, the semiconductor substrate 1 is annealed in a nitrogen atmosphere to diffuse the n-type impurity (P) and the p-type impurity, thereby forming the n-type semiconductor region 8 of the MISFET for memory cell selection. (Source region, drain region) and n of the n-channel MISFET of the peripheral circuit. ⁻ Semiconductor region 58 and n ⁺ Semiconductor region 60 and p-channel MISFET p ⁻ Semiconductor region 59 and p ⁺ And a mold semiconductor region 61. Each of the source region and the drain region of the n-channel MISFET of the peripheral circuit has n ⁻ Semiconductor region 58 and n ⁺ And a LDD (Lightly Doped Drain) structure composed of a p-type MISFET and a p-type MISFET. ⁻ Semiconductor region 59 and p ⁺ It has an LDD structure composed of the mold semiconductor region 61.
[0074]
Next, as shown in FIG. 28, a silicon oxide film 62 is deposited on each of the memory cell selecting MISFET, the n-channel MISFET of the peripheral circuit, and the p-channel MISFET by using the plasma CVD method. The silicon oxide film 62 is polished by a chemical mechanical polishing (CMP) method to planarize the surface, and then the silicon oxide film 62 and the gate oxide film 4 are etched by using a photoresist as a mask. Connection holes 63 and 64 are formed above the n-type semiconductor region 8 (source region and drain region) of the memory cell selecting MISFET, and n of the n-channel MISFET of the peripheral circuit is formed. ⁺ Connection holes 65 and 66 are formed above the type semiconductor region 60 (source region and drain region), and the p-type MISFET p ⁺ Connection holes 67 and 68 are formed above the type semiconductor region 61 (source region and drain region).
[0075]
At this time, the silicon nitride film 57 formed on the gate electrode 6A (word line WL) of the memory cell selection MISFET and the silicon nitride sidewall spacer 9 formed on the side wall are only slightly etched. The connection holes 63 and 64 are formed by self-alignment (self-alignment). Similarly, the silicon nitride film 57 formed on each of the gate electrode 6B of the n-channel MISFET and the gate electrode 6C of the p-channel MISFET of the peripheral circuit, and the silicon nitride sidewall spacer 9 formed on the side wall are: The connection holes 65 to 68 are formed by self-alignment (self-alignment) because they are only slightly etched.
[0076]
As an insulating film deposited on the memory cell selecting MISFET, the n-channel MISFET and the p-channel MISFET of the peripheral circuit, in addition to the silicon oxide film 62, ozone (O ₃ ) -BPSG film, ozone-TEOS (Tetra Ethoxy Silane) deposited using a CVD method, or the like can be used. Like the silicon oxide film 62, the surfaces of these insulating films are planarized by a chemical mechanical polishing (CMP) method.
[0077]
Next, as shown in FIG. 29, plugs 69 made of a laminated film of TiN and W are buried in the connection holes 63 to 68. The plug 69 is formed by depositing a TiN film serving as an adhesive layer between the substrate and the W film on the silicon oxide film 62 by a sputtering method, and then depositing a W film on the TiN film by a CVD method. After that, the W film and the TiN film are formed by etching back.
[0078]
At this time, in order to reduce the contact resistance between the plug 69 and the substrate, Ti silicide (TiSi ₂ ) A layer may be formed. The Ti silicide layer is formed by depositing a Ti film on the silicon oxide film 62 using a sputtering method, and reacting the Ti film with the substrate at the bottom of the connection holes 63 to 68 by annealing at about 800 ° C. The unreacted Ti film remaining on the silicon film 62 is formed by removing by wet etching. Thereafter, the TiN film and the W film deposited on the silicon oxide film 62 are etched back to form plugs 69.
[0079]
Next, as shown in FIG. 30, the bit line BL is formed on the silicon oxide film 62. ₁ , BL ₂ And wirings 70A and 70B of the peripheral circuit are formed. Bit line BL ₁ , BL ₂ The wirings 70A and 70B are formed by depositing a W film on the silicon oxide film 62 by using the plasma CVD method, and then depositing a silicon nitride film 71 on the W film by using the CVD method. These films are patterned at the same time by patterning with etching using as a mask.
[0080]
Bit line BL ₁ Is electrically connected to one of the source region and the drain region (the n-type semiconductor region 8) of the memory cell selecting MISFET through the connection hole 63. Also, the bit line BL ₂ Is one of the source region and the drain region (n) of the n-channel MISFET Qn of the peripheral circuit through the connection hole 65. ⁺ (Type semiconductor region 60).
[0081]
One end of the wiring 70A of the peripheral circuit is connected to the other (n) of the source region and the drain region of the n-channel MISFET through the connection hole 66. ⁺ Semiconductor region 60), and the other end is connected to one of the source region and the drain region (p ⁺ (Type semiconductor region 61). The wiring 70B is connected to the other of the source region and the drain region of the p-channel MISFET (p ⁺ (Type semiconductor region 61).
[0082]
Next, as shown in FIG. ₁ , BL ₂ And a side wall spacer 72 is formed on each side wall of the wirings 70A and 70B. The side wall spacer 72 is formed by depositing a silicon nitride film on the silicon oxide film 62 by using a plasma CVD method, and then processing the silicon nitride film by anisotropic etching.
[0083]
Next, as shown in FIG. ₁ , BL ₂ A silicon oxide film 73 is deposited on each of the wirings 70A and 70B using a plasma CVD method, and the silicon oxide film 73 is polished by a chemical mechanical polishing (CMP) method to planarize the surface. Thereafter, the silicon oxide film 73 is etched using a photoresist as a mask, so that the upper portion of the connection hole 64 formed on one upper portion of the n-type semiconductor region 8 (source region, drain region) of the memory cell selecting MISFET. A connection hole 74 is formed in the substrate. At this time, the bit line BL ₁ Since the silicon nitride film 71 formed on the upper surface and the silicon nitride sidewall spacers 72 formed on the side walls are only slightly etched, the connection holes 74 are formed by self-alignment (self-alignment).
[0084]
Bit line BL ₁ , BL ₂ As the insulating film deposited on the wirings 70A and 70B, in addition to the silicon oxide film 73, for example, the above-described ozone-BPSG film, ozone-TEOS film, or spin-on-glass (Spin On Glass; SOG) film Can be used. When an ozone-BPSG film or an ozone-TEOS film is used, the surface is flattened by a chemical mechanical polishing (CMP) method as in the case of the silicon oxide film 73.
[0085]
Next, as shown in FIG. 33, after a W plug 75 is embedded in the connection hole 74, a lower electrode (storage electrode) 76 of the information storage capacitor is formed above the connection hole 74. The W plug 75 is formed by depositing a W film on the silicon oxide film 73 using a CVD method and then etching back the W film. The lower electrode 76 is formed by depositing a W film on the silicon oxide film 73 using a CVD method and then patterning the W film by etching using a photoresist as a mask.
[0086]
Next, as shown in FIG. 34, a tantalum oxide film 77 is deposited on the lower electrode 22. The tantalum oxide film 77 is deposited by using a CVD method having good step coverage. The tantalum oxide film 77 is made of, for example, Ta (OC ₂ H ₅ ) Is deposited as a reaction gas at a temperature of about 400 ° C., and then annealed at a temperature of about 700 to 1000 ° C. using an electric furnace or a lamp annealing apparatus.
[0087]
Next, a conductive film for an upper electrode is deposited on the tantalum oxide film 77 using the CVD apparatus used in the first embodiment. The titanium-containing source gas used at this time is TiCl ₄ , TDAT or TDEAT, nitrogen-containing reducing gas is NH ₃ , MMH or their mixed gas, inert gas is He, Ar, N ₂ Or a mixed gas thereof.
[0088]
In this embodiment, a gas is introduced into the chamber of the CVD apparatus according to the steps shown in FIG. That is, after evacuating the chamber to a predetermined degree of vacuum, introducing an inert gas while raising the temperature of the substrate, and introducing a titanium-containing source gas when the substrate temperature becomes substantially constant to thermally decompose the same. As a result, as shown in FIG. 36, a thin protective film 78 having a thickness of about 30 to 50 ° and containing Ti as a main component is formed on the surface of the tantalum oxide film 77. Subsequently, a TiN film 79 is deposited on the surface of the protective film 78 as shown in FIG. 37 by introducing a nitrogen-containing reducing gas into the chamber and reacting it with a titanium-containing source gas. FIG. 38 shows a typical reaction equation between the titanium-containing source gas and the nitrogen-containing reducing gas at this time.
[0089]
The titanium-containing source gas may be introduced almost simultaneously with the inert gas when the temperature of the substrate is raised, as shown in FIG. 39, or may be introduced immediately before the introduction of the nitrogen-containing reducing gas, as shown in FIG. In any case, a titanium-containing source gas is introduced prior to the nitrogen-containing reducing gas. By doing so, a protective film 78 is formed on the surface of the tantalum oxide film 77 by the thermal decomposition of the titanium-containing source gas, and this prevents the contact between the nitrogen-containing reducing gas introduced later and the tantalum oxide film 77. Deterioration of the tantalum oxide film 77 is prevented.
[0090]
When depositing the protective film 78 and the TiN film 79 on the tantalum oxide film 77, the film is formed under such temperature conditions that the barrier property of the protective film 78 against permeation of the nitrogen-containing reducing gas becomes sufficiently high. There is a need to do. Specifically, film formation is performed at a temperature lower than the crystallization temperature, and an amorphous or polycrystalline protective film 78 having less gas-permeable paths in the film than the crystal is formed.
[0091]
The optimum values of the film forming temperatures of the protective film 78 and the TiN film 79 differ depending on the type of the titanium-containing source gas and the nitrogen-containing reducing gas used and the combination thereof. ₃ Is 550 ° C. or lower, more preferably 500 ° C. or lower, and MMH is 500 ° C. or lower, more preferably 450 ° C. or lower.
[0092]
FIGS. 41 and 42 are graphs showing the results of experiments in which the relationship between the film forming temperature of the protective film 78 and the TiN film 79 and the electric field strength of the tantalum oxide film 77 was examined. FIG. 41 is a diagram showing the case where a positive (+) voltage is applied to the upper electrode composed of the TiN film 79. ^-8 A / cm ² FIG. 42 shows the electric field strength at the time of applying a negative (−) voltage to the upper electrode. ^-8 A / cm ² 5 shows the electric field intensity at. The white circle (○) in the figure indicates that the film was formed in the steps shown in FIG. 35 (inert gas = He + Ar, titanium-containing source gas = TiCl ₄ , Nitrogen-containing reducing gas = NH ₃ ), Black circles (●) indicate that the film was formed in the steps shown in FIG. 39 (inert gas = He + Ar, titanium-containing source gas = TiCl ₄ , Nitrogen-containing reducing gas = NH ₃ ), White square marks (□) indicate that the film was formed in the steps shown in FIG. 40 (inert gas = He + Ar, titanium-containing source gas = TiCl). ₄ , Nitrogen-containing reducing gas = NH ₃ ), Black squares (■) indicate that the film was formed in the steps shown in FIG. 40 (inert gas = He + Ar, titanium-containing source gas = TiCl ₄ , Nitrogen-containing reducing gas = NH ₃ + MMH).
[0093]
From the above experimental results, it can be seen that, generally, the lower the deposition temperature of the protective film 78 and the TiN film 79, the higher the electric field strength of the tantalum oxide film 77 and the better the leakage withstand voltage of the capacitance insulating film. In the above film forming process, a titanium-containing source gas (TiCl ₄ The chlorine generated by the decomposition of ()) is taken into the film. As shown in FIG. 43, the chlorine concentration increases as the film formation temperature decreases. When a high concentration of chlorine is taken into the conductive film constituting the upper electrode, when a wiring containing Al (aluminum) is formed on the upper layer of the upper electrode, the wiring is formed through the connection hole connecting the upper electrode and the wiring. Since chlorine is taken in, the potential for causing wiring corrosion is increased. Therefore, the lower limit of the film forming temperature of the protective film 78 and the TiN film 79 needs to be set in consideration of this point.
[0094]
Next, as shown in FIG. 44, after a high selectivity film 80 is deposited on the TiN film 79, the high selectivity film 80, the TiN film 79, the protective film 78 and the oxide film are formed by dry etching using a photoresist as a mask. The tantalum film 77 is patterned to form an upper electrode (plate electrode) 90 and a capacitor insulating film (tantalum oxide film 77), thereby completing the information storage capacitor Cs. At the same time, wirings 81 and 82 of the peripheral circuit are formed. The high selectivity film 80 is a film that serves as an etching stopper when a silicon oxide film or a silicon nitride film is etched in a later step. If the material has a high etching selectivity to the silicon oxide film or the silicon nitride film, the insulating film is used. Or a conductive film.
[0095]
Next, as shown in FIG. 45, a silicon oxide film 83 is deposited on the information storage capacitor Cs and the wirings 81 and 82, and then the silicon oxide film 83 is dry-etched using a photoresist as a mask. A connection hole 84 is formed above the upper electrode 90 of the information storage capacitor Cs, and a connection hole 85 is formed above the wiring 81. At the same time, the silicon oxide film 83, the silicon oxide film 73, and the silicon nitride film 71 in the region where the wiring 82 is formed are etched to form a connection hole 86 above the wiring 70B of the peripheral circuit. At this time, since the upper part of the upper electrode 90 and the upper parts of the wirings 81 and 82 are covered with the high selectivity film 80, the upper electrode 90 and the wirings 81 and 82 are not etched and the film thickness is not reduced.
[0096]
Next, as shown in FIG. 46, by etching the high selectivity film 80 covering the upper electrode 90 and the wirings 81 and 82, a part of the wiring 81 is exposed inside the connection hole 85, One end of the wiring 82 is exposed inside 86.
[0097]
Next, as shown in FIG. 47, after plugs 87 made of TiN (or W) are embedded in the connection holes 84, 85 and 86, a wiring made of a laminated film of Al and TiN is formed on the silicon oxide film 83. 88A, 88B and 88C are formed. Thus, the wiring 81 of the peripheral circuit is connected to the lower wiring 70B via the wiring 88C and the wiring 82.
[0098]
As described above, according to the present embodiment, when the TiN film 79 is deposited by the low-temperature CVD method on the tantalum oxide film 77 constituting the capacitive insulating film of the information storage capacitive element Cs to form the upper electrode 90 Since the protective film 78 that does not allow the nitrogen-containing reducing gas to pass through is formed on the surface of the tantalum oxide film 77 in advance, the withstand voltage deterioration (increase in leak current) of the tantalum oxide film 77 can be reliably prevented. A DRAM with improved refresh characteristics can be realized.
[0099]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0100]
In the above embodiment, the case where the upper electrode of the capacitor is made of TiN has been described. However, the present invention can be applied to a case where the upper electrode is made of a material other than TiN, such as TaN. For example, when a TaN film is deposited on a tantalum oxide film by a CVD method, Ta (OC ₂ H ₅ ) To NH ₃ And a method of reducing with a nitrogen-containing reducing gas such as MMH. Therefore, by forming a protective film on the surface of the tantalum oxide film prior to the formation of the TaN film, it is possible to prevent the withstand voltage of the tantalum oxide film from deteriorating due to contact with the nitrogen-containing reducing gas.
[0101]
Further, according to the present invention, a capacitive insulating film of a capacitive element is formed of a high dielectric film other than tantalum oxide or a ferroelectric film such as ₃ , SrTiO ₃ , BaTiO ₃ , PZT, B (boron) or F (fluorine) -doped ZnO or the like, or a nonvolatile memory.
[0102]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0103]
According to the present invention, when a TiN film is deposited on a tantalum oxide film constituting a capacitive insulating film of a capacitive element to form an upper electrode, a protective film is previously formed on the surface of the tantalum oxide film by a low-temperature CVD method. By doing so, contact between the nitrogen-containing reducing gas and the tantalum oxide film is prevented, so that a capacitor with improved withstand voltage characteristics can be obtained.
[0104]
According to the present invention, the amount of charge stored in the capacitor can be increased by forming the capacitor insulating film of the capacitor from a high dielectric constant film.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to an embodiment of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;
FIG. 18 is a main part configuration diagram of a CVD apparatus used for manufacturing a DRAM according to an embodiment of the present invention.
FIG. 19 is a block diagram of a DRAM according to another embodiment of the present invention.
FIG. 20 is a circuit diagram of a memory array and a sense amplifier of a DRAM according to another embodiment of the present invention.
FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention;
FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 23 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention.
FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;
FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 27 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method of manufacturing a DRAM according to another embodiment of the present invention.
FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;
FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to another embodiment of the present invention;
FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 35 is a graph showing a step of forming a TiN film for an upper electrode.
FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 37 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 38 is a diagram showing a reaction formula between a titanium-containing source gas and a nitrogen-containing reducing gas.
FIG. 39 is a graph showing a step of forming a TiN film for an upper electrode.
FIG. 40 is a graph showing a step of forming a TiN film for an upper electrode.
FIG. 41 is a graph showing the relationship between the deposition temperature of the protective film and the TiN film and the electric field strength of the tantalum oxide film.
FIG. 42 is a graph showing the relationship between the deposition temperature of the protective film and the TiN film and the electric field strength of the tantalum oxide film.
FIG. 43 is a graph showing the relationship between the film forming temperature of the protective film and the TiN film and the concentration of chlorine taken in the film.
FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 45 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
FIG. 47 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to another embodiment of the present invention;
[Explanation of symbols]
1 semiconductor substrate
2 p-type wells
3 Field oxide film
4 Gate oxide film
5 p-type channel stopper layer
6 Gate electrode
6A-6C Gate electrode
7 Silicon oxide film
8 n-type semiconductor region (source region, drain region)
9 Side wall spacer
10 Silicon oxide film
11 Connection hole
12 Polycrystalline silicon film
13 BPSG film
14 Connection hole
15 Silicon oxide film
16 Silicon nitride film
17 Silicon oxide film
18 Connection hole
19 Polycrystalline silicon film
20 Silicon oxide film
21 Polycrystalline silicon film
22 Lower electrode (storage electrode)
23 Silicon nitride film
24 Tantalum oxide film
25 Capacitive insulating film
26 Amorphous Ti film
27 TiN film
28 Upper electrode
40 CVD equipment
41 chamber
42 valve
43 valve
44 vacuum pump
45 vacuum pump
53 silicon oxide film
54 silicon nitride film
55 n-type well
56 n-type channel stopper layer
57 silicon nitride film
58 n ⁻ Semiconductor region
59p ⁻ Semiconductor region
60 n ⁺ Semiconductor region
61 p ⁺ Semiconductor region
62 silicon oxide film
63-68 Connection hole
69 plug
70A wiring
70B wiring
71 Silicon nitride film
72 Sidewall spacer
73 silicon oxide film
74 Connection hole
75 plug
76 Lower electrode (storage electrode)
77 Tantalum oxide film
78 Protective film
79 TiN film
80 High Selectivity Ratio Membrane
81 Wiring
82 Wiring
83 silicon oxide film
84-86 Connection hole
87 plug
88A-88C Wiring
90 Upper electrode (plate electrode)
BL bit line
BL ₁ Bit line
BL ₂ Bit line
Cs information storage capacitor
CASB column address strobe signal
CD complementary common data line
IO data input / output circuit
MARY memory array
RASB row address strobe signal
SA sense amplifier
SP common source line
TG timing generation circuit
VP plate voltage
WEB write enable signal
WL word line
XB X address buffer
XD X address decoder
YB Y address buffer
YDY address decoder

Claims (11)

A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a first conductive film constituting a lower electrode of a capacitor on a main surface of a semiconductor substrate;
(B) forming a capacitance insulating film composed of a single film or a plurality of films including a high dielectric film on the first conductive film;
(C) forming a protective film on the capacitive insulating film by a low-temperature CVD method using a titanium-containing source gas and an inert gas not containing a reducing gas ;
(D) forming a second conductive film composed of a single or a plurality of films including a titanium nitride film constituting an upper electrode of the capacitive element with a reducing gas containing nitrogen and a titanium source gas on the protective film; Process. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said capacitive insulating film includes a tantalum oxide film. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said protective film includes an amorphous titanium film or a polycrystalline titanium film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said capacitance element is a capacitance element arranged above a memory cell selection MISFET constituting a memory cell of a DRAM. A method for manufacturing a circuit device. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, further comprising a step of patterning at least a part of a lower electrode of said capacitance element into a fin shape or a cylindrical shape. . A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:
(A) forming a MISFET on a main surface of a semiconductor substrate;
(B) forming a first conductive film composed of a single film or a plurality of films on the MISFET;
(C) patterning at least a part of the first conductive film into a fin shape or a cylindrical shape to form a lower electrode of the capacitor;
(D) forming a capacitive insulating film composed of a single or a plurality of films including a high dielectric film on the lower electrode;
(E) forming a protective film on the capacitive insulating film by a low-temperature CVD method under an inert gas condition containing a titanium-containing source gas and no nitrogen-containing reducing gas;
(F) forming a second conductive film composed of a single film or a plurality of films including a titanium nitride film on the protective film by a low-temperature CVD method under a condition including a titanium-containing source gas and a nitrogen-containing reducing gas; Process,
(G) forming an upper electrode of the capacitive element by patterning the second conductive film, the protective film, and the capacitive insulating film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the titanium-containing source gas is introduced into a chamber of a CVD apparatus to form the protective film, and then the nitrogen-containing reducing gas is introduced. A method of manufacturing a semiconductor integrated circuit device, wherein the second conductive film is continuously formed on the protective film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said capacitance insulating film includes a tantalum oxide film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said protective film includes an amorphous titanium film or a polycrystalline titanium film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the titanium-containing source gas contains titanium tetrachloride, tetraxydimethylaminotitanium, tetraxydiethylaminotitanium, or a mixed gas thereof. A method for manufacturing an integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the nitrogen-containing reducing gas includes ammonia, monomethylhydrazine, or a mixed gas thereof.

Images