JPH0982915A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device wherein a leak current is small, permittivity is high, and a very thin film of high permittivity is used as a capacitor insulating film. SOLUTION: A barium strontium titanate film 12 as a dielectric film is formed on an Ru film 11 as a first conductor electrode. After heat treatment is performed in an oxygen atmosphere at a temperature higher than or equal to the crystallization temperature of the barium strontium titanate film 12, a titanium nitride film 14 as a second conductor electrode is formed on the barium strontium titanate film 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynami
The present invention relates to a method for manufacturing a semiconductor device having a capacitor structure such as c Random Access read write memory).

[0002]

2. Description of the Related Art DRAM (Dynamic Random Access read)
write Memory), FRAM (Ferroelectric Random A)
In a semiconductor memory device such as a ccess read write memory) that stores data by accumulating charges in a capacitor electrode, with the increase in storage capacity and high integration of elements,
Memory cells are becoming smaller and smaller. However, when the area of the capacitor is reduced with the miniaturization of the memory cell and the capacitance of the capacitor is reduced, the noise may cause a malfunction in reading the data, or the leak of the accumulated charge may change the data. There is a problem that it will end up.

Therefore, a stack type capacitor structure in which a capacitor is formed on a gate electrode has been put into practical use.
However, due to further miniaturization of the cell due to the increase in storage capacity, it is becoming difficult to secure a sufficient capacitor capacity by simply forming the capacitor on the gate electrode. Therefore, a method has been proposed in which the area of the capacitor is increased by further making the stacked capacitor structure three-dimensional. However, since the manufacturing method of the three-dimensional capacitor structure is complicated, it is difficult to control,
It is very difficult to manufacture with good reproducibility.

As a method for solving these problems, attempts have been made to use an insulating film having a high dielectric constant as the capacitor insulating film. For example, BaXSr _1-X TiO ₃ (BST: barium strontium titanate), PbZrXTi _1-X O ₃
A crystal having a perovskite crystal structure such as (PZT: lead titanium zirconate) has a dielectric constant of about 400, and 3.9 of SiO ₂ which has been used most as a conventional insulating film.
It has a much higher dielectric constant than

A conventional D using such a high dielectric film
A method for manufacturing the RAM is shown in FIG. For example, the element isolation region 2 is formed on the p-type single crystal silicon substrate 1. Subsequently, a thermal oxide film and a polycrystalline silicon film are formed on the single crystal silicon substrate 1, and a gate electrode 3 is formed by an etching technique such as a usual photolithography method and RIE (reactive ion etching) method. Further, the n-type diffusion layer regions 4 and 5 are formed by the ion implantation method.

After that, an oxide film is deposited by using, for example, a CVD (chemical vapor deposition) method to form an interlayer insulating film 6. Next, a contact hole penetrating the n-type diffusion layer region 4 is formed in the interlayer insulating film 6. Subsequently, a polycrystalline silicon film 7 is formed in this contact hole, and phosphorus is added to this polycrystalline silicon film 7. Further, a tungsten silicide film is deposited, and the ordinary photolithography method and RIE are used.
The bit line 8 is formed by using an etching technique such as the etching method (FIG. 7A).

Next, an interlayer insulating film 9 is formed by depositing an oxide film using, for example, the CVD method. Subsequently, the interlayer insulating films 9 and 6 are etched by using an ordinary photolithography method and an etching technique such as an RIE method, so that the n-type diffusion layer 5 is formed.
A contact hole is formed so as to penetrate through. Next, CVD
Using the method, a polycrystalline silicon film 10 containing arsenic is formed in the contact hole. Then, a platinum film is deposited by the sputtering method. Furthermore, the capacitor lower electrode 51 is formed by using the ordinary photolithography method and etching technique.
Are formed ((b) of FIG. 7).

Next, for example, Sr (THD) ₂ , Ba (THD) ₂ , T
Amorphous BST film 52 of 15 nm is formed at a temperature of 430 ° C. and a pressure of 3 kPa by a CVD method using i (THD) ₂ and N ₂ O as raw material gases.
It is formed ((c) of FIG. 7). Where THD is 2,2,6,6
Abbreviation for Tetramethyl 1,3,5 heptanedionate.

Further, a platinum film 53 is deposited by a sputtering method to form an upper electrode of the capacitor, and a DRAM memory cell is completed (FIG. 7 (d)). After that, a wiring, a passivation film, and the like are formed according to a normal LSI manufacturing process, and the DRAM is completed.

As described above, in the conventional DRAM manufacturing method, by using the high dielectric film as the capacitor insulating film, a sufficient capacitance can be secured with a small capacitor area. For example, when a charge density of ²⁰⁰ fF / μm ² or more is secured, a 1 Giga DRAM adopting a memory cell having a planar stack type capacitor structure.
Can be realized. In this way, by significantly simplifying the manufacturing method as compared with the memory cell of the stack type capacitor structure having a complicated three-dimensional structure, it is possible to realize a DRAM manufacturing method with good reproducibility and low manufacturing cost. it can.

However, the high dielectric film manufactured by the conventional method has a problem that the dielectric constant decreases as the film thickness decreases. FIG. 3B shows the film thickness dependence of the dielectric constant of the BST film manufactured by the conventional method. As shown in this figure, when the thickness of the BST film becomes thinner than about 30 nm, the dielectric constant sharply decreases. Therefore, even if the thickness of the BST film is reduced to obtain a high charge density, the permittivity is lowered, and a sufficient charge density cannot be realized. For example, a 1 G D using a memory cell having a planar stack type capacitor structure as described above.
It becomes impossible to achieve ²⁰⁰ fF / μm ² for realizing a RAM.

The cause of such a decrease in the dielectric constant is explained as follows. In the first place, the high dielectric constant of an oxide high dielectric having a perovskite crystal structure such as BST is
The element located at the center of the crystal lattice is developed by being displaced by the applied electric field, but at a high electric field, the electric field dependency of such displacement is saturated. In a conventional capacitor structure using a high dielectric film, it is necessary to use an electrode material having a large work function difference with the high dielectric film in order to suppress the leak current. A high electric field is generated at the interface between the high dielectric film and the electrode due to the fact that it has the property of a semiconductor, not an object. Then, due to this high electric field, the displacement of the element is saturated and the dielectric constant is lowered as described above.

The cause will be described in more detail below. First, since an oxide high dielectric material having a perovskite crystal structure such as BST generally has a small band gap, a leak current easily flows due to hopping conduction or the like. Therefore, in order to suppress the leak current to the extent that it can be applied to, for example, a DRAM, an electrode material having a large work function difference with the high dielectric film is used, and the interface between the electrode and the high dielectric film is used. An energy barrier needs to be formed.

For example, in the above conventional manufacturing method,
Platinum films are used as the upper and lower electrodes 51 and 53 of the capacitor, but the work function difference between platinum and BST is 1.7 eV.
It is. Besides, ruthenium oxide (RuO ₂ ) having a work function difference from BST of 0.9 ev can also be used.

Furthermore, when a high dielectric constant such as BST is used for the capacitor insulating film, it contacts with an electrode material having a completely different crystal structure such as platinum, so that oxygen vacancies are present in the crystal due to discontinuity at the interface. Prone to Since such oxygen vacancies act as a divalent donor, the high dielectric film particularly near the electrode interface behaves not as an insulating film but as a semiconductor containing a high concentration of donors.

Therefore, when a high energy barrier is formed at the interface between the high dielectric film and the electrode as described above, the high dielectric film having the property of a semiconductor near the interface is depleted, and the high dielectric film near the interface is depleted. A strong electric field is generated. In FIG. 2B, platinum is used as the lower electrode material and BS is used as the capacitor insulating film.
The energy band structure when platinum is used for the T film as the upper electrode material is shown. Further, FIG. 2C shows the energy when ruthenium oxide is used as the lower electrode material.
It is a band structure. It can be seen that the band of the high-dielectric film is curved at the electrode interface both above and below, and the electric field is strongly concentrated in the region near the interface.

On the other hand, in a high dielectric having a perovskite crystal structure, Ti, which is generally located at the center of the Ti—O octahedron structure as shown in FIG. 8, is displaced in the direction of the electric field indicated by the arrow in the figure. , Develops a high dielectric constant.

However, when a very high voltage is applied, the lattice displacement of Ti is saturated and it becomes impossible to develop a high dielectric constant. Such electric field dependence of the permittivity is a general property of high dielectric materials having a perovskite crystal structure.

In this way, the high electric field region in the vicinity of the interface between the high dielectric film and the electrode behaves as a low dielectric constant layer, and particularly when the film thickness of the high dielectric film is reduced, this low electric field is reduced. Since the ratio of the dielectric constant layer increases, the dielectric constant sharply decreases as shown in FIG.

[0020]

As described above, in the conventional method for manufacturing a semiconductor device, the permittivity decreases as the high-dielectric film becomes thinner, so that a sufficiently high charge density can be secured. There was a problem that it was difficult. An object of the present invention is to provide a method of manufacturing a semiconductor device using an extremely thin high dielectric film having a small leak current and a high dielectric constant as a capacitor insulating film.

[0021]

In order to solve the above-mentioned problems and to achieve the object, a method of manufacturing a semiconductor device according to the present invention has a dielectric on at least a surface of a first conductor electrode containing ruthenium as a main component. The method comprises the steps of forming a film, performing heat treatment in an oxidizing atmosphere at a temperature equal to or higher than the crystallization temperature of the dielectric film, and forming a second conductor electrode on the dielectric film. It is characterized by

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a dielectric film on the first conductor electrode having at least a surface containing ruthenium as a main component, and a second step on the dielectric film. The method is characterized by comprising a step of forming a conductor electrode and a step of performing heat treatment at a temperature equal to or higher than the crystallization temperature of the dielectric film.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming a dielectric film on the first conductor electrode and at least the interface between the dielectric film and the dielectric film are mainly made of ruthenium. The method is characterized by including a step of forming a second conductor electrode as a component and a step of performing heat treatment at a temperature equal to or higher than the crystallization temperature of the dielectric film.

As described above, according to the present invention, as the lower electrode, at least the surface is composed of the first ruthenium-based first component.
Is formed on the first conductive film, and then heat treatment is performed in an oxidizing atmosphere to oxidize the surface of the lower electrode through the dielectric film. Since the ruthenium film is formed, the state of the interface between the ruthenium film and the dielectric film can be improved.

According to the second manufacturing method of the present invention,
A first conductor film having at least a surface containing ruthenium as a main component is formed as a lower electrode, a dielectric film is formed on the first conductor film, and a second conductor film is formed as an upper electrode. Then, heat treatment is performed to improve the state of the interface between the ruthenium film and the dielectric film.

Furthermore, according to the third manufacturing method of the present invention, the first conductor film is formed as the lower electrode, and the first conductor film is formed.
Forming a dielectric film on the conductive film and further forming a second conductive film whose upper surface is at least an interface with the dielectric film as an upper electrode on the dielectric film, and then heat treatment is performed. Thereby, the state of the interface between the ruthenium film and the dielectric film can be improved.

Due to such a favorable interface state, generation of oxygen vacancies in the dielectric film can be suppressed,
Even when an electrode material that forms a high energy barrier is used, formation of a depletion layer in the dielectric film near the interface can be prevented. Therefore, it is possible to suppress the concentration of the electric field in the vicinity of the interface in the dielectric film and avoid the saturation of the dielectric constant due to the high electric field. As described above, it is possible to manufacture a semiconductor device which uses an extremely thin high-dielectric film having a small leak current and a high dielectric constant as a capacitor insulating film.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention applied to a DRAM will be described below with reference to the drawings.
1A to 1D are process sectional views showing a first embodiment according to the present invention.

As in the conventional case, the element isolation region 2 is formed on the p-type single crystal silicon (Si) substrate 1, for example. Subsequently, a thermal oxide film and a polycrystalline silicon film are formed on the single crystal silicon substrate 1, and a gate electrode 3 is formed by a usual photolithography method and an etching technique such as RIE (reactive ion etching). To do. Further, the n-type diffusion layer regions 4 and 5 are formed by, for example, the ion implantation method.

Thereafter, an oxide film is deposited by using, for example, a CVD (chemical vapor deposition) method to form an interlayer insulating film 6. Next, a contact hole penetrating the n-type diffusion layer region 4 is formed in the interlayer insulating film 6 by a normal photolithography method and an etching technique such as an RIE method. continue,
A polycrystalline silicon film 7 is formed in this contact hole, and impurities such as phosphorus are added to this polycrystalline silicon film 7. Further, a tungsten silicide film is deposited, and the bit line 8 is formed by using an ordinary photolithography method and an etching technique such as the RIE method.

Next, an interlayer insulating film 9 is formed by depositing an oxide film by using, for example, the CVD method. Subsequently, the interlayer insulating films 9 and 6 are etched by using a normal photolithography method and an etching technique such as an RIE method to form a contact hole penetrating the n-type diffusion layer 5. Next, a polycrystalline silicon film 10 containing, for example, arsenic is formed in the contact hole and on the interlayer insulating film 9 by using, for example, the CVD method, and the polycrystalline silicon film 10 is etched by, for example, a method such as etch back. Is embedded in the contact hole ((a) of FIG. 1). Up to this point, it is the same as the conventional method.

After this, unlike the conventional method, for example, a ruthenium film is deposited by, for example, the sputtering method. Further, the lower electrode 11 of the capacitor is formed by using the usual photolithography method and etching technique ((b) of FIG. 1).

Next, as in the conventional case, for example, Sr (THD) ₂ ,
CV using Ba (THD) ₂ , Ti (THD) ₂ and N ₂ O as source gases
An amorphous BST film 12 having a thickness of 15 nm is formed by the D method at a temperature of 430 ° C. and a pressure of 3 kPa (FIG. 1C). Under the above film forming conditions, it is possible to form a BST film having excellent coverage in the step portion.

Next, unlike the conventional method, for example, the temperature is 700 ° C.
RTA (Rapid Thermal Anneal) for 1 minute in the oxygen atmosphere of
al) Perform processing. By this heat treatment, the ruthenium film 11
A ruthenium oxide film 13 of about 10 nm is formed on the surface of the BST film, a good interface is formed between the ruthenium film 11 and the BST film 12, and the BST film 12 is crystallized ((d) of FIG. 1).

Further, the titanium nitride film 1 is formed by the sputtering method.
4 is deposited to form the upper electrode of the capacitor,
The memory cell is completed ((e) in FIG. 1). After this,
According to a normal LSI manufacturing process, wiring, passivation film, etc. are formed to complete the DRAM.

As described above, in the present embodiment, the ruthenium film 11 forming the lower electrode of the capacitor is replaced with the BST film 12.
Oxidation via oxygen suppresses the generation of oxygen vacancies in the BST film 12, and a very good interface can be formed. Conventionally, since the BST film 12 is formed on the lower electrode 51 having a completely different crystal structure such as platinum and no heat treatment is performed, the lower electrode 51 and the BST film 1 are not formed.
Due to the discontinuity with No. 2, oxygen vacancies were generated in the BST film 12. However, according to the present embodiment,
By oxidizing the ruthenium film 11 which is the lower electrode and forming the ruthenium oxide film 13, such discontinuity can be alleviated and the generation of oxygen vacancies can be suppressed.

Further, when the high dielectric film is the BST film as in the present embodiment, the effect is more significant. In general, BST, which is a solid solution formed with an arbitrary composition ratio of BaTiO ₃ and SrTiO ₃ , is at the same time BaRuO ₃ and S which are conductors.
rRuO ₃ also forms a solid solution with an arbitrary composition ratio (SLCuff
ini, VAMacagno, RECarbonio, A.Melo, E.Trollund and
JLGautier: Journal of Solid State Chemistry 105,1
61-170 (1993)). Therefore, ruthenium film 11 is
Oxidation through the film 12 results in a transition layer Ba between the BST film 12 and the ruthenium oxide (RuO ₂ ) film 13.
_x Sr _y Ru _z Ti _w O ₃ (x + y = 1, z + w = 1) can be formed, and the discontinuity can be almost completely relaxed.

When the BST film 12 at the time of deposition is amorphous, such a transition layer is more easily formed in the crystallization process by heat treatment. Therefore, the BST film 1
For 2, it is desirable to deposit an amorphous BST film.

Further, in order to form such a transition layer, it is necessary that the lower electrode contains unoxidized ruthenium, and the ruthenium used as the lower electrode has an oxygen content of, for example, less than 2/3. Need to be

FIG. 2A shows a band structure when a capacitor is formed by the method according to this embodiment. In FIG. 2, a lower electrode is formed by a conventional method, that is, Pt ((b) of FIG. 2) or RuO ₂ ((c) of FIG. 2), and then a BST film is formed.
3 shows a band structure of a capacitor manufactured by forming a. In particular, FIGS. 2A and 2C show a similar capacitor structure in which RuO ₂ is used as the lower electrode, but in FIG. 2C, the RuO ₂ film is directly deposited. In the above method, the BST film 12 is formed on the Ru film 11,
The RuO ₂ film 13 is formed by oxidizing the Ru film 11 via the BST film 12. By this heat treatment, according to the method of the present invention, as shown by A in the figure, BS
The electric field at the interface between the T film 12 and the lower electrode (RuO ₂ film) 13 is relaxed.

Further, FIG. 3A shows the film thickness dependence of the dielectric constant of the high dielectric film when the capacitor is formed by the method according to the present embodiment. FIG. 3B shows the case where the conventional platinum is used. From this figure, it can be seen that a high dielectric constant can be obtained even in a thin film as compared with the conventional case.

As a second embodiment of the present invention, a case where ruthenium oxide is used for the lower electrode of the capacitor will be described. 4A to 4D are process cross-sectional views showing a method of manufacturing a DRAM according to the second embodiment of the present invention.

The steps up to the step of burying the polycrystalline silicon film 10 in the contact hole penetrating the n-type diffusion layer 5 are the same as those in the first embodiment of the present invention. Figure 4 (a)
Shows a state similar to that of FIG.

Then, unlike the first embodiment, the ruthenium oxide film 22 is deposited by, eg, sputtering. Further, the lower electrode of the capacitor is formed by using the usual photolithography method and etching technique (see FIG. 4).
(B)).

Next, for example, heat treatment is performed in a nitrous oxide atmosphere at a temperature of 430 ° C. and a pressure of 3 kPa for 15 minutes to reduce the surface of the ruthenium oxide film 22 to form a RuO _x (x <2) film 23. ((C) of FIG. 4).

After that, as in the first embodiment of the present invention, the amorphous BST film 12 is formed by the CVD method, for example, 15 times.
nm (FIG. 4 (d)). Furthermore, for example, a temperature of 7
RTA treatment is performed for 1 minute in an oxygen atmosphere at 00 ° C. By this heat treatment, the RuO _x (x <2) film 23 is oxidized to form the ruthenium oxide (RuO ₂ ) film 13, which forms a good interface between the lower electrode 22 and the BST film 12, and The film crystallizes ((e) of FIG. 4).

Further, a titanium nitride film 14 is deposited by, for example, a sputtering method to form an upper electrode of the capacitor,
A DRAM memory cell is completed (FIG. 4 (f)).
After that, according to the normal LSI manufacturing process, wiring,
A DRAM is completed by forming a passivation film and the like.

As described above, in the present embodiment, the ruthenium oxide film 22 is deposited as the first conductive film forming the lower electrode, and the BST film 12 is formed after reducing the surface thereof. Therefore, the subsequent RTA treatment is performed. RuO _x reduced by
The (x <2) film 23 is oxidized again through the BST film 12 to form a ruthenium oxide (RuO ₂ ) film 13,
A good interface between the RuO _x (x <2) film 23 and the BST film 12 can be formed. As described above, in the present invention, it is important to oxidize the electrode via the dielectric film such as the BST film 12. When the BST film 12 is simply formed on the ruthenium oxide film, the completed structure is apparently the same,
Since a good interface cannot be formed between the electrode and the dielectric film, the effect of the present invention cannot be obtained.

In the present embodiment, the RuO _x (x <2) film 23 formed by reduction is completely oxidized.
Only the surface of the O _x (x <2) film 23 is oxidized to form RuO _x.
It is also possible to leave the (x <2) film 23. Even in this case, a good interface can be formed by forming the ruthenium oxide film 13 between the lower electrodes 22 and 23 and the BST film 12.

As a third embodiment of the present invention, the RTA is formed after the upper electrode of the capacitor is further formed of ruthenium on the BST film formed on the ruthenium film.
A method of forming a capacitor having a BST film and upper and lower electrodes having favorable interfaces after the treatment is described. 5A to 5D are process sectional views showing a method of manufacturing a DRAM according to the third embodiment of the present invention.

Similar to the first embodiment according to the present invention,
A polycrystalline silicon film 10 is embedded in a contact hole penetrating the n-type diffusion layer 5. (A) of FIG. 5 is (a) of FIG.
Shows the same state as.

Thereafter, a ruthenium film 11 having a film thickness of 100 nm, for example, is deposited by, eg, sputtering method. Further, the lower electrode of the capacitor is formed by using the usual photolithography method and etching technique ((b) of FIG. 5).

Next, for example, Sr (THD) ₂ , Ba (THD) ₂ , T
Amorphous BST film 12 having a thickness of 15 nm is formed at a temperature of 430 ° C. and a pressure of 3 kPa by the CVD method using i (THD) ₂ and N ₂ O as raw material gases.
It is formed ((c) of FIG. 5). Under the above film forming conditions, it is possible to form a BST film having excellent coverage in the step portion. Up to this point, the process is the same as in the first embodiment of the present invention.

Further, unlike the first embodiment, a ruthenium film 34 of, eg, a 5 nm-thickness is deposited by, eg, sputtering method. In this way, a layered structure sandwiching the ruthenium films 11 and 34 above and below the amorphous BST film is formed ((d) of FIG. 5).

Next, RTA treatment is performed for 2 minutes in an oxygen atmosphere at a temperature of 800 ° C., for example. By this heat treatment, the ruthenium film 34 is completely oxidized to form the ruthenium oxide film 35, and the surface of the ruthenium film 11 is oxidized to about 10 nm.
The ruthenium oxide film 13 is formed, and the BST film is crystallized ((e) in FIG. 5). In this way, by forming a good interface between the BST film 12 and the upper and lower electrodes, a capacitor having a very high charge storage capacity can be realized.

Further, a titanium nitride film 37 is deposited on the ruthenium oxide film 35 by, for example, a sputtering method to reduce the sheet resistance of the upper electrode, and the DRAM memory cell is completed ((f in FIG. 5). )).

Thereafter, the wiring, the passivation film, etc. are formed in accordance with the usual LSI manufacturing process, and the DRA is formed.
M is completed. As described above, according to the present embodiment, the RTA process is performed after forming the layered structure sandwiching the ruthenium films 11 and 34 on the upper and lower sides of the amorphous BST film, and thereby, between the BST film 12 and the upper and lower electrodes. A good interface can be formed in any of them. Therefore, the BST film 1
The electric field in 2 can be relaxed not only in the vicinity of the lower electrode but also in the vicinity of the upper electrode.
It is possible to prevent a decrease in the dielectric constant when the film 12 is thinned.

Thus, according to the present embodiment, B
First to form a good interface only between the ST film and the lower electrode
As compared with the second embodiment, the charge storage ability is further improved, and particularly when the BST film is made thin, a capacitor having a very high capacitance can be realized.

Here, in order to form a good interface not only between the BST film 12 and the upper electrode but also between the lower electrode, oxygen reaches the interface between the BST film 12 and the lower electrode 11. Therefore, it is necessary to form the ruthenium oxide film 13.
Therefore, it is necessary to appropriately set the temperature, time, etc. of the oxidation step so that the upper electrode 34 is completely oxidized.

When it is more important to alleviate the high electric field on the upper electrode side due to the relationship between the voltages applied to the upper and lower electrodes, the ruthenium film is used only for the upper electrode and the lower electrode is used for the lower electrode. It is also possible to use conventional platinum.

Next, as a fourth embodiment, after the BST film is formed, oxidation is performed at a low temperature to reduce the thickness of the oxide film formed on the lower electrode, and further heat treatment is performed in a high-temperature non-oxidizing atmosphere. A method of making the crystallization of the BST film more complete by performing the method will be described.

Amorphous BS is formed on the lower electrode 11 of the capacitor formed of ruthenium by, for example, the CVD method.
The same process as in the first embodiment is performed until the T film 12 having a thickness of 15 nm is formed.

Next, unlike the first embodiment, RTA treatment is performed for 1 minute in an oxygen atmosphere at a temperature of 600 ° C., for example. By this heat treatment, the surface of the ruthenium film 11 has about 5
The ruthenium oxide film 13 having a thickness of nm is formed, and the crystallization of the BST film begins to proceed. Further, a good interface is formed at the interface between the ruthenium film 11 and the BST film 12.
Furthermore, RTA for 1 minute in a nitrogen atmosphere at a temperature of 850 ° C.
Perform processing. By this heat treatment, ruthenium film 11 and B
A sufficiently good interface is formed with the ST film 12, and the BST film 12 is sufficiently crystallized. At this time, the thickness of the ruthenium film 11 hardly increases.

Thereafter, similarly to the first embodiment, the titanium nitride film 14 is deposited by, for example, the sputtering method to form the upper electrode of the capacitor, and the DRAM memory cell is completed.

Thereafter, the wiring, the passivation film, etc. are formed in accordance with the usual LSI manufacturing process, and the DRA is formed.
M is completed. As described above, in the present embodiment, the ruthenium oxide film 13 formed on the lower electrode 11 is formed by lowering the heat treatment temperature of the oxidizing atmosphere to, for example, 600 ° C.
It is possible to reduce the film thickness and prevent the electrode from expanding in volume due to oxidation. Further, by performing heat treatment at a higher temperature in a non-oxidizing atmosphere, crystallization of the BST film 12 can be sufficiently promoted, and a sufficiently good interface can be formed between the ruthenium film 11 and the BST film 12.

As described above, the temperature, atmosphere, time, etc. of the heat treatment in the present invention depend on the interface characteristics between the electrode and the high dielectric film,
It can be appropriately set depending on the oxide film thickness formed on the electrode, the crystallization state of the BST film, and the like. Further, it is possible to combine several kinds of heat treatments as in the fourth embodiment of the present invention.

Particularly, in order to prevent the volume expansion of the electrode due to the oxidation, it is desirable to use a short-time heat treatment such as RTA, and further, it is possible to lower the temperature as in the fourth embodiment.

Further, even when only the heat treatment is performed in the non-oxidizing atmosphere, it is possible to form a good interface with the crystallization of the BST film, though it is not as good as the treatment in the oxidizing atmosphere.

In general, the higher the heat treatment temperature is, the better interface can be formed between the high dielectric film and the electrode. The above-described embodiments according to the present invention can be combined appropriately. For example, in the third embodiment, the method of performing the heat treatment in the oxidizing atmosphere after forming the upper electrode has been described.
It is also possible to combine the above embodiments and perform heat treatment in an oxidizing atmosphere and a non-oxidizing atmosphere after forming, for example, the upper electrode. Further, by combining the third embodiment and the second embodiment, heat treatment is performed after reducing the surface of the lower electrode formed of the ruthenium oxide film and forming the high dielectric film and the upper electrode. You can also

Further, in any of the above-mentioned embodiments, the temperature is 430 ° C. and the pressure is 3 k by the CVD method using Sr (THD) ₂ , Ba (THD) ₂ , Ti (THD) ₂ and N ₂ O as source gases.
An amorphous BST film was formed with Pa. For example, Sr (THD) ₂ ,
It is also possible to form an amorphous STO film at a temperature of 430 ° C. and a pressure of 3 kPa by a CVD method using TiO (THD) ₂ and N ₂ O as source gases. It is also possible to form the PZT film by the CVD method. Furthermore, the forming conditions such as temperature and pressure can be appropriately set so that an amorphous film having a good step coverage is formed.

Further, as the capacitor insulating film, BST, S
According to the present invention, the same effect can be obtained not only when using TO but also when using a ferroelectric having a perovskite structure containing an alkaline earth metal such as SrBi ₂ Ta ₂ O ₉ as a main component. Is.

Further, it is also possible to use a ferroelectric substance such as Pb _x La _1-x Zr _y Ti _1-y O ₃ . Further, not only a dielectric having a perovskite structure but also a high dielectric film such as Ta ₂ O ₅ can be used.

Further, in the above-mentioned embodiment, the high dielectric film is formed by using the CVD method. However, as the method of manufacturing the high dielectric film, sputtering method, vapor deposition method, MBE (molecular beam growth) is used.
Method, sol-gel method, laser ablation method or the like can be used.

Furthermore, in the above first, second and fourth embodiments, the upper electrode of the capacitor is formed using the titanium nitride film 14, but other conductive films such as tungsten nitride can be used. Is. Similarly, in the third embodiment, in order to reduce the sheet resistance of the upper electrode, the titanium nitride film 3 is formed on the ruthenium oxide film 35.
Although 7 is deposited, another metal having a low sheet resistance, such as tungsten nitride, may be formed on ruthenium oxide.

In the present invention, the high-dielectric film and the electrode film are formed and then heat-treated, so that both are heat-treated at the same time. For example, a transition layer is formed to form a good interface between them. To do. Therefore, if the ruthenium film is used for at least one of the upper and lower electrodes and the heat treatment is performed on the ruthenium film and the high dielectric film at the same time, the effect of the present invention can be obtained.

Further, not only the ruthenium film but also a noble metal film such as platinum (Pt), iridium (Ir), rhenium (Re), etc. is formed with a good interface with the high dielectric film by heat treatment. It is also possible to use other conductive films in combination.

In any of the above embodiments, the contact hole penetrating the n-type diffusion layer 5 is filled with the polycrystalline silicon film 10 containing arsenic.
Although the n-type diffusion layer 5 and the lower electrode 11 of the capacitor are electrically connected, a titanium nitride film, for example, may be formed between the polycrystalline silicon film 10 and the lower electrode 11 as shown in FIG. .

This method will be described with reference to FIG. Similar to the first embodiment, after the contact holes penetrating the n-type diffusion layer 5 are formed in the interlayer insulating films 9 and 6, the polycrystalline silicon film 10 containing arsenic is deposited by, for example, the CVD method. Then, the polycrystalline silicon film 10 is embedded in the contact hole by a method such as etch back. At this time, unlike the first embodiment, the surface of the polycrystalline silicon film 10 is made to recede from the surface of the interlayer insulating film 9 by controlling the time of the etch back and the like ((a) of FIG. 6).

Further, a titanium nitride film 21 is deposited by, for example, a sputtering method and etched back by, for example, a mechanical polishing method to leave the titanium nitride film 21 only in the contact hole (((6 in FIG. 6)). b)). After that, the lower electrode 11 is formed, for example, as in the first embodiment, and the DRAM is completed through the steps described above.

As described above, by forming, for example, the titanium nitride film 21 as a barrier metal between the polycrystalline silicon film 10 and the lower electrode 11, the polycrystalline silicon film 10 is formed.
The contact resistance between the lower electrode 11 and the lower electrode 11 can be reduced.

The material of the buried electrode is not limited to the polycrystalline silicon film, but a refractory metal film such as tungsten, or
It is possible to use a conductive film such as another metal film.
Further, the embedded electrode 10 can be formed not only by the etch-back method but also by a selective growth method, for example.

The case where the present invention is applied to the memory cell of the DRAM having the stack type capacitor structure has been described above, but the present invention is not limited to the memory cell having another capacitor structure such as the trench type capacitor structure or the DRAM.
The present invention can be applied to any semiconductor device such as FRAM having a capacitor structure using a high dielectric film as an insulating film.

[0083]

As described above, according to the method of manufacturing a semiconductor device of the present invention, an extremely thin high dielectric film having a small leak current and a high dielectric constant can be used as a capacitor insulating film. it can.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a band structure diagram of a capacitor manufactured according to the first embodiment of the present invention.

FIG. 3 is a diagram showing the film thickness dependence of the relative dielectric constant.

FIG. 4 is a process sectional view showing a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process sectional view showing a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a process sectional view showing a fifth embodiment of a method for manufacturing a semiconductor device according to the present invention.

7A to 7C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a diagram showing a dielectric constant developing mechanism of a high dielectric material having a perovskite crystal structure.

[Explanation of symbols]

1 ... Single crystal silicon substrate, 2 ... Element isolation region, 3 ... Gate
N electrodes, 4, 5 ... N-type diffusion layer regions, 6, 9 ... Interlayer insulating film, 7 ... Polycrystalline silicon film, 8 ... Bit line, 10 ... Arsenic doped polycrystalline silicon film, 11, 34 ... Ruthenium film ,
12, 52 ... BST film, 13, 22, 35 ... Ruthenium oxide film, 14, 21, 37 ... Titanium nitride film, 23 ... RuO
_x (x <2), 51, 53 ... Platinum

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kataro Imai 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (6)

[Claims] 1. A step of forming a dielectric film on at least a surface of a first conductor electrode containing ruthenium as a main component,
A semiconductor device comprising: a step of performing heat treatment in an oxidizing atmosphere at a temperature equal to or higher than a crystallization temperature of the dielectric film; and a step of forming a second conductor electrode on the dielectric film. Manufacturing method. 2. A step of forming a dielectric film on at least a surface of a first conductor electrode containing ruthenium as a main component,
Forming a second conductor electrode on the dielectric film;
And a step of performing a heat treatment at a temperature equal to or higher than the crystallization temperature of the dielectric film. 3. A step of forming a dielectric film on a first conductor electrode, and a step of forming a second conductor electrode having ruthenium as a main component on at least the interface with the dielectric film on the dielectric film. A method of manufacturing a semiconductor device, comprising: a forming step; and a heat treatment step at a temperature equal to or higher than a crystallization temperature of the dielectric film. 4. A step of forming a dielectric film on at least a surface of a first conductor electrode containing ruthenium as a main component,
Forming a second conductor electrode having ruthenium as a main component at least on an interface with the dielectric film on the dielectric film; and performing a heat treatment at a temperature equal to or higher than a crystallization temperature of the dielectric film. A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed in an oxidizing atmosphere. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is a metal oxide film containing one or more elements selected from a group consisting of barium, strontium and titanium.