JP3171173B2 - Capacitor structure and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a capacitor structure and a method of manufacturing the same, and more particularly, to a capacitor structure used for a dynamic random access memory (hereinafter referred to as DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor integrated circuits typified by DRAMs have been increasingly integrated. Regardless of the degree of integration, it is necessary to secure a capacitance of about 30 fF per semiconductor capacitance element. For this reason, studies have been made to utilize the side surface of the lower electrode by making the lower electrode structure three-dimensional and to secure the capacitance by making the capacitance film thinner.

Conventionally, a silicon oxide film and a silicon nitride film have been used as a capacitance film of the semiconductor capacitance element for a semiconductor integrated circuit. However, gigabit (Gbit)
When using the above-mentioned capacitance film having a dielectric constant of 3 to 7 in a DRAM of a level or higher, it is necessary to reduce the height of the three-dimensional lower electrode to 5000 Å or more, and to further reduce the capacitance film to a level of several atomic layers.

[0004] The lower electrode height causes problems such as exposure and dry etching during electrode processing. When the capacitance film is thinned down to the level of several atomic layers, a phenomenon occurs in which electrons tunnel through the capacitance film, and the capacitance film does not function as a capacitance film.

[0005] For the above reasons, the formation of a three-dimensional lower electrode using a silicon oxide film and a silicon nitride film as a capacitor film and a thinner capacitor film have reached their limits.

When a material having a large dielectric constant is used for the capacitance film, the same capacitance can be obtained with a smaller electrode area than when a silicon oxide film or a silicon nitride film is used.
For this reason, it is expected that the capacity can be ensured without creating a complicated lower electrode structure.

For the above reason, SrT having a dielectric constant several tens to several hundreds times higher than that of a silicon oxide film or a silicon nitride film.
High dielectric constant materials such as iO3, (Ba, Sr) TiO3 (hereinafter referred to as BST), and Pb (Zr, Ti) O3 have been studied as the capacitance film.

For example, at the 1991 International Electron Devices Meeting (Inter
national Electron Devices
Meetings Digest of Technical Papers (Digestof Technical)
Papers, pp. 823 to 826, reports on a 256 Mbit DRAM semiconductor capacitor using BST.

It is known that the higher the film forming temperature, the better the electrical characteristics of the high dielectric constant film can be obtained. Japanese Journal of Applied Physics (Japanese)
Journal of applied physics
cs) Volume 35, pages 5089 to 5093.

An example of this type of capacitor structure and a method of manufacturing the same are disclosed in Japanese Patent Application Laid-Open No. 8-97369 (hereinafter referred to as Document 1) and Japanese Patent Application Laid-Open No. 10-150155 (hereinafter referred to as Document 2). I have.

[0011]

However, when the capacitor film is formed at a high temperature, there is a problem that the dielectric constant is lowered due to the formation of an oxide film by diffusion of silicon from the polysilicon at the contact portion. In order to solve this problem, a silicon diffusion barrier layer is used, and in order to suppress the increase in the contact resistance due to oxidation of the silicon diffusion barrier layer, an electrode structure in which an oxidation resistant barrier layer is formed thereon has been developed using a Japanese electrode.
Journal of Applied Physics (Japan)
nice Journal of applied p
hysiscs), Vol. 34, pp. 5224-5228.

However, when this structure is processed into a stack shape and the electrode structure is further miniaturized, there is a problem that the silicon diffusion barrier layer is oxidized and the contact resistance is increased. Therefore, the 1996 International Electron Devices Meeting (International)
Electron Devices Meeting)
Digest of Technical Papers (Dig)
est of Technical Papers) pp. 675-678 and US Pat.
A structure has been proposed in which a silicon barrier layer is buried in a contact and capped with an oxygen diffusion barrier so that a low contact resistance can be maintained even at a high temperature for forming a high dielectric constant film.

The above structure is an effective method when ideal stack processing can be performed. However, when a misalignment occurs between the stack electrode and the contact, the silicon diffusion barrier layer is exposed in an oxygen atmosphere, and there has been a problem that it is not possible to suppress an increase in contact resistance. The means for solving this problem is not disclosed in the above-mentioned documents 1 and 2.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a capacitor structure and a method of manufacturing the same, which can suppress the increase in contact resistance even if misalignment occurs between the stack electrode and the contact.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a contact and a lower part in which an end of the contact and an end of the contact are stacked on the upper part of the contact with misalignment. A capacitor structure including an electrode, a capacitor film deposited on the lower electrode, and an upper electrode deposited on the capacitor film, wherein a step portion caused by the misalignment is formed between the capacitor film and the lower electrode. Top and the capacity
It is characterized by including an insulating film deposited between the films.

Another invention according to the present invention is directed to a contact, a lower electrode in which an end of the contact and an end of the contact are stacked on the contact with a misalignment, A method for manufacturing a capacitor structure including a capacitor film to be deposited and an upper electrode to be deposited on the capacitor film, the manufacturing method comprising: a first step of fabricating the contact; A second step of forming the lower electrode above the contact, a third step of depositing an insulating film on the lower electrode after the second step, and a step of depositing the capacitor film on the insulating film after the third step A fourth step of depositing the upper electrode on the capacitor film after the fourth step, and a sixth step of dry-etching the upper electrode after the fifth step. It is characterized by including.

According to the present invention and another invention according to the present invention, since a portion where the lower electrode and the contact are misaligned is covered with the insulating film, the gap between the stack electrode (lower electrode) and the contact is reduced. , It is possible to suppress an increase in contact resistance.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the features of the present invention will be outlined. The present invention provides a capacitor structure for preventing a position where misalignment between a contact and a stack electrode or a silicon diffusion barrier layer exposed under a stack electrode is oxidized by oxygen at the time of forming a capacitance film, thereby preventing a contact resistance from increasing. It is intended to provide.

More specifically, the present invention is characterized in that a part or the whole of a silicon diffusion barrier layer or a polysilicon (contact) portion exposed to oxygen is covered with an insulating film having an oxygen diffusion barrier property.

Further, as a method of manufacturing the structure of the present invention,
(1) An insulating film is formed on a part or the entire surface of the exposed silicon diffusion barrier layer or polysilicon portion by using a film forming method with low step coverage without using oxygen gas as a process gas. (2) The method is characterized in that the insulating film is formed by wet or dry etch-back so as to leave a portion or the entire surface of the exposed silicon diffusion barrier layer or polysilicon portion.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. First, a first embodiment will be described. FIG. 4 is a cross-sectional view of the first embodiment of the capacitor structure according to the present invention.

Referring to FIG. 4, a contact 1 comprising a capacitor contact 102 and a silicon diffusion barrier layer 103 and a lower electrode (hereinafter referred to as a stack electrode) 2 comprising an oxygen-resistant diffusion barrier layer 104 are misaligned. A structure in which the upper part of the silicon diffusion barrier layer 103 and the oxygen-resistant diffusion barrier layer 104 exposed in the misaligned portion is covered with an insulating film 105 formed by a film formation method having poor step coverage. ing.

As a result, it is possible to prevent the silicon diffusion barrier layer 103 from being oxidized by oxygen when the capacitance film 106 is formed.

In the first embodiment, the contact 1
Represents the capacitance contact 102 and the silicon diffusion barrier layer 10
3, the stack electrode 2 is formed only of the oxygen-resistant diffusion barrier layer 104.

Next, a second embodiment will be described. FIG. 8 is a sectional view of a second embodiment of the capacitor structure according to the present invention.

Referring to FIG. 8, capacitance contact 102
And the stack electrode 2 composed of the oxygen-resistant diffusion barrier layer 104 and the silicon diffusion barrier layer 103 are misaligned, and a part of the exposed side surface of the silicon diffusion barrier layer 103, the capacitance contact 102 composed of polysilicon, and The upper portion of the oxygen-resistant diffusion barrier layer 104 is covered with an insulating film 105 formed by a film formation method having poor step coverage.

As a result, the silicon diffusion barrier layer 103, the polysilicon 102
Can be prevented from being oxidized.

In the second embodiment, the contact 1
Is formed only by the capacitor contact 102, and the stack electrode 2 is formed by the silicon diffusion barrier layer 103 and the oxygen-resistant diffusion barrier layer 104.

Next, a third embodiment will be described. FIG. 12 is a sectional view of a third embodiment of the capacitor structure according to the present invention.

Referring to FIG. 12, capacitance contact 102
1 consisting of silicon and silicon diffusion barrier layer 103
And the stack electrode 2 composed of the oxygen diffusion barrier layer 104 is misaligned, and a part of the silicon diffusion barrier layer 103 exposed at the misaligned portion is covered with the insulating film 109. Have.

As a result, it is possible to prevent the silicon diffusion barrier layer 103 from being oxidized in an oxygen atmosphere when the capacitance film 106 is formed.

In the third embodiment, as in the first embodiment, the contact 1 is formed by the capacitor contact 102 and the silicon diffusion barrier layer 103, and the stack electrode 2 is formed by the oxygen-resistant diffusion barrier layer 104. It is formed only with.

Next, a fourth embodiment will be described. FIG. 16 is a sectional view of a fourth embodiment of the capacitor structure according to the present invention.

Referring to FIG. 16, capacitance contact 102
And the stack electrode 2 composed of the oxygen-resistant diffusion barrier layer 104 and the silicon diffusion barrier layer 103 are misaligned. It has a structure in which a part of the side surface is covered with the oxide film 109.

As a result, it is possible to prevent the silicon diffusion barrier layer 103 from being oxidized in an oxygen atmosphere when the capacitance film 106 is formed.

In the fourth embodiment, as in the second embodiment, the contact 1 is formed only of the capacitor contact 102, and the stack electrode 2 is formed of the silicon diffusion barrier layer 103 and the oxygen-resistant diffusion barrier layer. 104.

Next, the details of the capacitor structure and the manufacturing method thereof will be described with reference to examples.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment will be described. This first example shows an example of the first embodiment. 1 to 4 are process diagrams showing a capacitor structure manufacturing process of the first embodiment, and FIG. 19 is a flowchart of the process.

The first embodiment is characterized in that the insulating film 105 is formed by using a film forming method having poor step coverage.

Referring to FIG. 1, a capacitor contact 102 made of polysilicon opened in an insulating film 101 made of SiO 2, and further thereon 500 A (angstrom) of titanium nitride (TiN) and titanium (Ti).
Is formed in the insulating film 101 (see S1 in FIG. 19).

Further, ruthenium oxide (Ru)
An oxidation-resistant barrier layer 104 made of O2) is processed into a stack electrode 2 having a desired size by a dry etching method (see S2 in the same figure).

The stack electrode 2 made of RuO 2 and the capacitor contact 102 are misaligned, and the silicon diffusion barrier layer 103 is exposed.

At this time, the height of RuO2104 is 5000
A (angstrom), width 0.5μm × 0.2μ
m, the stack interval between RuO2104 and RuO2104 is 0.15 μm, and the diameter of the capacitive contact 102 is 0.14 μm.
m and the amount of misalignment (= capacitive contact 102
Is the maximum exposed length) is 0.07 μm.

Next, as shown in FIG. 2, an insulating film 105 of SiO 2 is deposited at 500 A by a collimated sputtering method which does not contain oxygen in the process gas. The sputtering conditions at this time are as follows.

SiO 2 as the target and A as the sputtering gas
r, plasma power is 2 kW, DC applied voltage is 5
00V, deposition chamber pressure 3 mTorr, substrate heating 100
° C.

The insulating film 105 is deposited only on the upper surface of the stack electrode 2 made of RuO 2 and between the stack electrodes 2 by using the collimated sputtering method having poor step coverage (see FIG. 3 in FIG. 3).

Further, as shown in FIG. 3, strontium titanate (SrTiO 3, hereinafter referred to as ST
Is referred to as ECRCVD (Electron Cyclotron Resonance Chemical Vapor Deposition).
ance Chemical Vapor Depos
(ECR-CVD method) (see S4 in FIG. 4).

The ST film forming conditions at this time are as follows.
The film forming temperature was 500 ° C., the film forming chamber pressure was 7 mTorr, the plasma power was 750 W, and Sr (DPM) was used as a raw material.
2 (dipivaloyl methanate strontium) and titanium isoprocoxide (hereinafter referred to as Ti (Oi-Pr) 4), each of which was transported to the film formation chamber using argon (Ar) as a carrier gas. Is mixed with oxygen gas to form a film.

Subsequently, as shown in FIG.
Ru is deposited to a thickness of 100 nm by sputtering (see S5 in FIG. 19).

The deposition conditions at this time are as follows. Ru is used for the target, Ar is used for the sputtering gas, the plasma power is 2 kW, the DC application voltage is 500 V, the film forming chamber pressure is 3 mTorr, and the substrate heating is 100 ° C.

Further, the upper electrode 107 is processed into an appropriate size by a dry etching method to form a capacitor (see S6 in the same figure).

FIG. 22 is a sectional view of an example of a conventional capacitor structure. In the figure, the same components as those in FIGS. 1 to 4 are denoted by the same reference numerals.

The conventional capacitor structure differs from the structure of the present invention in that the conventional capacitor structure (see FIG. 22) does not have the insulating film 105 of the present invention (see FIG. 4).

FIG. 17 shows the result of comparing the contact resistance when an ST106 film is formed at a film formation temperature of 100 ° C. to 600 ° C. using the conventional structure shown in FIG. 22 and the capacitor structure according to the present invention. FIG. 17 is a first contact resistance versus film forming temperature characteristic diagram.

Referring to FIG. 17, in the prior art, the silicon diffusion barrier layer 103 is
Is oxidized and the conductivity is deteriorated, so that the contact resistance is 4
It rises from about 00 ° C.

On the other hand, in the present invention, almost no increase in the contact resistance was observed even when the film was formed at 600 ° C., and the low contact resistance was maintained.

Further, according to the present invention, desired characteristics can be obtained only by adding one step (S3), and there is an advantage that an effect can be obtained with a minimum increase in steps.

Next, a second embodiment will be described. This second example shows an example of the second embodiment.
5 to 8 are process diagrams showing a capacitor structure manufacturing process of the second embodiment. The flowchart in FIG. 19 is used.

As in the first embodiment, the second embodiment has a feature that an insulating film is formed by using a film forming method having poor step coverage.

As shown in FIG. 5, a capacitance contact 102 made of polysilicon is formed in an insulating film 101 made of SiO2 (see S1 in FIG. 19).

A silicon diffusion barrier layer 1 having a laminated structure of titanium nitride (TiN) and titanium (Ti)
03, a stack of an oxidation-resistant barrier layer 104 made of ruthenium oxide (RuO2) is formed on the stacked electrode 2 having a desired size by dry etching (S2 in FIG. 3).

The stack electrode 2 composed of the silicon diffusion barrier layer 103 and the oxygen-resistant diffusion barrier layer 104 and the capacitance contact 102 are misaligned, and the side surface of the silicon diffusion barrier layer 103 and the capacitance contact 102 composed of polysilicon are exposed. ing.

At this time, the height of RuO2104 is 5000
A, width 0.5 μm × 0.2 μm, RuO2104 and R
The stack interval of uO2104 is 0.15 μm, the diameter of the capacitance contact is 0.14 μm, and the amount of misalignment (= the length of the maximum exposed portion of the capacitance contact)
Is 0.07 μm.

Hereinafter, a capacitor is manufactured by the same steps as in the first embodiment. At this time, the silicon barrier layer 103
The thickness of the insulating film 105 was set so that a part of the side surface of the insulating film 105 was covered with the insulating film 105 (see FIGS. 6 to 8).

FIG. 18 is a graph showing a second contact resistance versus film forming temperature characteristic. Since the exposed polysilicon 102 and part of the side surface of the silicon diffusion barrier layer 103 are covered with the insulating film 105, oxidation due to ST film formation is suppressed,
As shown in FIG. 18, it is possible to suppress an increase in contact resistance.

In the present invention, the silicon diffusion barrier layer 103
Although the thickness of the insulating film 105 in contact with the side surface is set to 400 A, if the thickness is set to cover the entire side surface of the silicon diffusion barrier layer 103, the effect of preventing oxygen gas from oxidizing the side surface of the silicon diffusion barrier layer 103 is increased. As shown in FIG. 17, the oxidation resistance is further improved.

Next, a third embodiment will be described. This third example shows an example of the third embodiment.
9 to 12 are process diagrams showing a capacitor structure manufacturing process of the third embodiment, and FIG. 20 is a flowchart of the process.

The third embodiment is characterized in that after the insulating film 109 is formed, etching is performed to a desired shape by wet etching back.

As shown in FIG. 9, a capacitor contact 102 made of polysilicon opened in an insulating film 101 made of SiO 2, and a 500 A titanium nitride (TiN) / titanium (Ti) laminated structure is further formed thereon. The silicon diffusion barrier layer 103 is buried in the insulating film 101 (see S11 in FIG. 20).

Further, ruthenium oxide (Ru)
The oxygen-resistant diffusion barrier layer 104 made of O2) is processed into a stack electrode 2 having a desired size by a dry etching method (S12 in the same figure).

The stack electrode 2 made of RuO 2 and the capacitor contact 102 are misaligned, and the silicon diffusion barrier layer 103 is exposed.

At this time, the height of RuO2104 is 5000
A, width 0.5 μm × 0.2 μm, RuO2104 and R
The stack interval of the uO2104 is 0.15 μm, the diameter of the capacitance contact 102 is 0.14 μm, and the amount of misalignment (= the length of the maximum exposed portion of the capacitance contact) is 0.07 μm. Next, as shown in FIG. 10, 5000 A of SiO2109, which is an insulating film, is deposited by long throw sputtering to cover the entire stack electrode 2 (S13 in FIG. 10).

The film forming conditions at this time are as follows. The target is SiO 2, the sputtering gas is Ar, the plasma power is 2 kW, the DC application voltage is 500 V, the film forming chamber pressure is 3 mTorr, and the substrate heating is 100 ° C.

Subsequently, buffered hydrofluoric acid (BHF)
Is used to wet-etch the insulating film 109 (S14 in the same figure).

Utilizing the fact that wet etching is isotropic, a part of the silicon diffusion barrier layer 103 has a thickness of 0.5 μm.
The insulating film 109 covers m portions (see FIG. 11).

Subsequently, as shown in FIG.
Is deposited by ECRCVD to a thickness of 30 nm (S15).

Further, Ru as the upper electrode 107 is deposited to a thickness of 100 nm by a sputtering method (see S16 in FIG. 20), and processed into an appropriate size by a dry etching method to form a capacitor (S17).

According to the present invention, it is possible to obtain a low contact resistance in film formation at a high temperature as shown in FIG.

In the present invention, the silicon diffusion barrier layer 103
Is partially covered with the insulating film 109, but by covering the entire silicon diffusion barrier layer 103, the effect of suppressing oxidation is improved, and as shown in FIG. 17, the oxidation resistance is further improved.

Further, in the structure according to the present embodiment, since the insulating film 109 does not exist on the oxygen-resistant diffusion barrier layer 104, it is possible to obtain a wider electrode area than the structure used in the first and second embodiments. There is an advantage in possible points.

Next, a fourth embodiment will be described. This fourth example shows another example of the third embodiment. 9 to 12 are also used in the fourth embodiment. FIG.
9 is a flowchart showing the steps of the third embodiment.

The fourth embodiment is characterized in that after the insulating film 109 is formed, it is etched to a desired shape by dry etch back.

The detailed film forming conditions are the same as in the third embodiment.

As shown in FIG. 9, a capacitor contact 102 made of polysilicon opened in an insulating film 101 made of SiO 2, and a titanium nitride (Ti)
A silicon diffusion barrier layer 103 having a laminated structure of N) and titanium (Ti) is embedded in the insulating film 101 (see S21 in FIG. 21).

Further, ruthenium oxide (Ru)
The oxygen-resistant diffusion barrier layer 104 made of O2) is processed into a stack electrode 2 having a desired size by a dry etching method (S22 in the same figure).

The stack electrode 2 made of RuO 2 and the capacitor contact 102 are misaligned, and the silicon diffusion barrier layer 103 is exposed.

The height of RuO2104 at this time is 5000
A, width 0.5 μm × 0.2 μm, RuO2104 and R
The stack interval of the uO2104 is 0.15 μm, the diameter of the capacitance contact 102 is 0.14 μm, and the amount of misalignment (= the length of the maximum exposed portion of the capacitance contact) is 0.07 μm.

Next, as shown in FIG.
iO2109 was 5,000 by long throw sputtering.
A is deposited to cover the entire stack electrode 2 (S23).

Subsequently, the insulating film 109 is etched back by dry etching using SF6 (sulfur hexafluoride), and a part of the exposed capacitance contact 102 is 0.5 μm thick.
This was processed so as to cover the insulating film 109 (see S24 in FIGS. 11 and 21). At this time, a condition having strong isotropy was used.

Subsequently, as shown in FIG.
ST having a thickness of 6 is deposited to a thickness of 30 nm by ECRCVD (see S25 in FIG. 21).

Further, Ru, which is the upper electrode 107, is deposited to a thickness of 100 nm by sputtering (S26 in the same figure) and processed to an appropriate size by dry etching to form a capacitor (S27 in the same figure).

In the present invention, the silicon diffusion barrier layer 103
Is partially covered by the insulating film 109, but by covering the entire silicon diffusion barrier layer 103, the effect of suppressing oxidation is improved and the oxidation resistance is further improved.

Next, a fifth embodiment will be described. This fifth example shows an example of the fourth embodiment.
13 to 16 are process diagrams showing a capacitor structure manufacturing process of the fifth embodiment. The fifth embodiment uses the flowchart of FIG.

The fifth embodiment is characterized in that after the insulating film 109 is formed, etching is performed to a desired shape by wet etching back.

As shown in FIG. 13, a capacitor contact 102 made of polysilicon is formed in an insulating film 101 made of SiO2 (see S11 in FIG. 20).

A silicon diffusion barrier layer 1 having a laminated structure of titanium nitride (TiN) and titanium (Ti)
03, and a stack of an oxygen-resistant diffusion barrier layer 104 made of ruthenium oxide (RuO2) formed on the stacked electrode 2 having a desired size by dry etching (S12 in the same figure).

The misalignment between the stack electrode 2 composed of the silicon diffusion barrier layer 103 and the oxygen-resistant diffusion barrier layer 104 and the capacitance contact 102 has occurred, and the side surface of the silicon diffusion barrier layer 103 and the polysilicon 102 are exposed. Has become.

At this time, the height of RuO2104 is 5000
A, width 0.5 μm × 0.2 μm, RuO2104 and R
The stack interval of the uO2104 is 0.15 μm, the diameter of the capacitance contact 102 is 0.14 μm, and the amount of misalignment (= the length of the maximum exposed portion of the capacitance contact) is 0.07 μm.

Next, as shown in FIG.
iO2109 was 5,000 by long throw sputtering.
A is deposited to cover the entire stack electrode 2 (S13 in the same figure).

The film forming conditions at this time are as follows. The target is SiO 2, the sputtering gas is Ar, the plasma power is 2 kW, the DC application voltage is 500 V, the film forming chamber pressure is 3 mTorr, and the substrate heating is 100 ° C.

Subsequently, buffered hydrofluoric acid (BHF)
Is used to wet-etch the insulating film 109 (S1).
4).

Utilizing that the wet etching is isotropic, the insulating film 109 covers all the exposed capacitance contacts 102 and a part of the silicon diffusion barrier layer 103 corresponding to 0.5 μm (FIG. 15).

Hereinafter, a capacitor is manufactured by the same steps as in the third embodiment. When forming the insulating film 109, the thickness of the insulating film 109 was set to 400 A so that part of the silicon diffusion barrier layer 103 was covered with the insulating film 109.

In the present invention, the silicon diffusion barrier layer 103
Although only the insulating film 109 partially covers the capacitor contact 102, when the capacitor contact 102 and the silicon diffusion barrier layer 103 partially cover the insulating film 109,
The same effect can be obtained when only 2 is partially covered with the insulating film 109.

By completely covering the silicon diffusion barrier layer 103 and the capacitor contact 102, the effect of suppressing oxidation is improved, and the oxidation resistance is further improved.

As a result, the exposed polysilicon 10
2 and the silicon diffusion barrier layer 103 are partially or entirely covered with the insulating film, so that oxidation is suppressed,
As shown in FIG. 17, an increase in contact resistance can be suppressed.

Although wet etching is used in this embodiment, the same effect can be obtained by the dry etching method used in the fourth embodiment.

In the above five embodiments, RuO 2 was used as the oxygen-resistant diffusion barrier layer 104 and Ru was used as the upper electrode 107. However, platinum (Pt), iridium (I
r), palladium (Pd), tungsten (W), R
u (ruthenium) and oxides and nitrides thereof, and strontium ruthenium oxide (SrRuO)
Similar effects can be obtained with oxides such as 3se4).

Furthermore, in the above embodiment, ST was used as the capacitance film 106, but it was represented by ABO3, where A was Ba,
At least one of Sr, Pb, Ca, La, Li, or K, and B is Zr, Ti, Ta, Nb, M
g, Fe, Zn, or at least one element of W, or a chemical formula of (Bi2O
2) represented by (Xm-1YmO3m + 1) (m is a positive integer), and X is Ba, Sr, Pb, Ca, K, or B
i is at least one kind, Y is Nb, Ta, T
The same effect can be obtained even if the capacitor film is one or more elements of i or W, or its chemical formula is Ta2O5 or BaMgF4.

Although SiO2 was used as the insulating film (109 or 105), SiN (silicon nitride film), A
The same effect can be obtained with l2O3 (aluminum oxide).

[0111]

According to the present invention, a contact, a lower electrode on which the end of the contact and the end of the contact are laminated with a misalignment over the contact, and a lower electrode deposited on the lower electrode. A capacitor structure comprising: a capacitor film having an upper electrode deposited on the capacitor film, wherein the capacitor structure includes a step portion caused by the misalignment and an insulating film deposited between the capacitor film. With this configuration, even if misalignment occurs between the stack electrode and the contact, it is possible to suppress an increase in contact resistance.

According to another aspect of the present invention, there is provided a contact, a lower electrode on which an end of the contact and an end of the contact are stacked with a misalignment above the contact, A method of manufacturing a capacitor structure including a capacitance film deposited on an electrode and an upper electrode deposited on the capacitance film, the method comprising: a first step of fabricating the contact; A second step of forming the lower electrode on the contact, and a third step of depositing an insulating film on the lower electrode after the second step;
Following the third step, a fourth step of depositing the capacitor film on the insulating film, a step of depositing the upper electrode on the capacitor film after the fourth step, and a step of following the fifth step And a sixth step of dry-etching the upper electrode. Therefore, even if misalignment occurs between the stack electrode and the contact, it is possible to suppress an increase in contact resistance.

[Brief description of the drawings]

FIG. 1 is a process chart showing a capacitor structure manufacturing process of a first embodiment according to the present invention.

FIG. 2 is a process diagram showing a capacitor structure manufacturing process according to a first embodiment of the present invention.

FIG. 3 is a process diagram showing a capacitor structure manufacturing process of the first embodiment according to the present invention.

FIG. 4 is a sectional view of a first embodiment of the capacitor structure according to the present invention.

FIG. 5 is a process diagram showing a capacitor structure manufacturing process of a second embodiment.

FIG. 6 is a process diagram showing a capacitor structure manufacturing process of a second embodiment.

FIG. 7 is a process chart showing a capacitor structure manufacturing process of a second embodiment.

FIG. 8 is a sectional view of a second embodiment of the capacitor structure according to the present invention.

FIG. 9 is a process chart showing a capacitor structure manufacturing process of a third embodiment.

FIG. 10 is a process diagram showing a capacitor structure manufacturing process of a third embodiment.

FIG. 11 is a process diagram showing a capacitor structure manufacturing process of a third embodiment.

FIG. 12 is a sectional view of a third embodiment of the capacitor structure according to the present invention.

FIG. 13 is a process chart showing a capacitor structure manufacturing process of the fifth embodiment.

FIG. 14 is a process chart showing a capacitor structure fabricating step of the fifth embodiment.

FIG. 15 is a process chart showing a capacitor structure fabricating step of the fifth embodiment.

FIG. 16 is a sectional view of a fourth embodiment of the capacitor structure according to the present invention.

FIG. 17 is a first contact resistance versus film forming temperature characteristic diagram.

FIG. 18 is a graph showing a second contact resistance versus film forming temperature characteristic.

FIG. 19 is a flowchart of a capacitor structure manufacturing process of the first embodiment.

FIG. 20 is a flowchart of a capacitor structure manufacturing process of the third embodiment.

FIG. 21 is a flowchart showing the steps of the third embodiment.

FIG. 22 is a sectional view of an example of a conventional capacitor structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Contact 2 Lower electrode 102 Capacitance contact 103 Silicon diffusion barrier layer 104 Oxygen-resistant diffusion barrier layer 105,109 Insulating film 106 Capacity film 107 Upper electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-94600 (JP, A) JP-A-9-186299 (JP, A) JP-A-10-303395 (JP, A) JP-A-11- 330405 (JP, A) JP-A-5-110026 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] A contact, a lower electrode laminated on the contact with an end of the contact being misaligned with the end thereof, a capacitor film deposited on the lower electrode, A capacitor structure including an upper electrode deposited on a capacitance film, wherein a step portion caused by the misalignment and the capacitance film
And a dielectric film deposited between the upper part of the lower electrode and the capacitance film . 2. The method according to claim 1, wherein the contact is formed by a capacitor contact and a silicon diffusion barrier layer stacked on the capacitor contact, and the lower electrode is formed by an oxygen-resistant diffusion barrier layer. 2. The capacitor structure according to 1. 3. The method according to claim 1, wherein the contact is formed by a capacitive contact, and the lower electrode is formed by a silicon diffusion barrier layer and an oxygen-resistant diffusion barrier layer laminated on the silicon diffusion barrier layer. The capacitor structure according to claim 1. 4. A contact, a lower electrode which is stacked above the contact with an end of the contact being misaligned, and a capacitor film deposited on the lower electrode. A method of manufacturing a capacitor structure including an upper electrode deposited on a capacitance film, comprising: a first step of forming the contact; and a second step of forming the lower electrode above the contact after the first step. A third step of depositing an insulating film on the lower electrode after the second step; a fourth step of depositing the capacitor film on the insulating film after the third step; A fifth step of depositing the upper electrode on the capacitor film, and a sixth step of dry-etching the upper electrode after the fifth step. 5. A contact, a lower electrode which is stacked above the contact with an end of the contact being misaligned, and a capacitor film deposited on the lower electrode; A method of manufacturing a capacitor structure including an upper electrode deposited on a capacitance film, comprising: an eleventh step of forming the contact; and a twelfth step of forming the lower electrode above the contact after the eleventh step. A twelfth step, a thirteenth step of depositing an insulating film on an upper portion of the lower electrode and a step portion below the lower electrode caused by the misalignment, and a thirteenth step, and A fourteenth step of depositing the capacitance film on the exposed portion of the electrode and the insulating film; and a fifteenth step of depositing the upper electrode on the capacitance film after the fourteenth step.
5. The method according to claim 4, further comprising the step of: performing a dry etching on the upper electrode after the fifteenth step. 6. A contact, a lower electrode which is stacked above the contact with an end of the contact being misaligned, and a capacitor film deposited on the lower electrode. A method of manufacturing a capacitor structure including an upper electrode deposited on a capacitance film, comprising: a twenty-first step of forming the contact; and a twenty-second step of forming the lower electrode above the contact after the twenty-first step. A twenty-third step of depositing an insulating film over the entire lower electrode following the twenty-second step; a twenty-fourth step of performing wet etching on the insulating film following the twenty-third step; Next, a twenty-fifth step of depositing the capacitance film on the exposed portion of the lower electrode and the insulating film; a twenty-sixth step of depositing the upper electrode on the capacitance film after the twenty-fifth step; Process The method for manufacturing a capacitor structure according to claim 4, wherein the upper electrode and a second 27 step of performing dry etching. 7. A contact, a lower electrode laminated on the contact with an end of the contact being misaligned with the end thereof, a capacitor film deposited on the lower electrode, 31. A method for manufacturing a capacitor structure including an upper electrode deposited on a capacitance film, comprising: a 31st step of forming the contact; and 32nd step of forming the lower electrode above the contact after the 31st step. A step of depositing an insulating film over the entire lower electrode following the 32nd step, a 34th step of performing dry etching on the insulating film after the 33rd step, and a 34th step Next, a thirty-fifth step of depositing the capacitance film on the exposed portion of the lower electrode and the insulating film; a thirty-sixth step of depositing the upper electrode on the capacitance film after the thirty-fifth step; Next to process Method for manufacturing a capacitor structure according to claim 4, characterized in that it comprises a first 37 step of performing dry etching on the upper electrode. 8. The device according to claim 1, wherein the contact is formed by a capacitor contact and a silicon diffusion barrier layer stacked on the capacitor contact, and the lower electrode is formed by an oxygen-resistant diffusion barrier layer. 8. The method for manufacturing a capacitor structure according to any one of 4 to 7. 9. The method according to claim 9, wherein the contact is formed by a capacitance contact, and the lower electrode is formed by a silicon diffusion barrier layer and an oxygen-resistant diffusion barrier layer laminated on the silicon diffusion barrier layer. Claims 4 to 6
A method for manufacturing the capacitor structure according to any one of the above.