JP4641702B2 - Ferroelectric nonvolatile semiconductor memory and manufacturing method thereof - Google Patents

Description

【００８４】
あるいは又、ＳｒＢｉ₂Ｔａ₂Ｏ₉から成る強誘電体層２２をパルスレーザアブレーション法、上述のようにゾル−ゲル法、あるいはＲＦスパッタリング法にて全面に形成することもできる。これらの場合の形成条件を、それぞれ、以下の表３、表４、表５に例示する。尚、ゾル−ゲル法によって厚い強誘電体層２２を形成する場合、所望の回数、スピンコート及び乾燥、あるいはスピンコート及び焼成（又は、アニール処理）を繰り返せばよい。
【００８５】
［表３］
パルスレーザアブレーション法による形成
ターゲット：ＳｒＢｉ₂Ｔａ₂Ｏ₉
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、５Ｈｚ）
形成温度 ：４００〜８００゜Ｃ
酸素濃度 ：３Ｐａ
【００８６】

【００８７】
［表５］
ＲＦスパッタリング法による形成
ターゲット：ＳｒＢｉ₂Ｔａ₂Ｏ₉セラミックターゲット
ＲＦパワー：１．２Ｗ〜２．０Ｗ／ターゲット１ｃｍ²
雰囲気圧力：０．２〜１．３Ｐａ
形成温度 ：室温〜６００゜Ｃ
プロセスガス：Ａｒ／Ｏ₂の流量比＝２／１〜９／１
【００８８】
強誘電体層を、ＰＺＴあるいはＰＬＺＴから構成するときの、マグネトロンスパッタリング法によるＰＺＴあるいはＰＬＺＴの形成条件を以下の表６に例示する。あるいは又、ＰＺＴやＰＬＺＴを、反応性スパッタリング法、電子ビーム蒸着法、ゾル−ゲル法、又は、ＭＯＣＶＤ法にて形成することもできる。
【００８９】
［表６］
ターゲット ：ＰＺＴあるいはＰＬＺＴ
プロセスガス：Ａｒ／Ｏ₂＝９０体積％／１０体積％
圧力 ：４Ｐａ
パワー ：５０Ｗ
形成温度 ：５００゜Ｃ
【００９０】
更には、ＰＺＴやＰＬＺＴをパルスレーザアブレーション法にて形成することもできる。この場合の形成条件を以下の表７に例示する。
【００９１】
［表７］
ターゲット：ＰＺＴ又はＰＬＺＴ
使用レーザ：ＫｒＦエキシマレーザ（波長２４８ｎｍ、パルス幅２５ｎ秒、３Ｈｚ）
出力エネルギー：４００ｍＪ（１．１Ｊ／ｃｍ²）
形成温度 ：５５０〜６００゜Ｃ
酸素濃度 ：４０〜１２０Ｐａ
【００９２】
以上に説明した各種の強誘電体層２２の形成方法は、以下に説明する実施の形態においても適用することができる。
【００９３】
高温での強誘電体層２２の形成において、下部電極２１と酸素バリア層３０との界面からの酸素拡散を完全に防ぐことは容易ではないものの、コンタクトプラグ１８Ａの酸化を防止し、下部電極２１とコンタクトプラグ１８Ａとの間のコンタクト抵抗の上昇を防ぐことができれば、不揮発性メモリの動作上、実質的に問題は生じない。この界面経由の酸素拡散の問題について、本発明者らは、複雑な測定パターンを形成することなく、簡便に評価できる評価方法を見出した。この評価方法に基づき、下部電極２１の厚さ（より正確には、下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁）を設定することで、コンタクトプラグ１８Ａの酸化を防止することができる。
【００９４】
この評価手法は、例えば、拡散バリア層２０を構成するＴｉＮやＴａＮは、酸化によって体積膨張を伴うことを応用している。即ち、［工程−１６０］において強誘電体層２２を形成した後、走査型電子顕微鏡（ＳＥＭ）等を用いて拡散バリア層２０の酸化状態を観察する。即ち、拡散バリア層２０の膨張状態を観察する。この状態を、図５の（Ａ）に模式的に図示する。尚、拡散バリア層２０の酸化による膨張に伴い、下部電極２１、強誘電体層２２の形状も変化するが、図５の（Ａ）には、これらの変化の図示を省略した。これを、下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁、及び、［工程−１６０］における強誘電体層２２の結晶化のための熱処理温度をパラメータとして、拡散バリア層２０の側壁２１Ａからどのくらいの距離まで拡散バリア層２０が酸化したかを評価する。下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁と、酸化された拡散バリア層２０の領域１２０の拡散バリア層２０の側壁からの距離Ｌは、図５の（Ｂ）に模式的に示すような関係にある。即ち、長さＬ₁の値が大きいほど距離Ｌの値は小さくなる。
【００９５】
距離Ｌの値が、開口部１７Ａの上端部１７ａから下部電極２１の側壁２１Ａの下端部２１ａまでの水平方向最短距離Ｌ₀の値よりも小さければ（あるいは十分に小さければ）、コンタクトプラグ１８Ａが酸化されることはない。例えば、下部電極２１をＩｒから構成し、酸素バリア層３０としてＡｌ₂Ｏ₃を用いた場合、ＳＢＴのように結晶化温度が７００゜Ｃ程度と高温を要する場合、距離Ｌを０．４μｍ以下に抑制するためには、下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁を１５０ｎｍ以上とすればよいことが、各種の試験の結果、判明した。また、ＰＺＴのようにのように結晶化温度が６００゜Ｃ程度である場合、距離Ｌを０．４μｍ以下に抑制するためには、下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁を８０ｎｍ以上とすればよいことが、各種の試験の結果、判明した。そして、このようにして見積もられた下部電極２１の厚さ方向に沿った下部電極２１の側壁２１Ａの長さＬ₁に加え、リソグラフィー技術の合わせ精度を考慮して決定した長さＬ₁（実施の形態１においては、０．２２μｍ）を適用して実施の形態１のとおり不揮発性メモリを製造し、下部電極２１とコンタクトプラグ１８Ａとの間のコンタクト抵抗を測定したところ、上述のように酸化による導通不良のない信頼性の高い台座型電極構造を得ることができた。
【００９６】
（実施の形態２）
実施の形態２は実施の形態１の変形である。実施の形態１においては、拡散バリア層２０は、コンタクトプラグ１８Ａの頂面から層間絶縁層１６上に亙って形成されている。一方、実施の形態２においては、図６に模式的な一部断面図を示すように、拡散バリア層２０Ａは、コンタクトプラグ１８Ａの頂面にのみ形成されている。そして、下部電極２１の側壁は酸素バリア層３０で被覆されている。これらの点を除き、実施の形態２の不揮発性メモリは、実施の形態１にて説明した不揮発性メモリと同じ構造を有しているので、詳細な説明は省略する。
【００９７】
実施の形態２の不揮発性メモリは、以下の方法で製造することができる。即ち、実施の形態１の［工程−１２０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂを形成した後、コンタクトプラグ１８Ａ、接続孔１８ＢのＲＩＥ法に基づくエッチバックを行うことで、開口部１７Ａ，１７Ｂ内のコンタクトプラグ１８Ａ、接続孔１８Ｂの頂部を除去する。次いで、実施の形態１の［工程−１３０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂの頂面から層間絶縁層１６上に亙って、ＴｉＮから成る拡散バリア層２０を形成した後、層間絶縁層１６上の拡散バリア層２０を、例えばＣＭＰ法にて除去すればよい。
【００９８】
あるいは又、図７に模式的な一部断面図を示すように、拡散バリア層２０Ｂがコンタクトプラグ１８Ａの頂面から層間絶縁層１６上に亙って形成されており、拡散バリア層２０Ｂは下部電極２１で覆われている構造とすることもできる。この場合、拡散バリア層２０Ｂの平面形状と下部電極２１の平面形状とは異なり、下部電極２１の側壁は酸素バリア層３０で被覆されている。このような構造は、実施の形態１の［工程−１３０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂの頂面から層間絶縁層１６上に亙って、ＴｉＮから成る拡散バリア層２０Ｂを形成した後、拡散バリア層２０Ｂをパターニングし、次いで、全面に下部電極２１を形成した後、下部電極２１をパターニングすればよい。
【００９９】
（実施の形態３）
実施の形態３は、本発明の第２の態様及び第３の態様に係る不揮発性メモリ、及び、本発明の第２の態様に係る不揮発性メモリの製造方法に関する。
【０１００】
模式的な一部断面図を図８に示すように、実施の形態３の不揮発性メモリも、選択用トランジスタＴＲ、層間絶縁層１６、コンタクトプラグ１８Ａ、拡散バリア層２０、下部電極２１、強誘電体層２２、上部電極２３から構成されている。ここで、選択用トランジスタＴＲはシリコン半導体基板から成る半導体基板１０に形成されており、ＳｉＯ₂から成る層間絶縁層１６は選択用トランジスタＴＲを含む全面を覆っている。また、タングステンから構成されたコンタクトプラグ１８Ａは、層間絶縁層１６に形成された開口部１７Ａ内に設けられ、選択用トランジスタＴＲの一方のソース／ドレイン領域１５Ａに接続されている。ＴｉＮから成る拡散バリア層２０は、少なくともコンタクトプラグ１８Ａの頂面に、より具体的には、コンタクトプラグ１８Ａの頂面から層間絶縁層１６上に亙って形成されており、しかも、パターニングされている。更には、酸素拡散防止能を有する導電性材料（より具体的にはＩｒ／Ｉｒ−Ｈｆ）から成る下部電極２１は、拡散バリア層２０上に形成され、しかも、拡散バリア層２０と略同形にパターニングされている。ＳＢＴから成る強誘電体層２２は下部電極２１上に形成されており、白金（Ｐｔ）から成る上部電極２３は強誘電体層２２上に形成されている。
【０１０１】
そして、下部電極２１の側壁、より具体的には、下部電極２１及び拡散バリア層２０の側壁は、Ａｌ₂Ｏ₃から成る第１の酸素バリア層４０で被覆されており、この第１の酸素バリア層４０は層間絶縁層１６上を延在している。更には、図示していないが、この第１の酸素バリア層４０は、合わせマーク及び／又は周辺回路を覆っている。また、下部電極２１の下端部と層間絶縁層１６の表面との近傍に位置する第１の酸素バリア層４０の部分の上には、第２の酸素バリア層４１が形成されている。
【０１０２】
更には、下部電極２１が形成されていない層間絶縁層１６の部分には、絶縁膜３１が形成されている。
【０１０３】
また、開口部１７Ａの上端部から下部電極２１の側壁の下端部までの水平方向最短距離をＬ₀、下部電極２１の厚さ方向に沿った下部電極２１の側壁の長さをＬ₁としたとき（図１の（Ｂ）参照）、Ｌ₁≧０．２５Ｌ₀を満足する。具体的には、Ｌ₀＝０．４μｍ、Ｌ₁＝０．２２μｍである。尚、Ｌ₁≧０．２５Ｌ₀の関係は、不揮発性メモリの大きさ（セルサイズ）によって変化し得る。
【０１０４】
以下、半導体基板等の模式的な一部断面図である図９を参照して、実施の形態３の不揮発性メモリの製造方法を説明する。
【０１０５】
［工程−３００］
先ず、実施の形態１の［工程−１００］と同様にして、選択用トランジスタＴＲとして機能するＭＯＳ型トランジスタをシリコン半導体基板から成る半導体基板１０に形成する。次いで、実施の形態１の［工程−１１０］と同様にして、全面に層間絶縁層１６を形成する。その後、実施の形態１の［工程−１２０］と同様に、コンタクトプラグ１８Ａ、接続孔１８Ｂを開口部１７Ａ，１７Ｂ内に形成する。
【０１０６】
［工程−３１０］
次に、実施の形態１の［工程−１３０］と同様に、少なくともコンタクトプラグ１８Ａ、接続孔１８Ｂの頂面に、より具体的には、コンタクトプラグ１８Ａ、接続孔１８Ｂの頂面から層間絶縁層１６上に亙って、ＴｉＮから成り、パターニングされた拡散バリア層２０と、パターニングされた下部電極２１との積層構造を形成する。尚、実施の形態１と同様に、下部電極２１及び拡散バリア層２０の緻密化と応力緩和のために、７００゜Ｃの窒素ガス雰囲気中で３０分の熱処理を施すことが好ましい。この温度は、強誘電体層２２の形成（結晶化）と同じ温度である。
【０１０７】
［工程−３２０］
その後、実施の形態１の［工程−１４０］と同様に、ＥＣＲスパッタリング法により厚さ５０ｎｍのＡｌ₂Ｏ₃から成る第１の酸素バリア層４０を全面に形成する。こうして、下部電極２１及び拡散バリア層２０の側壁を第１の酸素バリア層４０で被覆し、且つ、第１の酸素バリア層４０を層間絶縁層１６上を延在させる。尚、第１の酸素バリア層４０を選択的に除去して、層間絶縁層１６上には第１の酸素バリア層４０を残さなくともよい。
【０１０８】
［工程−３３０］
次に、段差被覆性に優れたプラズマＣＶＤ法により厚さ８０ｎｍのＳｉＮ層を全面に成膜する。その後、ＲＩＥ法によってＳｉＮ層のエッチバックを行い、下部電極２１の下端部と層間絶縁層１６の表面との近傍に位置する第１の酸素バリア層４０の部分（所謂シーム部）の上に、ＳｉＮから成り、サイドウオール状の第２の酸素バリア層４１を形成する。尚、第２の酸素バリア層４１を構成する材料は、酸素バリア性を有するのであれば他の材料でもよいが、第１の酸素バリア層４０のシーム部を補強する観点から、カバレッジの良い成膜方法を用いることが好ましい。こうして、図９の（Ａ）に示す構造を得ることができる。
【０１０９】
［工程−３４０］
次いで、実施の形態１の［工程−１５０］と同様に、第１の酸素バリア層４０上に絶縁膜３１を形成する。そして、ＣＭＰ法によって平坦化処理を行い、その後、絶縁膜３１、第１の酸素バリア層４０及び第２の酸素バリア層４１の緻密化と応力緩和のために、７００゜Ｃの窒素ガス雰囲気中で３０分の熱処理を施すことが好ましい。尚、この温度は、強誘電体層２２の形成（結晶化）と同じ温度である。その後、下部電極２１を構成する材料と選択比のある条件を用いたエッチバック法に基づき、下部電極２１上の絶縁膜３１及び第１の酸素バリア層４０を除去し、図９の（Ｂ）に示す台座型電極構造を得ることができる。尚、図面においては、絶縁膜３１を１層で表した。
【０１１０】
［工程−３５０］
次いで、実施の形態１の［工程−１６０］〜［工程−１８０］と同様の工程を実行することによって、図８に示した不揮発性メモリを完成させる。
【０１１１】
尚、［工程−３３０］においてＳｉＮ層を全面に成膜し、ＳｉＮ層のエッチバックを行うことなく、［工程−３４０］においてＳｉＮ層上に絶縁膜３１を形成し、その後、ＣＭＰ法によって平坦化処理を行い、更に、絶縁膜３１、ＳｉＮ層、第１の酸素バリア層４０及び第２の酸素バリア層４１の緻密化と応力緩和のために、７００゜Ｃの窒素ガス雰囲気中で３０分の熱処理を施した後、下部電極２１を構成する材料と選択比のある条件を用いたエッチバック法に基づき、下部電極２１上の絶縁膜３１、ＳｉＮ層及び第１の酸素バリア層４０を除去して、下部電極２１の下端部と層間絶縁層１６の表面との近傍に位置する第１の酸素バリア層４０の部分（所謂シーム部）の上に、ＳｉＮから成る第２の酸素バリア層４１を形成してもよい。尚、この場合、第２の酸素バリア層４１は、層間絶縁層１６上を延在する第１の酸素バリア層４０上にも残される。
【０１１２】
実施の形態３にあっては、下部電極２１の下端部と層間絶縁層１６の表面との近傍（具体的には、例えばシーム部）に位置する第１の酸素バリア層４０の部分の上には第２の酸素バリア層４１が形成されているが故に、コンタクトプラグ１８Ａや拡散バリア層２０が酸化されることを確実に防止することができる。
【０１１３】
下部電極２１とコンタクトプラグ１８Ａとの間のコンタクト抵抗を公知のケルビン４端子法、及び、下部電極２１とコンタクトプラグ１８Ａとを直列に数十個〜数千個並べたコンタクトチェーンにより測定したところ、共に線型なＩ−Ｖ特性を示し、直径０．２５μｍのコンタクトプラグ１８Ａのコンタクト抵抗は約１８０Ωという値が得られ、実施の形態３のスタック型キャパシタ構造は十分な耐熱性・耐酸化性を有していることが明らかとなった。また、強誘電体層２２の残留分極も２Ｐ_r＝１８μＣ／ｃｍ²と良好な値を示した。
【０１１４】
（実施の形態４）
実施の形態４は実施の形態３の変形である。実施の形態３においては、拡散バリア層２０は、コンタクトプラグ１８Ａの頂面から層間絶縁層１６上に亙って形成されている。一方、実施の形態４においては、図１０に模式的な一部断面図を示すように、拡散バリア層２０Ａは、コンタクトプラグ１８Ａの頂面にのみ形成されている。そして、下部電極２１の側壁は酸素バリア層３０で被覆されている。これらの点を除き、実施の形態４の不揮発性メモリは、実施の形態３にて説明した不揮発性メモリと同じ構造を有しているので、詳細な説明は省略する。
【０１１５】
実施の形態４の不揮発性メモリは、以下の方法で製造することができる。即ち、実施の形態１の［工程−１２０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂを形成した後、コンタクトプラグ１８Ａ、接続孔１８ＢのＲＩＥ法に基づくエッチバックを行うことで、開口部１７Ａ，１７Ｂ内のコンタクトプラグ１８Ａ、接続孔１８Ｂの頂部を除去する。次いで、実施の形態１の［工程−１３０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂの頂面から層間絶縁層１６上に亙って、ＴｉＮから成る拡散バリア層２０を形成した後、層間絶縁層１６上の拡散バリア層２０を、例えばＣＭＰ法にて除去すればよい。
【０１１６】
あるいは又、図１１に模式的な一部断面図を示すように、拡散バリア層２０Ｂがコンタクトプラグ１８Ａの頂面から層間絶縁層１６上に亙って形成されており、拡散バリア層２０Ｂは下部電極２１で覆われている構造とすることもできる。この場合、拡散バリア層２０Ｂの平面形状と下部電極２１の平面形状とは異なり、下部電極２１の側壁は第１の酸素バリア層４０で被覆されている。このような構造は、実施の形態１の［工程−１３０］と同様の工程において、コンタクトプラグ１８Ａ、接続孔１８Ｂの頂面から層間絶縁層１６上に亙って、ＴｉＮから成る拡散バリア層２０Ｂを形成した後、拡散バリア層２０Ｂをパターニングし、次いで、全面に下部電極２１を形成した後、下部電極２１をパターニングすればよい。
【０１１７】
以上、本発明を、発明の実施の形態に基づき説明したが、本発明はこれらに限定されるものではない。発明の実施の形態にて説明した不揮発性メモリの構造、使用した材料、各種の形成条件等は例示であり、適宜変更することができる。例えば、場合によっては、プレート線の形成を省略し、上部電極がプレート線を兼ねる構成とすることができる。
【０１１８】
本発明における強誘電体層をＢａＴｉＯ₃（チタン酸バリウム）や、ＳｒＴｉＯ₃（チタン酸ストロンチウム）、（Ｂａ，Ｓｒ）ＴｉＯ₃（チタン酸バリウムストロンチウム）等の高誘電体材料から成る高誘電体層と置き換えれば、ＤＲＡＭ及びその製造方法に適用することが可能である。また、また、本発明の強誘電体型不揮発性半導体メモリをＤＲＡＭに適用することもできる。この場合には、強誘電体層の分極を、分極反転の起きない付加電圧の範囲で利用する。即ち、外部電界による最大（飽和）分極Ｐ_maxと外部電界が０の場合の残留分極Ｐ_rとの差（Ｐ_max−Ｐ_r）が、電源電圧に対して一定の関係（ほぼ比例する関係）を有する特性を利用する。強誘電体層の分極状態は、常に飽和分極（Ｐ_max）と残留分極（Ｐ_r）の間にあり、反転しない。データはリフレッシュによって保持される。
【０１１９】
【発明の効果】
本発明の第１の態様に係る強誘電体型不揮発性半導体メモリ及びその製造方法にあっては、下部電極の側壁（場合によっては、加えて、拡散バリア層の側壁）は酸素バリア層で被覆されており、この酸素バリア層は層間絶縁層上を延在しているが故に、コンタクトプラグが酸化されることを確実に防止することができると共に、各種の周辺回路及び／又は合わせマークが酸化されることを確実に防止することができる。また、本発明の第２の態様に係る強誘電体型不揮発性半導体メモリ及びその製造方法にあっては、下部電極下端部と層間絶縁層表面との近傍に位置する第１の酸素バリア層の部分の上には第２の酸素バリア層が形成されているが故に、たとえ、下部電極下端部と層間絶縁層表面との近傍に位置する第１の酸素バリア層の部分にシーム部が生成したとしても、このシーム部は第２の酸素バリア層によって被覆されているが故に、コンタクトプラグや拡散バリア層が酸化されることを確実に防止することができる。更には、本発明の第３の態様に係る強誘電体型不揮発性半導体メモリにおいては、Ｌ₁≧０．２５Ｌ₀を満足するが故に、下部電極の側壁と酸素バリア層との間から酸素が侵入してきた場合であっても、酸素がコンタクトプラグまで到達することがなく、コンタクトプラグが酸化されることを確実に防止することができる。そして、本発明にあっては、スタック型キャパシタ構造におけるコンタクトプラグに導通不良が発生したり、下部電極とコンタクトプラグとの間の密着低下、下部電極と拡散バリア層との間の密着低下、層間絶縁層と拡散バリア層との間の密着低下といった問題が生じることが無く、高い信頼性を有する強誘電体型不揮発性半導体メモリを得ることができる。
【図面の簡単な説明】
【図１】図１の（Ａ）は、発明の実施の形態１の強誘電体型不揮発性半導体メモリの模式的な一部断面図であり、図１の（Ｂ）は、拡散バリア層、下部電極、コンタクトプラグ等の部分的な拡大図である。
【図２】図２の（Ａ）及び（Ｂ）は、発明の実施の形態１の強誘電体型不揮発性半導体メモリの製造方法を説明するための、半導体基板等の模式的な一部断面図である。
【図３】図３の（Ａ）及び（Ｂ）は、図２の（Ｂ）に引き続き、発明の実施の形態１の強誘電体型不揮発性半導体メモリの製造方法を説明するための、半導体基板等の模式的な一部断面図である。
【図４】図４は、図３の（Ｂ）に引き続き、発明の実施の形態１の強誘電体型不揮発性半導体メモリの製造方法を説明するための、半導体基板等の模式的な一部断面図である。
【図５】図５の（Ａ）は、強誘電体層を形成した後の拡散バリア層の酸化状態を模式的に示す図であり、図５の（Ｂ）は、下部電極の厚さ方向に沿った下部電極の側壁の長さＬ₁と、酸化された拡散バリア層の領域の拡散バリア層の側壁からの距離Ｌの関係を模式的に示すグラフである。
【図６】図６は、発明の実施の形態２の強誘電体型不揮発性半導体メモリの模式的な一部断面図である。
【図７】図７は、発明の実施の形態２の強誘電体型不揮発性半導体メモリの変形例の模式的な一部断面図である。
【図８】図８は、発明の実施の形態３の強誘電体型不揮発性半導体メモリの模式的な一部断面図である。
【図９】図９の（Ａ）及び（Ｂ）は、発明の実施の形態１の強誘電体型不揮発性半導体メモリの製造方法を説明するための、半導体基板等の模式的な一部断面図である。
【図１０】図１０は、発明の実施の形態４の強誘電体型不揮発性半導体メモリの模式的な一部断面図である。
【図１１】図１１は、発明の実施の形態４の強誘電体型不揮発性半導体メモリの変形例の模式的な一部断面図である。
【図１２】図１２の（Ａ）は、従来の強誘電体型不揮発性半導体メモリの模式的な一部断面図であり、図１２の（Ｂ）は、従来の強誘電体型不揮発性半導体メモリにおける問題点を説明するための強誘電体型不揮発性半導体メモリの製造途中における模式的な一部断面図である。
【図１３】図１３の（Ａ）は、特開２００１−６０６７０に開示された強誘電体型不揮発性半導体メモリの模式的な一部断面図であり、図１３の（Ｂ）は、特開２００１−６０６７０に開示された強誘電体型不揮発性半導体メモリにおける問題点を説明するための強誘電体型不揮発性半導体メモリの製造途中における模式的な一部断面図である。
【図１４】図１４の（Ａ）は、強誘電体型不揮発性半導体メモリの等価回路図であり、図１４の（Ｂ）は、強誘電体のＰ−Ｅヒステリシスループを模式的に示す図である。
【符号の説明】
１０・・・シリコン半導体基板、１１・・・素子分離領域、１２・・・ゲート絶縁膜、１３・・・ゲート電極、１４・・・ゲートサイドウオール、１５Ａ，１５Ｂ・・・ソース／ドレイン領域、１６・・・層間絶縁層、１７Ａ，１７Ｂ・・・開口部、１８Ａ・・・コンタクトプラグ、１８Ｂ，１８Ｃ・・・接続孔、２０，２０Ａ，２０Ｂ・・・拡散バリア層、２１・・・下部電極、２２・・・強誘電体層、２３・・・上部電極、２４・・・絶縁層、３０・・・酸素バリア層、３１・・・絶縁膜、４０・・・第１の酸素バリア層、４１・・・第２の酸素バリア層、３１・・・絶縁膜、ＢＬ・・・ビット線、ＰＬ・・・プレート線[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric nonvolatile semiconductor memory also called a so-called FeRAM and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, semiconductor memory devices have been highly integrated, and accordingly, the area of the capacitor portion has been required to be reduced. However, in a semiconductor memory device represented by DRAM (Dynamic Random Access Memory), the SiO used conventionally as a capacitor material is used.₂And Si_ThreeN_FourSince the dielectric constant is low, it is becoming difficult to secure the capacitor capacity necessary for data storage as the area is reduced. In order to solve such problems, BaTiO_Three(Barium titanate) and (Ba, Sr) TiO_ThreeStudies using high dielectric materials such as (barium strontium titanate) as capacitor materials are underway.
[0003]
As a capacitor material, SrBi₂Ta₂O₉(Hereinafter sometimes referred to as SBT) or Pb (Zr, Ti) O_ThreeDevelopment of new semiconductor memory devices such as a ferroelectric nonvolatile semiconductor memory (FeRAM, Ferroelectric Random Access Memory) using a ferroelectric material such as PZT (hereinafter may be referred to as PZT) is also actively underway.
[0004]
FIG. 14A shows an equivalent circuit diagram of the ferroelectric nonvolatile semiconductor memory (hereinafter sometimes referred to as a nonvolatile memory). In FIG. 14A, two nonvolatile memories are illustrated. This non-volatile memory is a non-volatile memory that has a ferroelectric layer and can detect high-speed polarization reversal of the ferroelectric layer and changes in the amount of stored charge in the capacitor section using its remanent polarization. It is a memory, basically the capacitor part FC₁, FC₂And selection transistor TR₁, TR₂It consists of and. Then, the selection transistor TR₁, TR₂One source / drain region is the capacitor part FC₁, FC₂Is connected to one end of the capacitor FC₁, FC₂The other end of the plate wire PL₁, PL₂It is connected to the. The selection transistor TR₁, TR₂The other source / drain region is connected to the bit line BL, and the selection transistor TR₁, TR₂The gate electrode of the word line WL₁, WL₂It is connected to the.
[0005]
Data is written to or read from the nonvolatile memory by applying a ferroelectric PE hysteresis loop shown in FIG. That is, when an external electric field is applied after applying an external electric field to the ferroelectric layer, the ferroelectric layer exhibits residual polarization. Then, the remanent polarization of the ferroelectric layer is + P when an external electric field in the positive direction is applied._rWhen an external electric field in the negative direction is applied, -P_rIt becomes. Here, the remanent polarization is + P_rIn the case of the state (see “D” in FIG. 14B), the residual polarization is −P._rIn this state (see “A” in FIG. 14B), “1” is assumed.
[0006]
In order to determine the state of “1” or “0”, for example, an external electric field in the positive direction is applied to the ferroelectric layer. As a result, the polarization of the ferroelectric layer becomes the state “C” in FIG. At this time, if the data is “0”, the polarization state of the ferroelectric layer changes from “D” to “C”. On the other hand, if the data is “1”, the polarization state of the ferroelectric layer changes from “A” to “C” via “B”. When the data is “0”, the polarization inversion of the ferroelectric layer does not occur. On the other hand, when the data is “1”, polarization inversion occurs in the ferroelectric layer. As a result, a difference occurs in the amount of charge stored in the capacitor portion. By turning on the selection transistor of the selected nonvolatile memory, this accumulated charge is detected as a signal current. When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric layer becomes the state of “D” in FIG. 14B regardless of whether the data is “0” or “1”. End up. That is, at the time of reading, the data “1” is once destroyed. Therefore, when the data is “1”, an external electric field in the negative direction is applied to make the state “A” along the paths “D” and “E”, and the data “1” is written again.
[0007]
In order to achieve high integration of these various semiconductor memory devices, a so-called stack type capacitor structure in which a selection transistor is covered with an interlayer insulating layer and a capacitor portion is formed on the interlayer insulating layer together with a reduction in cell area. Is required.
[0008]
In the conventional non-volatile memory, as shown in a schematic partial cross-sectional view in FIG. 12A, the capacitor portion specifically includes a lower electrode 21 and a ferroelectric formed thereon. The layer 22 includes an upper electrode 23 formed on the ferroelectric layer 22. The lower electrode 21 is formed on the interlayer insulating layer 16, and a diffusion barrier layer 20 is formed between the lower electrode 21 and the interlayer insulating layer 16. Further, a contact plug 18A is formed in the interlayer insulating layer 16 in order to connect one source / drain region 15A of the selection transistor and the lower electrode 21. The contact plug 18A is usually made of a conductive material such as polycrystalline silicon or tungsten. In FIG. 12A, reference numeral 24 is an insulating layer, reference numeral 10 is a semiconductor substrate, reference numeral 11 is an element isolation region, reference numeral 12 is a gate insulating film, reference numeral 13 is a gate electrode, reference numeral 14. Is a gate sidewall, reference numeral 15B is the other source / drain region, reference numeral 18D is a connection hole connecting the bit line BL and the other source / drain region 15B, and reference numeral WL is a word line.
[0009]
By the way, the above-described high-dielectric material and ferroelectric material are mainly oxides, and for example, heat treatment in a high-temperature oxygen gas atmosphere is required for crystallization of the ferroelectric layer 22.
[0010]
When the mutual diffusion of the atoms of the material constituting the lower electrode 21 and the atoms of the material constituting the contact plug 18A occurs due to such heat treatment, the characteristics and reliability of the nonvolatile memory are deteriorated. Therefore, in order to suppress mutual diffusion, a diffusion barrier layer 20 made of TiN, TaN, or TiAlN is provided. Further, in such a heat treatment, when oxygen reaches the contact plug 18A through the lower electrode 21, there is a problem that the portion of the contact plug 18A near the boundary region between the lower electrode 21 and the contact plug 18A is oxidized and becomes non-conductive. There arises a problem that the adhesion between the lower electrode 21 and the contact plug 18A is lowered. Furthermore, the above-described materials constituting the diffusion barrier layer 20 also lose the conductivity when oxidized, decrease in adhesion between the lower electrode 21 and the diffusion barrier layer 20, the interlayer insulating layer 16 and the diffusion barrier. There arises a problem that the adhesion between the layer 20 is lowered.
[0011]
Therefore, the lower electrode 21 needs to be made of a material that is stable even in a high-temperature oxygen gas atmosphere and has an oxygen barrier property, and is generally Ir or IrO.₂Noble metal materials such as are used. From such a background, when a high dielectric material or a ferroelectric material is applied to the stacked capacitor structure, a laminated structure in which the lower electrode 21 having an oxygen barrier property and the diffusion barrier layer 20 are combined is adopted. There are many.
[0012]
Further, as a method for increasing the degree of integration of the semiconductor memory device, it is possible to eliminate as much as possible the alignment margin of each layer in the photolithography process. This is because the ferroelectric layer 22 is formed on the previously patterned lower electrode 21. It becomes possible by adopting a so-called pedestal type (pedestal type) electrode structure. This pedestal-type electrode structure formation process is a process that leads to a three-dimensional capacitor structure performed in a DRAM or the like in order to secure the amount of charge accumulated in the capacitor portion when the semiconductor memory device is further miniaturized. is there.
[0013]
For the reasons described above, it is effective to adopt a stack type capacitor structure having a pedestal type electrode structure in order to promote high integration of the semiconductor memory device.
[0014]
Conventionally, in the formation of a capacitor portion using a pedestal electrode structure, after forming the lower electrode 21, the gap between the lower electrodes 21 is reduced to SiO.₂The ferroelectric layer 22 is formed on the lower electrode 21 after being flattened by being filled with an insulating film 31 such as the like.
[0015]
[Problems to be solved by the invention]
However, when the above-mentioned pedestal electrode structure is applied to a stack type capacitor structure using a capacitor material that needs to be crystallized in a high-temperature oxygen gas atmosphere such as BST, PZT, or SBT, it is shown in FIG. As described above, when the ferroelectric layer 22 is crystallized in the high-temperature oxygen gas atmosphere, oxygen enters from between the insulating film 31 and the lower electrode 21, and the side wall of the diffusion barrier layer 20 is oxidized. Furthermore, oxygen that has penetrated into the diffusion barrier layer 20 reaches the contact plug 18A, the contact plug 18A is oxidized, and there is a problem that conduction between the selection transistor and the lower electrode 21 cannot be achieved. The oxidized portion of the contact plug 18A is indicated by reference numeral 18a.
[0016]
Therefore, for example, as disclosed in Japanese Patent Laid-Open No. 2001-60670, a sidewall 100 made of a metal oxide 100A having an oxygen barrier property such as aluminum oxide, zirconium oxide, iridium oxide, rhodium oxide, and ruthenium oxide is formed on the lower electrode 21. Attempts have been made to prevent the contact plug 18A from being oxidized by being disposed on the side wall of the diffusion barrier layer 20. A schematic partial sectional view of such a structure is shown in FIG.
[0017]
However, even if such a sidewall is disposed on the side wall of the pedestal electrode structure, when the metal oxide 100A is formed by sputtering, a schematic partial cross-sectional view is shown in FIG. As shown, a seam portion 100B is formed in a portion of the metal oxide 100A located in the vicinity of the lower end portion of the diffusion barrier layer 20 and the surface of the interlayer insulating layer 16, and the seam 100 is finally formed on the side wall 100 that is finally obtained. The portion 100B remains and oxygen enters from the seam portion 100B. As a result, the diffusion barrier layer 20 and the contact plug 18A are oxidized.
[0018]
In addition, when manufacturing the nonvolatile memory, not only the selection transistor and the capacitor part but also various peripheral circuits are formed. When the ferroelectric layer 22 is crystallized in a high-temperature oxygen gas atmosphere, the peripheral circuit is configured. The material to be oxidized may be oxidized. Further, at the time of manufacturing the non-volatile memory, an alignment mark is formed for alignment of the photomask. However, the alignment mark is oxidized when the ferroelectric layer 22 is crystallized in a high-temperature oxygen gas atmosphere. There is a possibility that the alignment mark disappears.
[0019]
Accordingly, a first object of the present invention is to have a stacked capacitor structure, which can reliably prevent the contact plug from being oxidized, and that various peripheral circuits and alignment marks are oxidized. An object of the present invention is to provide a ferroelectric-type nonvolatile semiconductor memory having a structure that can be surely prevented and a method for manufacturing the same.
[0020]
A second object of the present invention is to provide a ferroelectric nonvolatile semiconductor memory having a stacked capacitor structure and a structure capable of reliably preventing the contact plug from being oxidized, and a method for manufacturing the same. It is in.
[0021]
[Means for Solving the Problems]
In order to achieve the first object, a ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention includes:
(A) a selection transistor formed on a semiconductor substrate;
(B) an interlayer insulating layer covering the selection transistor;
(C) a contact plug provided in an opening formed in the interlayer insulating layer and connected to one source / drain region of the selection transistor;
(D) a diffusion barrier layer formed and patterned on at least the top surface of the contact plug;
(E) a patterned lower electrode formed on at least the diffusion barrier layer;
(F) a ferroelectric layer formed on the lower electrode, and
(G) an upper electrode formed on the ferroelectric layer;
A ferroelectric nonvolatile semiconductor memory comprising:
The side wall of the lower electrode is covered with an oxygen barrier layer, and the oxygen barrier layer extends over the interlayer insulating layer.
[0022]
In the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, the diffusion barrier layer may be formed only on the top surface of the contact plug, but the diffusion barrier layer is interlayer-insulated from the top surface of the contact plug. The diffusion barrier layer and the lower electrode have substantially the same planar shape, and the sidewalls of the lower electrode and the diffusion barrier layer are covered with an oxygen barrier layer. preferable. That is, when the diffusion barrier layer is formed only on the top surface of the contact plug, the diffusion barrier layer is covered with the lower electrode, and the planar shape of the diffusion barrier layer is different from the planar shape of the lower electrode. The sidewall is covered with an oxygen barrier layer. On the other hand, when the diffusion barrier layer is formed over the interlayer insulating layer from the top surface of the contact plug, the diffusion barrier layer may be covered with the lower electrode (in this case, the plane of the diffusion barrier layer). Unlike the planar shape of the lower electrode and the planar shape of the lower electrode, the side wall of the lower electrode is covered with an oxygen barrier layer), and the planar shape of the diffusion barrier layer and the planar shape of the lower electrode substantially coincide with each other. In some cases, the side wall is covered with an oxygen barrier layer.
[0023]
In the manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention or the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention described later, the side wall ( In some cases, in addition, the sidewalls of the diffusion barrier layer are covered with an oxygen barrier layer, and this oxygen barrier layer extends over the interlayer insulating layer, thus ensuring that the contact plug is oxidized. In addition, various peripheral circuits and / or alignment marks can be reliably prevented from being oxidized.
[0024]
In order to achieve the second object, a ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention includes:
(A) a selection transistor formed on a semiconductor substrate;
(B) an interlayer insulating layer covering the selection transistor;
(C) a contact plug provided in an opening formed in the interlayer insulating layer and connected to one source / drain region of the selection transistor;
(D) a diffusion barrier layer formed and patterned on at least the top surface of the contact plug;
(E) a patterned lower electrode formed on at least the diffusion barrier layer;
(F) a ferroelectric layer formed on the lower electrode, and
(G) an upper electrode formed on the ferroelectric layer;
A ferroelectric nonvolatile semiconductor memory comprising:
The side wall of the lower electrode is covered with a first oxygen barrier layer,
A second oxygen barrier layer is formed on a portion of the first oxygen barrier layer located in the vicinity of the lower end portion of the lower electrode and the surface of the interlayer insulating layer.
[0025]
In the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention, the diffusion barrier layer may be formed only on the top surface of the contact plug, but the diffusion barrier layer is interlayer-insulated from the top surface of the contact plug. The diffusion barrier layer and the lower electrode have substantially the same planar shape, and the side walls of the lower electrode and the diffusion barrier layer are covered with the first oxygen barrier layer. It is preferable to do. That is, when the diffusion barrier layer is formed only on the top surface of the contact plug, the diffusion barrier layer is covered with the lower electrode, and the planar shape of the diffusion barrier layer is different from the planar shape of the lower electrode. The sidewall is covered with a first oxygen barrier layer. On the other hand, when the diffusion barrier layer is formed over the interlayer insulating layer from the top surface of the contact plug, the diffusion barrier layer may be covered with the lower electrode (in this case, the plane of the diffusion barrier layer). Unlike the planar shape of the lower electrode and the planar shape of the lower electrode, the side wall of the lower electrode is covered with the first oxygen barrier layer), the planar shape of the diffusion barrier layer and the planar shape of the lower electrode substantially coincide, The side wall of the diffusion barrier layer may be covered with the first oxygen barrier layer.
[0026]
In the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention, the first oxygen barrier layer may extend on the interlayer insulating layer.
[0027]
In the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention or the method for manufacturing the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention described later, the lower electrode lower end portion and the interlayer insulation Since the second oxygen barrier layer is formed on the portion of the first oxygen barrier layer located in the vicinity of the layer surface, even if it is in the vicinity of the lower electrode lower end portion and the interlayer insulating layer surface. Even if a seam portion is formed in the portion of the first oxygen barrier layer that is positioned, it is ensured that the contact plug and the diffusion barrier layer are oxidized because the seam portion is covered with the second oxygen barrier layer. Can be prevented.
[0028]
In order to achieve the second object, a ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention includes:
(A) a selection transistor formed on a semiconductor substrate;
(B) an interlayer insulating layer covering the selection transistor;
(C) a contact plug provided in an opening formed in the interlayer insulating layer and connected to one source / drain region of the selection transistor;
(D) a diffusion barrier layer formed and patterned on at least the top surface of the contact plug;
(E) a patterned lower electrode formed on at least the diffusion barrier layer;
(F) a ferroelectric layer formed on the lower electrode, and
(G) an upper electrode formed on the ferroelectric layer;
A ferroelectric nonvolatile semiconductor memory comprising:
The side wall of the lower electrode is covered with an oxygen barrier layer,
The shortest horizontal distance from the upper end of the opening to the lower end of the lower electrode side wall is L₀, The length of the side wall of the lower electrode along the thickness direction of the lower electrode is L₁L₁≧ 0.25L₀It is characterized by satisfying.
[0029]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, L₁≧ 0.5L₀It is desirable to satisfy Alternatively, L₁≧ 5 × 10^-8m, preferably L₁≧ 1 × 10^-7It is desirable to satisfy m.
[0030]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, the diffusion barrier layer may be formed only on the top surface of the contact plug, but the diffusion barrier layer is interlayer-insulated from the top surface of the contact plug. The diffusion barrier layer and the lower electrode have substantially the same planar shape, and the sidewalls of the lower electrode and the diffusion barrier layer are covered with an oxygen barrier layer. preferable. That is, when the diffusion barrier layer is formed only on the top surface of the contact plug, the diffusion barrier layer is covered with the lower electrode, and the planar shape of the diffusion barrier layer is different from the planar shape of the lower electrode. The sidewall is covered with an oxygen barrier layer. On the other hand, when the diffusion barrier layer is formed over the interlayer insulating layer from the top surface of the contact plug, the diffusion barrier layer may be covered with the lower electrode (in this case, the plane of the diffusion barrier layer). Unlike the planar shape of the lower electrode and the planar shape of the lower electrode, the side wall of the lower electrode is covered with an oxygen barrier layer), and the planar shape of the diffusion barrier layer and the planar shape of the lower electrode substantially coincide with each other. In some cases, the side wall is covered with an oxygen barrier layer.
[0031]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, the oxygen barrier layer may extend on the interlayer insulating layer. Alternatively, the second oxygen barrier layer may be formed on the oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. In addition, the oxygen barrier layer may be configured to extend on the interlayer insulating layer.
[0032]
In the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, L₁≧ 0.25L₀Therefore, from between the side wall of the lower electrode and the oxygen barrier layer (in some cases, between the side wall of the diffusion barrier layer and the oxygen barrier layer, or alternatively, via the diffusion barrier layer) ) Even when oxygen enters, oxygen does not reach the contact plug, and the contact plug can be reliably prevented from being oxidized.
[0033]
In the ferroelectric nonvolatile semiconductor memory according to the first to third aspects of the present invention, an insulating film may be formed in a portion of the interlayer insulating layer where the lower electrode is not formed. From the viewpoint that a ferroelectric layer can be formed on a flat surface. As a material constituting the insulating film, silicon oxide (SiO₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG, or LTO.
[0034]
A method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention for achieving the first object is as follows.
(A) forming a selection transistor on a semiconductor substrate;
(B) forming an interlayer insulating layer on the entire surface;
(C) after forming an opening in the interlayer insulating layer, forming a contact plug connected to one source / drain region of the selection transistor in the opening;
(D) forming a laminated structure of a patterned diffusion barrier layer and a patterned lower electrode on at least the top surface of the contact plug;
(E) covering the side wall of the lower electrode with an oxygen barrier layer and extending the oxygen barrier layer over the interlayer insulating layer;
(F) forming a ferroelectric layer on the lower electrode;
(G) forming an upper electrode on the ferroelectric layer;
It is characterized by comprising.
[0035]
Here, in the step (d), after the patterned diffusion barrier layer is formed, the patterned lower electrode may be formed on the diffusion barrier layer, or after the diffusion barrier layer is formed, the diffusion barrier layer is formed. The lower electrode may be formed on the upper electrode, and then the lower electrode and the diffusion barrier layer may be patterned. Both forms are included in the method for manufacturing the ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention. .
[0036]
In the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, in the step (d), a diffusion barrier layer is formed from the top surface of the contact plug over the interlayer insulating layer, Further, the diffusion barrier layer and the lower electrode may have a laminated structure having substantially the same planar shape, and in the step (e), the side walls of the lower electrode and the diffusion barrier layer may be covered with the oxygen barrier layer. preferable. In this case, in the step (e), an oxygen barrier layer is formed on the entire surface, then an insulating film is formed on the oxygen barrier layer, and then the insulating film and the oxygen barrier layer on the lower electrode are removed. It is desirable from the viewpoint of forming the ferroelectric layer on a flat surface. Furthermore, the insulating film is made of silicon oxide (SiO 2₂And is preferably formed by a high density plasma CVD method (HDP-CVD method), and after forming an insulating film on the entire surface, in order to expose the top surface of the lower electrode, insulation on the lower electrode Before the film and the oxygen barrier layer are removed, the insulating film and the oxygen barrier layer are subjected to heat treatment at substantially the same temperature as the formation of the ferroelectric layer in the step (f). It is preferable from the viewpoint of mitigating. The insulating film is made of silicon oxide (SiO₂), But may be composed of silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG or LTO.
[0037]
Further, between the step (d) and the step (e), the lower electrode and the diffusion barrier layer may be heat-treated at substantially the same temperature as the formation of the ferroelectric layer in the step (f). This is preferable from the viewpoint of relieving stress due to the diffusion barrier layer. Alternatively, in the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, the ferroelectric layer in the step (f) is interposed between the step (e) and the step (f). It is preferable to heat-treat the oxygen barrier layer at substantially the same temperature as the formation from the viewpoint of relieving stress due to the oxygen barrier layer.
[0038]
In the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the first aspect of the present invention, the oxygen barrier layer is formed by ECR sputtering in order to form an oxygen barrier layer having a dense film quality, although not limited thereto. Or it is preferable to form by an atomic layer deposition (ALD) method.
[0039]
A method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention for achieving the second object is as follows.
(A) forming a selection transistor on a semiconductor substrate;
(B) forming an interlayer insulating layer on the entire surface;
(C) after forming an opening in the interlayer insulating layer, forming a contact plug connected to one source / drain region of the selection transistor in the opening;
(D) forming a laminated structure of a patterned diffusion barrier layer and a patterned lower electrode on at least the top surface of the contact plug;
(E) The side wall of the lower electrode is covered with the first oxygen barrier layer, and the second oxygen barrier layer is formed on the portion of the first oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. Forming an oxygen barrier layer of
(F) forming a ferroelectric layer on the lower electrode;
(G) forming an upper electrode on the ferroelectric layer;
It is characterized by comprising.
[0040]
Here, in the step (d), after the patterned diffusion barrier layer is formed, the patterned lower electrode may be formed on the diffusion barrier layer, or after the diffusion barrier layer is formed, the diffusion barrier layer is formed. The lower electrode may be formed on the upper electrode, and then the lower electrode and the diffusion barrier layer may be patterned. Both forms are included in the method for manufacturing the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention. .
[0041]
In the method of manufacturing a ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention, in the step (d), a diffusion barrier layer is formed from the top surface of the contact plug over the interlayer insulating layer, Further, the diffusion barrier layer and the lower electrode form a laminated structure having substantially the same planar shape, and in the step (e), the sidewalls of the lower electrode and the diffusion barrier layer are covered with the first oxygen barrier layer; It is preferable to do. In this case, after forming the first oxygen barrier layer on the entire surface, the step (e) is performed on the portion of the first oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. And forming a second oxygen barrier layer on the entire surface, then forming an insulating film on the entire surface, and then removing the insulating film on the lower electrode and the first oxygen barrier layer. It is preferable from the viewpoint of forming on the surface. Through such a process, the first oxygen barrier layer extends on the interlayer insulating layer. Here, the insulating film is silicon oxide (SiO₂And is preferably formed by a high-density plasma CVD method (HDP-CVD method). In addition, after forming the insulating film on the entire surface, the insulating film and the first oxygen barrier layer on the lower electrode are removed in order to expose the top surface of the lower electrode, but before that, in the step (f) It is preferable to heat-treat the insulating film, the first oxygen barrier layer, and the second oxygen barrier layer at substantially the same temperature as the formation of the ferroelectric layer from the viewpoint of reducing stress caused by the insulating film. The insulating film is made of silicon oxide (SiO₂), But may be composed of silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG or LTO.
[0042]
In the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention, the ferroelectric layer is formed in the step (f) between the step (d) and the step (e). It is preferable to heat-treat the lower electrode and the diffusion barrier layer at substantially the same temperature as from the viewpoint of relieving stress caused by the lower electrode and the diffusion barrier layer.
[0043]
In the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention, the oxygen barrier layer is formed by ECR sputtering in order to form an oxygen barrier layer having a dense film quality, although not limited thereto. Or it is preferable to form by an atomic layer deposition (ALD) method.
[0044]
The ferroelectric-type nonvolatile semiconductor memory according to the first or third aspect of the present invention, or the oxygen barrier layer in the manufacturing method of the ferroelectric-type nonvolatile semiconductor memory according to the first aspect of the present invention, or The first oxygen barrier layer in the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention or the manufacturing method thereof is preferably made of a material having excellent adhesion to the lower electrode and the oxygen barrier layer. Specifically, Al₂O_Three, ZrO₂, HfO₂TiO_X, TaO_X, AlN and IrN_XPreferably it consists of at least one material selected from the group consisting of:
[0045]
In the ferroelectric nonvolatile semiconductor memory according to the second aspect of the present invention or the manufacturing method thereof, or in the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, the second oxygen barrier layer is made of SiN. However, the present invention is not limited to this. In short, it may be made of a material having an oxygen diffusion preventing ability. Note that the second oxygen barrier layer is desirably formed by a film forming method having excellent step coverage such as a CVD method.
[0046]
Ferroelectric nonvolatile semiconductor memory according to the first to third aspects of the present invention, or manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first to second aspects of the present invention (hereinafter referred to as the ferroelectric nonvolatile semiconductor memory) In these cases, the ferroelectric layer is formed on the lower electrode, but the ferroelectric layer may extend over the oxygen barrier layer. In some cases, it may further extend on the insulating film.
[0047]
In the present invention, the lower electrode is preferably made of a conductive material having oxygen diffusion preventing ability, specifically, at least one noble metal selected from the group consisting of Ir, Ru, Rh, Pd, and Pt, Or it is preferable to consist of the compound or the laminated structure of these noble metals or compounds. The upper electrode is also preferably composed of at least one kind of noble metal selected from the group consisting of Ir, Ru, Rh, Pd, and Pt, or a compound thereof, or a laminated structure of these noble metals or compounds. More specifically, for example, Ir, IrO as a material constituting the lower electrode or the upper electrode_2-X, IrO_2-X/ Ir, SrIrO_Three, Ir / Ir-Hf, Ru, RuO_2-X, SrRuO_Three, Pt, Pt / IrO_2-X, Pt / RuO_2-X, Pd, Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La_0.5Sr_0.5CoO_Three(LSCO), Pt / LSCO laminated structure, YBa₂Cu_ThreeO₇Can be mentioned. Here, the value of X is 0 ≦ X <2. In the laminated structure, the material described before “/” is in contact with the ferroelectric layer. The lower electrode and the upper electrode may be made of the same material, may be made of the same material, or may be made of different materials. In order to form the lower electrode or the upper electrode, the conductive material layer may be patterned in a step after forming the conductive material layer constituting the lower electrode or the conductive material layer constituting the upper electrode. The conductive material layer can be appropriately formed by a method suitable for the material forming the conductive material layer, such as sputtering, reactive sputtering, electron beam evaporation, MOCVD, or pulsed laser ablation. The patterning of the conductive material layer can be performed by, for example, an ion milling method or an RIE method. The lower electrode may have a so-called damascene structure. In other words, the insulating material layer may have a structure surrounding the lower electrode formed on the interlayer insulating layer.
[0048]
In the present invention, examples of the material constituting the diffusion barrier layer include TiN, TaN, and TiAlN.
[0049]
In the method for manufacturing a ferroelectric nonvolatile semiconductor memory according to the first or second aspect of the present invention, the diffusion barrier layer is etched by etching the lower electrode and the diffusion barrier layer in the step (d). In the case of forming a laminated structure with the lower electrode, it is preferable to perform etching under the condition that the diffusion barrier layer is not side-etched. When the diffusion barrier layer is side-etched, it may be difficult to cover the side-etched portion of the diffusion barrier layer with the oxygen barrier layer or the first oxygen barrier layer. Such etching is performed by, for example, Cl.₂Etching gas mainly containing / Ar may be used.
[0050]
Examples of the material constituting the ferroelectric layer in the present invention include a bismuth layered compound, more specifically, a Bi-based layered structure perovskite type ferroelectric material. Bi-based layered structure perovskite type ferroelectric materials belong to so-called non-stoichiometric compounds and are tolerant of compositional shifts at both sites of metal elements and anion (O, etc.) elements. It is also not uncommon for optimal electrical characteristics to be exhibited at a slight deviation from the stoichiometric composition. Bi-based layered structure perovskite type ferroelectric materials include, for example, the general formula₂O₂)²⁺(A_m-1B_mO_{3m + 1})^2-Can be expressed as Here, “A” represents one type of metal selected from the group consisting of metals such as Bi, Pb, Ba, Sr, Ca, Na, K, and Cd, and “B” represents Ti, Nb. , Ta, W, Mo, Fe, Co, Cr, and one type selected from the group consisting of a plurality of types, or a combination based on an arbitrary ratio. M is an integer of 1 or more.
[0051]
Alternatively, the material constituting the ferroelectric layer is
(Bi_X, Sr_1-X)₂(Sr_Y, Bi_1-Y) (Ta_Z, Nb_1-Z)₂O_d  Formula (1)
(However, 0.9 ≦ X ≦ 1.0, 0.7 ≦ Y ≦ 1.0, 0 ≦ Z ≦ 1.0, 8.7 ≦ d ≦ 9.3) It is preferable to include as a phase. Alternatively, the material constituting the ferroelectric layer is
Bi_XSr_YTa₂O_d  Formula (2)
However, it is preferable that a crystal phase represented by (X + Y = 3, 0.7 ≦ Y ≦ 1.3, 8.7 ≦ d ≦ 9.3) is included as a main crystal phase. In these cases, it is more preferable that 85% or more of the crystal phase represented by the formula (1) or (2) is contained as the main crystal phase. In formula (1), (Bi_X, Sr_1-X) Means that Sr occupies the site originally occupied by Bi in the crystal structure, and the ratio of Bi and Sr at this time is X: (1-X). Also, (Sr_Y, Bi_1-Y) Means that Bi occupies the site originally occupied by Sr in the crystal structure, and the ratio of Sr and Bi at this time is Y: (1-Y). The material constituting the ferroelectric layer including the crystal phase represented by the formula (1) or (2) as the main crystal phase includes Bi oxide, Ta and Nb oxide, Bi, Ta and Nb. There may be some composite oxides.
[0052]
Alternatively, the material constituting the ferroelectric layer is
Bi_X(Sr, Ca, Ba)_Y(Ta_Z, Nb_1-Z)₂O_d  Formula (3)
(However, the crystal phase represented by 1.7 ≦ X ≦ 2.5, 0.6 ≦ Y ≦ 1.2, 0 ≦ Z ≦ 1.0, 8.0 ≦ d ≦ 10.0) is included. May be. “(Sr, Ca, Ba)” means one type of element selected from the group consisting of Sr, Ca, and Ba. If the composition of the material constituting the ferroelectric layer represented by each of these formulas is expressed by the stoichiometric composition, for example, Bi₂SrTa₂O₉(Strontium bismuth tantalate), Bi₂SrNb₂O₉(Strontium bismuth niobate), Bi₂BaTa₂O₉(Barium bismuth tantalate), Bi₂BaNb₂O₉(Barium bismuth niobate), Bi₂Sr (Ta, Nb)₂O₉(Strontium bismuth tantalate niobate) and the like. Alternatively, as a ferroelectric material, Bi_FourSrTi_FourO₁₅(Strontium bismuth titanate), Bi_ThreeTiNbO₉(Bismuth titanium niobate), Bi_ThreeTiTaO₉(Bismuth titanium tantalate), Bi_FourTi_ThreeO₁₂(Bismuth titanate), (Bi, La)_FourTi_ThreeO₁₂(Lanthanum bismuth titanate), Bi₂PbTa₂O₉(Bismuth lead tantalate) and the like can be exemplified, but also in these cases, the ratio of each metal element can be changed to such an extent that the crystal structure does not change. That is, there may be a composition shift at both sites of the metal element and oxygen element.
[0053]
Alternatively, as a ferroelectric material, PbTiO_Three(Lead titanate), BaTiO_Three(Barium titanate), LiNbO_Three(Lithium niobate), LiTaO_Three(Lithium tantalate), YMnO_Three(Yttrium manganate), PbZrO having a perovskite structure_ThreeAnd PbTiO_ThreeZirconate titanate [PZT, Pb (Zr_1-y, Ti_y) O_Three(However, 0 <y <1)], PLZT [(Pb, La) (Zr, Ti) O which is a metal oxide obtained by adding La to PZT_Three(Lead lanthanum zirconate titanate)], or PNZT, which is a metal oxide obtained by adding Nb to PZT, and PSZT [(Pb, Sr) (Zr), which is a metal oxide obtained by adding strontium (Sr) to PZT._X, Ti_Y) O_ThreeAnd a mixture thereof.
[0054]
In the materials constituting the ferroelectric layer described above, the crystallization temperature can be changed by removing these compositions from the stoichiometric composition.
[0055]
In order to obtain the ferroelectric layer, the ferroelectric thin film may be patterned in the process after the ferroelectric thin film is formed. In some cases, patterning of the ferroelectric thin film is not necessary. The formation of the ferroelectric thin film is, for example, MOCVD, MOD (Metal Organic Decomposition) using bismuth organometallic compound having bismuth-oxygen bond (bismuth alkoxide compound), LSMCD (Liquid Source Mist Chemical Deposition), A method suitable for the material constituting the ferroelectric thin film, such as a pulse laser ablation method, a sputtering method, or a sol-gel method, can be used as appropriate. The patterning of the ferroelectric thin film can be performed by, for example, an anisotropic ion etching (RIE) method.
[0056]
The selection transistor can be constituted by, for example, a well-known MIS type FET or MOS type FET. The contact plug for connecting the selection transistor and the lower electrode can be formed by burying, for example, polysilicon doped with tungsten or impurities in the opening formed in the interlayer insulating layer. The interlayer insulating layer is made of, for example, silicon oxide (SiO₂), Silicon nitride (SiN), SiON, SOG, NSG, BPSG, PSG, BSG or LTO.
[0057]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on embodiments of the invention (hereinafter abbreviated as embodiments) with reference to the drawings.
[0058]
(Embodiment 1)
The first embodiment is a ferroelectric nonvolatile semiconductor memory (hereinafter abbreviated as a nonvolatile memory) according to the first and third aspects of the present invention, and the nonvolatile memory according to the first aspect of the present invention. The present invention relates to a method for manufacturing a memory.
[0059]
As shown in FIG. 1A, the nonvolatile memory of Embodiment 1 includes a selection transistor TR, an interlayer insulating layer 16, a contact plug 18A, a diffusion barrier layer 20, a lower electrode, as shown in FIG. 21, a ferroelectric layer 22, and an upper electrode 23. Here, the selection transistor TR is formed on the semiconductor substrate 10 made of a silicon semiconductor substrate, and SiO 2₂An interlayer insulating layer 16 made of is covering the entire surface including the selection transistor TR. The contact plug 18A made of tungsten is provided in an opening 17A formed in the interlayer insulating layer 16, and is connected to one source / drain region 15A of the selection transistor TR. The diffusion barrier layer 20 made of TiN is formed at least on the top surface of the contact plug 18A, more specifically, over the interlayer insulating layer 16 from the top surface of the contact plug 18A, and is patterned. Yes. Furthermore, the lower electrode 21 made of a conductive material (more specifically, Ir / Ir-Hf) having an oxygen diffusion preventing ability is formed on the diffusion barrier layer 20 and is substantially the same shape as the diffusion barrier layer 20. Patterned. The ferroelectric layer 22 made of SBT is formed on the lower electrode 21, and the upper electrode 23 made of platinum (Pt) is formed on the ferroelectric layer 22.
[0060]
The sidewalls of the lower electrode 21, more specifically, the sidewalls of the lower electrode 21 and the diffusion barrier layer 20, are made of Al.₂O_ThreeThe oxygen barrier layer 30 is covered with an oxygen barrier layer 30, and the oxygen barrier layer 30 extends over the interlayer insulating layer 16. Further, although not shown, the oxygen barrier layer 30 covers the alignment mark and / or the peripheral circuit. Therefore, it is possible not only to reliably prevent the contact plug 18A from being oxidized, but also to reliably prevent various peripheral circuits and / or alignment marks from being oxidized.
[0061]
An insulating film 31 is formed on the portion of the interlayer insulating layer 16 where the lower electrode 21 is not formed.
[0062]
Furthermore, as shown in FIG. 1B, a partially enlarged view of the diffusion barrier layer 20, the lower electrode 21, the contact plug 18A, and the like is shown, and the lower end of the side wall 21A of the lower electrode 21 from the upper end 17a of the opening 17A. L in the horizontal direction to the part 21a₀The length of the side wall 21A of the lower electrode 21 along the thickness direction of the lower electrode 21 is L₁L₁≧ 0.25L₀Satisfied. Specifically, L₀= 0.4 μm, L₁= 0.22 μm. L₁≧ 0.25L₀This relationship may vary depending on the size (cell size) of the nonvolatile memory.
[0063]
A method for manufacturing the nonvolatile memory according to the first embodiment will be described below with reference to FIGS. 2 to 4 which are schematic partial sectional views of a semiconductor substrate or the like.
[0064]
[Step-100]
First, a MOS transistor that functions as the selection transistor TR is formed on a semiconductor substrate 10 made of a silicon semiconductor substrate. Therefore, for example, the element isolation region 11 having a LOCOS structure is formed based on a known method. The element isolation region may have a trench structure, or a combination of a LOCOS structure and a trench structure. Thereafter, the surface of the semiconductor substrate 10 is oxidized by, for example, a pyrogenic method to form the gate insulating film 12. Next, after a polysilicon layer doped with impurities is formed on the entire surface by a CVD method, the polysilicon layer is patterned to form the gate electrode 13. The gate electrode 13 also serves as the word line WL. The gate electrode 13 can be made of polycide or metal silicide instead of the polysilicon layer. Next, ion implantation is performed on the semiconductor substrate 10 to form an LDD structure. Then, SiO is deposited on the entire surface by CVD.₂After forming the layer, this SiO 2₂The side wall 14 is formed on the side surface of the gate electrode 13 by etching back the layer. Next, after ion implantation is performed on the semiconductor substrate 10, source / drain regions 15A and 15B are formed by performing activation annealing of the implanted impurities.
[0065]
[Step-110]
Next, SiO having a thickness of about 1 μm is formed on the entire surface.₂After forming the interlayer insulating layer made of CVD by the CVD method, the interlayer insulating layer is polished by the chemical / mechanical polishing method (CMP method) to obtain the interlayer insulating layer 16 having a thickness of about 0.35 μm.
[0066]
[Step-120]
Thereafter, openings 17A and 17B are formed in the interlayer insulating layer 16 above the source / drain regions 15A and 15B by the RIE method, and then the contact plug 18A connected to one source / drain region 15A of the selection transistor TR. Is formed in the opening 17A. At the same time, a connection hole 18B connected to the other source / drain region 15B of the selection transistor TR is formed in the opening 17B. Thus, the structure shown in FIG. 2A can be obtained. The top surfaces of the contact plug 18 </ b> A and the connection hole 18 </ b> B are on the same plane as the surface of the interlayer insulating layer 16. The conditions for filling the openings 17A and 17B with tungsten and forming the contact plug 18A and the connection hole 18B are shown in Table 1 below. Note that, before the openings 17A and 17B are filled with tungsten, it is preferable that the Ti layer and the TiN layer are sequentially formed on the interlayer insulating layer 16 including the openings 17A and 17B by, for example, magnetron sputtering. Here, the reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and to improve the adhesion of tungsten. In the drawing, illustration of the Ti layer and the TiN layer is omitted. The tungsten layer, TiN layer, and Ti layer on the interlayer insulating layer 16 may be removed by a chemical / mechanical polishing method (CMP method). Further, polysilicon doped with impurities can be used instead of tungsten.
[0067]
[Table 1]
Sputtering conditions for Ti layer (thickness: 5 nm)
Process gas: Ar = 35 sccm
Pressure: 0.52 Pa
RF power: 2kW
Substrate heating: None
Sputtering conditions for TiN layer (thickness: 50 nm)
Process gas: N₂/ Ar = 100 / 35sccm
Pressure: 1.0 Pa
RF power: 6kW
Substrate heating: None
Conditions for tungsten CVD
Gas used: WF₆/ H₂/ Ar = 40/400 / 2250sccm
Pressure: 10.7kPa
Formation temperature: 450 ° C
Etching conditions for tungsten layer, TiN layer, and Ti layer
First stage etching: Tungsten layer etching
Gas used: SF₆/ Ar / He = 110: 90: 5 sccm
Pressure: 46Pa
RF power: 275W
Second stage etching: TiN layer / Ti layer etching
Gas used: Ar / Cl₂= 75 / 5sccm
Pressure: 6.5Pa
RF power: 250W
[0068]
[Step-130]
Next, at least the top surfaces of the contact plugs 18A and the connection holes 18B, more specifically, the top surfaces of the contact plugs 18A and the connection holes 18B and the interlayer insulating layer 16 are formed of TiN and patterned. A laminated structure of the diffusion barrier layer 20 and the patterned lower electrode 21 is formed.
[0069]
As a method for forming the diffusion barrier layer 20, for example, a Ti layer having a thickness of 30 nm is formed on the entire surface based on the DC magnetron sputtering method, and then for 30 seconds in a nitrogen gas atmosphere at 750 ° C. by the RTA (Rapid Thermal Annealing) method. A method of heat-treating the Ti layer and nitriding the Ti layer to form a TiN layer can be mentioned, but the method is not limited to such a method. That is, the TiN layer may be formed by, for example, a reactive sputtering method or a CVD method. Furthermore, the material constituting the diffusion barrier layer 20 is not limited to TiN, and any material having an interdiffusion barrier effect at a temperature for forming the ferroelectric layer 22 such as TaN or TiAlN may be used.
[0070]
Further, as a method for forming the lower electrode 21, there can be exemplified a method in which an Ir-Hf film added with 15 atom% of Hf is 20 nm, and an Ir film is formed thereon with a thickness of 200 nm by DC magnetron sputtering. Note that the Ir—Hf film functions as an adhesion layer. In the drawing, the lower electrode 21 is represented by one layer.
[0071]
Next, for densification of the lower electrode 21 and the diffusion barrier layer 20 and stress relaxation, it is preferable to perform a heat treatment for 30 minutes in a 700 ° C. nitrogen gas atmosphere. This temperature is the same as the formation (crystallization) of the ferroelectric layer 22 described later.
[0072]
Thereafter, the lower electrode 21 and the diffusion barrier layer 20 are patterned based on the lithography technique and the dry etching technique (see FIG. 2B). The lower electrode 21 and the diffusion barrier layer 20 have substantially the same planar shape. Depending on the etching conditions, the isotropicity of etching becomes stronger and side etching of the diffusion barrier layer 20 occurs. This is because a seam portion (see FIG. 13B) is generated in the oxygen barrier layer when the oxygen barrier layer is subsequently formed. Will cause. Therefore, Cl₂Etching gas mainly containing Ar / Cl₂: Ar = 9: 1 to 1: 9, gas pressure 0.7 to 4 Pa (5 to 30 mTorr), input power 30 to 200 W, etching with strong anisotropy is performed, and side etching of the diffusion barrier layer 20 is performed. It is preferable to prevent. Of course, other highly anisotropic etching conditions may be used.
[0073]
[Step-140]
After that, 50 nm thick Al was formed by ECR sputtering.₂O_ThreeAn oxygen barrier layer 30 made of is formed on the entire surface (see FIG. 3A). Thus, the side walls of the lower electrode 21 and the diffusion barrier layer 20 are covered with the oxygen barrier layer, and the oxygen barrier layer 30 extends on the interlayer insulating layer 16. The oxygen barrier layer 30 may be made of another material that is thermally stable and has good adhesion to the material constituting the lower electrode 21, and the film forming method is not limited to the ECR sputtering method. Any method for forming a dense film may be used, and for example, an ALD (Atomic Layer Deposition) method may be employed.
[0074]
[Step-150]
Next, an insulating film 31 is formed on the oxygen barrier layer 30. Specifically, first, a 50 nm thick SiO₂A film is formed by a plasma-TEOS CVD method, and then a high-density plasma CVD method (HDP-CVD method) is used to form SiO having a thickness of about 0.6 μm.₂A film is formed.
[0075]
Next, a planarization process is performed by a CMP method, and then a heat treatment for 30 minutes is preferably performed in a nitrogen gas atmosphere at 700 ° C. for densification of the insulating film 31 and the oxygen barrier layer 30 and stress relaxation. . This temperature is the same as the formation (crystallization) of the ferroelectric layer 22 described later.
[0076]
Thereafter, the insulating film 31 and the oxygen barrier layer 30 on the lower electrode 21 are removed on the basis of an etch back method using conditions having a selection ratio with the material constituting the lower electrode 21, and the pedestal shown in FIG. A mold electrode structure can be obtained. In the drawing, the insulating film 31 is represented by one layer.
[0077]
[Step-160]
Next, a ferroelectric layer 22 made of SBT having a thickness of 120 nm is formed by a sol-gel method. Specifically, the ferroelectric layer is formed by repeating the process of applying the SBT precursor solution by a spin-on method and performing heat treatment for 30 minutes in an oxygen gas atmosphere at 700 ° C. for crystallization three times. 22 can be obtained.
[0078]
[Step-170]
Next, an upper electrode 23 made of Pt having a thickness of 100 nm is formed on the entire surface by DC magnetron sputtering. Then, the capacitor structure shown in FIG. 4 can be obtained by sequentially patterning the upper electrode 23 and the ferroelectric layer 22 based on a two-stage lithography technique and a dry etching technique. Note that the upper electrode 23 and the ferroelectric layer 22 may be etched together using a hard mask or the like. Thereafter, in order to recover the characteristic deterioration of the ferroelectric layer 22 due to patterning, it is preferable to perform a heat treatment at 700 ° C. for 30 minutes in an oxygen gas atmosphere.
[0079]
[Step-180]
Then, about 0.3 μm thick SiO₂An insulating layer 24 is formed on the entire surface by plasma-TEOS CVD, and then an opening is formed in the insulating layer 24 above the connection hole 18B and the upper electrode 23 based on a lithography technique and a dry etching technique. Then, a laminated film (not shown) of TiN (thickness 20 nm) / Ti (thickness 20 nm) is added as a wiring layer on the insulating layer 24 including the inside of the opening, and 1 atom% of Si is further added thereon. The Al—Si layers having a thickness of about 0.6 μm are respectively formed by DC magnetron sputtering. Finally, the wiring layer is patterned based on the lithography technique and the dry etching technique, and the bit line BL connected to the source / drain region 15B through the connection holes 18B and 18C, and the plate line connected to the upper electrode 23 PL can be obtained. Thereafter, a passivation film (not shown) is formed on the entire surface to complete the nonvolatile memory shown in FIG.
[0080]
Note that the connection hole 18C may be formed in the opening having a smaller aspect ratio than the conventional nonvolatile memory formed in the insulating layer 24, so that the connection hole 18C having high reliability can be obtained. . Moreover, since the connection hole 18B is covered with the oxygen barrier layer 30 until the opening is formed in the insulating layer 24, it is possible to reliably prevent the connection hole 18B from being oxidized in [Step-160]. In addition, the oxygen barrier layer 30 also functions as an etching stopper layer when an opening is provided in the insulating layer 24 in order to form the connection hole 18C.
[0081]
When the contact resistance between the lower electrode 21 and the contact plug 18A was measured by a known Kelvin 4-terminal method and a contact chain in which several tens to several thousand of the lower electrode 21 and the contact plug 18A were arranged in series, Both show linear IV characteristics, and the contact resistance of the contact plug 18A having a diameter of 0.25 μm is approximately 180Ω / (contact plug having a diameter of 0.25 μm). It became clear that it had sufficient heat resistance and oxidation resistance. In addition, the remanent polarization of the ferroelectric layer 22 is 2P._r= 19 μC / cm²And showed good values.
[0082]
For example, the ferroelectric layer 22 made of a Bi-based layered structure perovskite ferroelectric material may be formed by the MOD method or the MOCVD method. For example, SrBi₂Ta₂O₉Table 2 below illustrates the formation conditions based on the MOCVD method of the ferroelectric layer 22 made of In Table 2, “thd” is an abbreviation for tetramethylheptane dinate. The source materials shown in Table 2 are dissolved in a solvent containing tetrahydrofuran (THF) as a main component.
[0083]

[0084]
Alternatively, SrBi₂Ta₂O₉The ferroelectric layer 22 made of may be formed on the entire surface by the pulse laser ablation method, the sol-gel method or the RF sputtering method as described above. The formation conditions in these cases are exemplified in the following Table 3, Table 4, and Table 5, respectively. When the thick ferroelectric layer 22 is formed by the sol-gel method, the desired number of times of spin coating and drying, or spin coating and baking (or annealing treatment) may be repeated.
[0085]
[Table 3]
Formation by pulsed laser ablation
Target: SrBi₂Ta₂O₉
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 5 Hz)
Formation temperature: 400-800 ° C
Oxygen concentration: 3 Pa
[0086]

[0087]
[Table 5]
Formation by RF sputtering method
Target: SrBi₂Ta₂O₉Ceramic target
RF power: 1.2W-2.0W / target 1cm²
Atmospheric pressure: 0.2 to 1.3 Pa
Formation temperature: Room temperature to 600 ° C
Process gas: Ar / O₂Flow rate ratio = 2/1 to 9/1
[0088]
Table 6 below illustrates the formation conditions of PZT or PLZT by the magnetron sputtering method when the ferroelectric layer is made of PZT or PLZT. Alternatively, PZT or PLZT can be formed by a reactive sputtering method, an electron beam evaporation method, a sol-gel method, or an MOCVD method.
[0089]
[Table 6]
Target: PZT or PLZT
Process gas: Ar / O₂= 90% by volume / 10% by volume
Pressure: 4Pa
Power: 50W
Formation temperature: 500 ° C
[0090]
Furthermore, PZT and PLZT can be formed by a pulse laser ablation method. The formation conditions in this case are illustrated in Table 7 below.
[0091]
[Table 7]
Target: PZT or PLZT
Laser used: KrF excimer laser (wavelength 248 nm, pulse width 25 ns, 3 Hz)
Output energy: 400 mJ (1.1 J / cm²)
Formation temperature: 550-600 ° C
Oxygen concentration: 40 to 120 Pa
[0092]
The various methods for forming the ferroelectric layer 22 described above can also be applied to the embodiments described below.
[0093]
In the formation of the ferroelectric layer 22 at a high temperature, although it is not easy to completely prevent oxygen diffusion from the interface between the lower electrode 21 and the oxygen barrier layer 30, oxidation of the contact plug 18A is prevented, and the lower electrode 21 is prevented. If an increase in contact resistance between the contact plug 18A and the contact plug 18A can be prevented, there is substantially no problem in the operation of the nonvolatile memory. With respect to the problem of oxygen diffusion via the interface, the present inventors have found an evaluation method that can be easily evaluated without forming a complicated measurement pattern. Based on this evaluation method, the thickness of the lower electrode 21 (more precisely, the length L of the side wall 21A of the lower electrode 21 along the thickness direction of the lower electrode 21).₁) Can prevent oxidation of the contact plug 18A.
[0094]
This evaluation method applies, for example, that TiN and TaN constituting the diffusion barrier layer 20 are accompanied by volume expansion due to oxidation. That is, after forming the ferroelectric layer 22 in [Step-160], the oxidation state of the diffusion barrier layer 20 is observed using a scanning electron microscope (SEM) or the like. That is, the expansion state of the diffusion barrier layer 20 is observed. This state is schematically illustrated in FIG. Although the shape of the lower electrode 21 and the ferroelectric layer 22 also changes as the diffusion barrier layer 20 expands due to oxidation, the illustration of these changes is omitted in FIG. This is the length L of the side wall 21A of the lower electrode 21 along the thickness direction of the lower electrode 21.₁Then, by using the heat treatment temperature for crystallization of the ferroelectric layer 22 in [Step-160] as a parameter, how far the diffusion barrier layer 20 is oxidized from the side wall 21A of the diffusion barrier layer 20 is evaluated. The length L of the side wall 21A of the lower electrode 21 along the thickness direction of the lower electrode 21₁The distance L from the side wall of the diffusion barrier layer 20 in the region 120 of the oxidized diffusion barrier layer 20 has a relationship as schematically shown in FIG. That is, the length L₁The larger the value of, the smaller the value of the distance L.
[0095]
The distance L is the shortest horizontal distance L from the upper end 17a of the opening 17A to the lower end 21a of the side wall 21A of the lower electrode 21.₀If it is smaller than (or sufficiently small), the contact plug 18A will not be oxidized. For example, the lower electrode 21 is made of Ir, and the oxygen barrier layer 30 is made of Al.₂O_ThreeWhen the crystallization temperature is as high as about 700 ° C. like SBT, the lower electrode 21 along the thickness direction of the lower electrode 21 is used to suppress the distance L to 0.4 μm or less. Side wall 21A length L₁As a result of various tests, it was found that the thickness of the film should be 150 nm or more. Further, when the crystallization temperature is about 600 ° C. as in PZT, in order to suppress the distance L to 0.4 μm or less, the side wall of the lower electrode 21 along the thickness direction of the lower electrode 21 is used. 21A length L₁As a result of various tests, it was found that the thickness should be 80 nm or more. Then, the length L of the side wall 21A of the lower electrode 21 along the thickness direction of the lower electrode 21 estimated in this way.₁In addition to the length L determined in consideration of the alignment accuracy of lithography technology₁(In the first embodiment, 0.22 μm) was applied to manufacture a nonvolatile memory as in the first embodiment, and the contact resistance between the lower electrode 21 and the contact plug 18A was measured. In addition, a highly reliable pedestal-type electrode structure free from poor conduction due to oxidation could be obtained.
[0096]
(Embodiment 2)
The second embodiment is a modification of the first embodiment. In the first embodiment, diffusion barrier layer 20 is formed over interlayer insulating layer 16 from the top surface of contact plug 18A. On the other hand, in the second embodiment, as shown in a schematic partial cross-sectional view in FIG. 6, the diffusion barrier layer 20A is formed only on the top surface of the contact plug 18A. The side wall of the lower electrode 21 is covered with the oxygen barrier layer 30. Except for these points, the non-volatile memory of the second embodiment has the same structure as the non-volatile memory described in the first embodiment, and a detailed description thereof will be omitted.
[0097]
The nonvolatile memory according to the second embodiment can be manufactured by the following method. That is, in the same step as [Step-120] of the first embodiment, after the contact plug 18A and the connection hole 18B are formed, the contact plug 18A and the connection hole 18B are etched back based on the RIE method, thereby opening the contact plug 18A and the connection hole 18B. The contact plugs 18A and the tops of the connection holes 18B in the parts 17A and 17B are removed. Next, in the same step as [Step-130] in the first embodiment, after the diffusion barrier layer 20 made of TiN is formed over the interlayer insulating layer 16 from the top surfaces of the contact plug 18A and the connection hole 18B. The diffusion barrier layer 20 on the interlayer insulating layer 16 may be removed by, for example, a CMP method.
[0098]
Alternatively, as shown in a schematic partial cross-sectional view in FIG. 7, the diffusion barrier layer 20B is formed over the interlayer insulating layer 16 from the top surface of the contact plug 18A, and the diffusion barrier layer 20B is formed in the lower part. It can also be set as the structure covered with the electrode 21. FIG. In this case, unlike the planar shape of the diffusion barrier layer 20 </ b> B and the planar shape of the lower electrode 21, the side wall of the lower electrode 21 is covered with the oxygen barrier layer 30. In such a structure, in the same step as [Step-130] of the first embodiment, the diffusion barrier layer 20B made of TiN extends from the top surfaces of the contact plug 18A and the connection hole 18B onto the interlayer insulating layer 16. After forming the diffusion barrier layer 20B, the lower electrode 21 may be patterned after the lower electrode 21 is formed on the entire surface.
[0099]
(Embodiment 3)
The third embodiment relates to the nonvolatile memory according to the second and third aspects of the present invention and the method for manufacturing the nonvolatile memory according to the second aspect of the present invention.
[0100]
As shown in a schematic partial cross-sectional view in FIG. 8, the nonvolatile memory of the third embodiment also includes the selection transistor TR, the interlayer insulating layer 16, the contact plug 18A, the diffusion barrier layer 20, the lower electrode 21, and the ferroelectric. It is composed of a body layer 22 and an upper electrode 23. Here, the selection transistor TR is formed on the semiconductor substrate 10 made of a silicon semiconductor substrate, and SiO 2₂An interlayer insulating layer 16 made of is covering the entire surface including the selection transistor TR. The contact plug 18A made of tungsten is provided in an opening 17A formed in the interlayer insulating layer 16, and is connected to one source / drain region 15A of the selection transistor TR. The diffusion barrier layer 20 made of TiN is formed at least on the top surface of the contact plug 18A, more specifically, over the interlayer insulating layer 16 from the top surface of the contact plug 18A, and is patterned. Yes. Furthermore, the lower electrode 21 made of a conductive material (more specifically, Ir / Ir-Hf) having an oxygen diffusion preventing ability is formed on the diffusion barrier layer 20 and is substantially the same shape as the diffusion barrier layer 20. Patterned. The ferroelectric layer 22 made of SBT is formed on the lower electrode 21, and the upper electrode 23 made of platinum (Pt) is formed on the ferroelectric layer 22.
[0101]
The sidewalls of the lower electrode 21, more specifically, the sidewalls of the lower electrode 21 and the diffusion barrier layer 20, are made of Al.₂O_ThreeThe first oxygen barrier layer 40 is covered with the first oxygen barrier layer 40, and the first oxygen barrier layer 40 extends on the interlayer insulating layer 16. Further, although not shown, the first oxygen barrier layer 40 covers the alignment mark and / or the peripheral circuit. A second oxygen barrier layer 41 is formed on the first oxygen barrier layer 40 located in the vicinity of the lower end of the lower electrode 21 and the surface of the interlayer insulating layer 16.
[0102]
Furthermore, an insulating film 31 is formed in the portion of the interlayer insulating layer 16 where the lower electrode 21 is not formed.
[0103]
The shortest horizontal distance from the upper end of the opening 17A to the lower end of the side wall of the lower electrode 21 is L.₀The length of the side wall of the lower electrode 21 along the thickness direction of the lower electrode 21 is L₁(See FIG. 1B), L₁≧ 0.25L₀Satisfied. Specifically, L₀= 0.4 μm, L₁= 0.22 μm. L₁≧ 0.25L₀This relationship may vary depending on the size (cell size) of the nonvolatile memory.
[0104]
A method for manufacturing the nonvolatile memory according to the third embodiment will be described below with reference to FIG. 9 which is a schematic partial sectional view of a semiconductor substrate or the like.
[0105]
[Step-300]
First, in the same manner as in [Step-100] of the first embodiment, a MOS transistor functioning as the selection transistor TR is formed on the semiconductor substrate 10 made of a silicon semiconductor substrate. Next, in the same manner as in [Step-110] in the first embodiment, the interlayer insulating layer 16 is formed on the entire surface. Thereafter, the contact plug 18A and the connection hole 18B are formed in the openings 17A and 17B in the same manner as in [Step-120] of the first embodiment.
[0106]
[Step-310]
Next, as in [Step-130] of the first embodiment, at least the top surfaces of the contact plugs 18A and the connection holes 18B, more specifically, the interlayer insulating layers from the top surfaces of the contact plugs 18A and the connection holes 18B. A laminated structure of TiN and patterned diffusion barrier layer 20 and patterned lower electrode 21 is formed over 16. As in the first embodiment, it is preferable to perform a heat treatment for 30 minutes in a nitrogen gas atmosphere at 700 ° C. in order to densify the lower electrode 21 and the diffusion barrier layer 20 and relieve stress. This temperature is the same temperature as the formation (crystallization) of the ferroelectric layer 22.
[0107]
[Step-320]
Thereafter, similarly to [Step-140] of the first embodiment, Al having a thickness of 50 nm is formed by ECR sputtering.₂O_ThreeA first oxygen barrier layer 40 made of is formed on the entire surface. Thus, the side walls of the lower electrode 21 and the diffusion barrier layer 20 are covered with the first oxygen barrier layer 40, and the first oxygen barrier layer 40 extends on the interlayer insulating layer 16. Note that the first oxygen barrier layer 40 may be selectively removed so that the first oxygen barrier layer 40 does not remain on the interlayer insulating layer 16.
[0108]
[Step-330]
Next, an SiN layer having a thickness of 80 nm is formed on the entire surface by a plasma CVD method having excellent step coverage. Thereafter, the SiN layer is etched back by the RIE method, and on the portion of the first oxygen barrier layer 40 (so-called seam portion) located in the vicinity of the lower end portion of the lower electrode 21 and the surface of the interlayer insulating layer 16, A second oxygen barrier layer 41 made of SiN and having a sidewall shape is formed. The material constituting the second oxygen barrier layer 41 may be any other material as long as it has an oxygen barrier property. However, from the viewpoint of reinforcing the seam portion of the first oxygen barrier layer 40, a material with good coverage can be obtained. It is preferable to use a membrane method. Thus, the structure shown in FIG. 9A can be obtained.
[0109]
[Step-340]
Next, the insulating film 31 is formed on the first oxygen barrier layer 40 as in [Step-150] of Embodiment 1. Then, planarization is performed by a CMP method, and then in a nitrogen gas atmosphere at 700 ° C. for densification and stress relaxation of the insulating film 31, the first oxygen barrier layer 40 and the second oxygen barrier layer 41. It is preferable to heat-treat for 30 minutes. This temperature is the same as the formation (crystallization) of the ferroelectric layer 22. Thereafter, the insulating film 31 and the first oxygen barrier layer 40 on the lower electrode 21 are removed based on an etch-back method using conditions having a selection ratio with the material constituting the lower electrode 21, and FIG. Can be obtained. In the drawing, the insulating film 31 is represented by one layer.
[0110]
[Step-350]
Next, the non-volatile memory shown in FIG. 8 is completed by executing the same steps as [Step-160] to [Step-180] of the first embodiment.
[0111]
In [Step-330], a SiN layer is formed on the entire surface, and without performing etch back of the SiN layer, the insulating film 31 is formed on the SiN layer in [Step-340], and then flattened by CMP. In addition, for the purpose of densification and stress relaxation of the insulating film 31, the SiN layer, the first oxygen barrier layer 40, and the second oxygen barrier layer 41, 30 minutes in a nitrogen gas atmosphere at 700 ° C. After the heat treatment is performed, the insulating film 31, the SiN layer, and the first oxygen barrier layer 40 on the lower electrode 21 are removed based on an etch back method using conditions having a selection ratio with the material constituting the lower electrode 21. Then, the second oxygen barrier layer 41 made of SiN is formed on the portion of the first oxygen barrier layer 40 (so-called seam portion) located in the vicinity of the lower end portion of the lower electrode 21 and the surface of the interlayer insulating layer 16. May be formed. In this case, the second oxygen barrier layer 41 is also left on the first oxygen barrier layer 40 extending on the interlayer insulating layer 16.
[0112]
In the third embodiment, on the portion of the first oxygen barrier layer 40 located near the lower end of the lower electrode 21 and the surface of the interlayer insulating layer 16 (specifically, for example, a seam portion). Since the second oxygen barrier layer 41 is formed, the contact plug 18A and the diffusion barrier layer 20 can be reliably prevented from being oxidized.
[0113]
When the contact resistance between the lower electrode 21 and the contact plug 18A was measured by a known Kelvin 4-terminal method and a contact chain in which several tens to several thousand of the lower electrode 21 and the contact plug 18A were arranged in series, Both show linear IV characteristics, and the contact resistance of the contact plug 18A having a diameter of 0.25 μm is about 180Ω. The stacked capacitor structure of the third embodiment has sufficient heat resistance and oxidation resistance. It became clear that In addition, the remanent polarization of the ferroelectric layer 22 is 2P._r= 18 μC / cm²And showed good values.
[0114]
(Embodiment 4)
The fourth embodiment is a modification of the third embodiment. In the third embodiment, diffusion barrier layer 20 is formed on interlayer insulating layer 16 from the top surface of contact plug 18A. On the other hand, in the fourth embodiment, as shown in a schematic partial sectional view of FIG. 10, the diffusion barrier layer 20A is formed only on the top surface of the contact plug 18A. The side wall of the lower electrode 21 is covered with the oxygen barrier layer 30. Except for these points, the non-volatile memory of the fourth embodiment has the same structure as the non-volatile memory described in the third embodiment, and a detailed description thereof will be omitted.
[0115]
The nonvolatile memory according to the fourth embodiment can be manufactured by the following method. That is, in the same step as [Step-120] of the first embodiment, after the contact plug 18A and the connection hole 18B are formed, the contact plug 18A and the connection hole 18B are etched back based on the RIE method, thereby opening the contact plug 18A and the connection hole 18B. The contact plugs 18A and the tops of the connection holes 18B in the parts 17A and 17B are removed. Next, in the same step as [Step-130] in the first embodiment, after the diffusion barrier layer 20 made of TiN is formed over the interlayer insulating layer 16 from the top surfaces of the contact plug 18A and the connection hole 18B. The diffusion barrier layer 20 on the interlayer insulating layer 16 may be removed by, for example, a CMP method.
[0116]
Alternatively, as shown in a schematic partial cross-sectional view in FIG. 11, the diffusion barrier layer 20B is formed over the interlayer insulating layer 16 from the top surface of the contact plug 18A, and the diffusion barrier layer 20B is formed in the lower part. It can also be set as the structure covered with the electrode 21. FIG. In this case, unlike the planar shape of the diffusion barrier layer 20 </ b> B and the planar shape of the lower electrode 21, the side wall of the lower electrode 21 is covered with the first oxygen barrier layer 40. In such a structure, in the same step as [Step-130] of the first embodiment, the diffusion barrier layer 20B made of TiN extends from the top surfaces of the contact plug 18A and the connection hole 18B onto the interlayer insulating layer 16. After forming the diffusion barrier layer 20B, the lower electrode 21 may be patterned after the lower electrode 21 is formed on the entire surface.
[0117]
As mentioned above, although this invention was demonstrated based on embodiment of this invention, this invention is not limited to these. The structure of the nonvolatile memory described in the embodiment of the invention, the materials used, various formation conditions, and the like are examples, and can be changed as appropriate. For example, in some cases, the formation of the plate line can be omitted, and the upper electrode can also serve as the plate line.
[0118]
In the present invention, the ferroelectric layer is made of BaTiO._Three(Barium titanate) and SrTiO_Three(Strontium titanate), (Ba, Sr) TiO_ThreeIf it is replaced with a high dielectric layer made of a high dielectric material such as (barium strontium titanate), it can be applied to a DRAM and a manufacturing method thereof. The ferroelectric nonvolatile semiconductor memory of the present invention can also be applied to a DRAM. In this case, the polarization of the ferroelectric layer is used within the range of the additional voltage that does not cause polarization reversal. That is, the maximum (saturated) polarization P due to the external electric field_maxAnd the residual polarization P when the external electric field is zero_rDifference from (P_max-P_r) Uses a characteristic having a certain relation (substantially proportional relation) to the power supply voltage. The polarization state of the ferroelectric layer is always saturation polarization (P_max) And remanent polarization (P_r) And not reversed. Data is retained by refresh.
[0119]
【The invention's effect】
In the ferroelectric nonvolatile semiconductor memory and the manufacturing method thereof according to the first aspect of the present invention, the side wall of the lower electrode (in some cases, in addition, the side wall of the diffusion barrier layer) is covered with the oxygen barrier layer. Since the oxygen barrier layer extends over the interlayer insulating layer, the contact plug can be reliably prevented from being oxidized, and various peripheral circuits and / or alignment marks are oxidized. Can be reliably prevented. Further, in the ferroelectric nonvolatile semiconductor memory and the manufacturing method thereof according to the second aspect of the present invention, the portion of the first oxygen barrier layer located in the vicinity of the lower electrode lower end portion and the surface of the interlayer insulating layer Since the second oxygen barrier layer is formed on the surface, it is assumed that the seam portion is generated in the portion of the first oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. However, since the seam portion is covered with the second oxygen barrier layer, the contact plug and the diffusion barrier layer can be reliably prevented from being oxidized. Furthermore, in the ferroelectric nonvolatile semiconductor memory according to the third aspect of the present invention, L₁≧ 0.25L₀Therefore, even when oxygen enters from between the side wall of the lower electrode and the oxygen barrier layer, oxygen does not reach the contact plug, and the contact plug is surely oxidized. Can be prevented. In the present invention, a contact failure occurs in the contact plug in the stack type capacitor structure, the adhesion between the lower electrode and the contact plug is lowered, the adhesion between the lower electrode and the diffusion barrier layer is lowered, the interlayer A problem such as a decrease in adhesion between the insulating layer and the diffusion barrier layer does not occur, and a ferroelectric nonvolatile semiconductor memory having high reliability can be obtained.
[Brief description of the drawings]
FIG. 1A is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to a first embodiment of the present invention, and FIG. It is a partial enlarged view of an electrode, a contact plug, etc.
FIGS. 2A and 2B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention; It is.
FIGS. 3A and 3B are semiconductor substrates for explaining a manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention, following FIG. 2B; FIGS. It is typical partial sectional views, such as.
4 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention, following FIG. 3B. FIG. FIG.
FIG. 5A is a diagram schematically showing an oxidation state of the diffusion barrier layer after the ferroelectric layer is formed, and FIG. 5B is a diagram showing a thickness direction of the lower electrode. The length L of the side wall of the lower electrode along₁And a graph schematically showing the relationship between the distance L from the side wall of the diffusion barrier layer in the region of the oxidized diffusion barrier layer.
FIG. 6 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to a second embodiment of the invention.
FIG. 7 is a schematic partial sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to the second embodiment of the present invention.
FIG. 8 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to a third embodiment of the present invention.
FIGS. 9A and 9B are schematic partial cross-sectional views of a semiconductor substrate and the like for explaining the manufacturing method of the ferroelectric nonvolatile semiconductor memory according to the first embodiment of the invention. FIGS. It is.
FIG. 10 is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory according to a fourth embodiment of the invention.
FIG. 11 is a schematic partial cross-sectional view of a modification of the ferroelectric nonvolatile semiconductor memory according to the fourth embodiment of the present invention.
12A is a schematic partial cross-sectional view of a conventional ferroelectric nonvolatile semiconductor memory, and FIG. 12B is a diagram of a conventional ferroelectric nonvolatile semiconductor memory. It is a typical partial cross section figure in the middle of manufacture of the ferroelectric type non-volatile semiconductor memory for demonstrating a problem.
13A is a schematic partial cross-sectional view of a ferroelectric nonvolatile semiconductor memory disclosed in Japanese Patent Application Laid-Open No. 2001-60670, and FIG. It is a typical partial cross section figure in the middle of manufacture of the ferroelectric type non-volatile semiconductor memory for demonstrating the problem in the ferroelectric type non-volatile semiconductor memory disclosed by -60670.
FIG. 14A is an equivalent circuit diagram of a ferroelectric nonvolatile semiconductor memory, and FIG. 14B is a diagram schematically showing a ferroelectric PE hysteresis loop. is there.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Element isolation region, 12 ... Gate insulating film, 13 ... Gate electrode, 14 ... Gate side wall, 15A, 15B ... Source / drain region, 16 ... Interlayer insulating layer, 17A, 17B ... Opening, 18A ... Contact plug, 18B, 18C ... Connection hole, 20, 20A, 20B ... Diffusion barrier layer, 21 ... Bottom Electrode 22 ... ferroelectric layer 23 ... upper electrode 24 ... insulating layer 30 ... oxygen barrier layer 31 ... insulating film 40 ... first oxygen barrier layer 41 ... second oxygen barrier layer, 31 ... insulating film, BL ... bit line, PL ... plate line

Claims (19)

(A) a selection transistor formed on a semiconductor substrate;
(B) an interlayer insulating layer covering the selection transistor;
(C) a contact plug provided in an opening formed in the interlayer insulating layer and connected to one source / drain region of the selection transistor;
(D) a diffusion barrier layer formed and patterned on at least the top surface of the contact plug;
(E) a patterned lower electrode formed on at least the diffusion barrier layer;
(F) a ferroelectric layer formed on the lower electrode, and
(G) an upper electrode formed on the ferroelectric layer;
A ferroelectric nonvolatile semiconductor memory comprising:
The side wall of the lower electrode is covered with a first oxygen barrier layer,
A ferroelectric nonvolatile semiconductor, wherein a second oxygen barrier layer is formed on a portion of the first oxygen barrier layer located in the vicinity of the lower end of the lower electrode and the surface of the interlayer insulating layer memory. The diffusion barrier layer is formed over the interlayer insulating layer from the top surface of the contact plug,
The diffusion barrier layer and the lower electrode have substantially the same planar shape,
2. The ferroelectric nonvolatile semiconductor memory according to claim 1, wherein side walls of the lower electrode and the diffusion barrier layer are covered with a first oxygen barrier layer.   2. The ferroelectric-type nonvolatile semiconductor memory according to claim 1, wherein the first oxygen barrier layer extends on the interlayer insulating layer.   2. The ferroelectric-type nonvolatile semiconductor memory according to claim 1, wherein an insulating film is formed in a portion of the interlayer insulating layer where the lower electrode is not formed. The first oxygen barrier layer is made of at least one material selected from the group consisting of Al ₂ O ₃ , ZrO ₂ , HfO ₂ , TiO _x , TaO _x and AlN. Ferroelectric type nonvolatile semiconductor memory.   2. The ferroelectric nonvolatile semiconductor memory according to claim 1, wherein the second oxygen barrier layer is made of SiN.   2. The ferroelectric nonvolatile semiconductor memory according to claim 1, wherein the lower electrode is made of a conductive material having an oxygen diffusion preventing ability.   8. The ferroelectric-type nonvolatile semiconductor according to claim 7, wherein the lower electrode layer is made of at least one noble metal selected from the group consisting of Ir, Ru, Rh, Pd, and Pt, or a compound thereof. memory. (A) forming a selection transistor on a semiconductor substrate;
(B) forming an interlayer insulating layer on the entire surface;
(C) after forming an opening in the interlayer insulating layer, forming a contact plug connected to one source / drain region of the selection transistor in the opening;
(D) forming a laminated structure of a patterned diffusion barrier layer and a patterned lower electrode on at least the top surface of the contact plug;
(E) The side wall of the lower electrode is covered with the first oxygen barrier layer, and the second oxygen barrier layer is formed on the portion of the first oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. Forming an oxygen barrier layer of
(F) forming a ferroelectric layer on the lower electrode;
(G) forming an upper electrode on the ferroelectric layer;
A method for manufacturing a ferroelectric nonvolatile semiconductor memory, comprising: In the step (d), a diffusion barrier layer is formed from the top surface of the contact plug over the interlayer insulating layer, and a diffusion structure in which the diffusion barrier layer and the lower electrode have substantially the same planar shape is formed. ,
10. The method for manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 9 , wherein in the step (e), the side walls of the lower electrode and the diffusion barrier layer are covered with a first oxygen barrier layer. In the step (e), after the first oxygen barrier layer is formed on the entire surface, the second oxygen is formed on the portion of the first oxygen barrier layer located near the lower end of the lower electrode and the surface of the interlayer insulating layer. 11. The ferroelectric type according to claim 10 , further comprising a step of forming a barrier layer and then forming an insulating film on the entire surface and then removing the insulating film and the first oxygen barrier layer on the lower electrode. A method for manufacturing a nonvolatile semiconductor memory. The method of manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 11 , wherein the insulating film is made of SiO ₂ and is formed by a high density plasma CVD method. After the insulating film is formed, the insulating film, the first oxygen barrier layer, and the second oxygen barrier layer are subjected to heat treatment at substantially the same temperature as the formation of the ferroelectric layer in the step (f). A method for manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 11 . During the step (d) and step (e), claim 9, characterized in that a heat treatment to the lower electrode and the diffusion barrier layer substantially at the same temperature with the formation of the ferroelectric layer in the step (f) A method for manufacturing a ferroelectric-type nonvolatile semiconductor memory described in 1. 10. The method for manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 9 , wherein the oxygen barrier layer is formed by ECR sputtering. The first oxygen barrier layer, according to _{Al 2 O 3, ZrO 2,} HfO 2, TiO X, claim 9, characterized in that it consists of at least one material selected from the group consisting of TaO _X and AlN Of manufacturing a ferroelectric-type nonvolatile semiconductor memory. 10. The method for manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 9 , wherein the second oxygen barrier layer is made of SiN. 10. The method for manufacturing a ferroelectric nonvolatile semiconductor memory according to claim 9 , wherein the lower electrode is made of a conductive material having an oxygen diffusion preventing ability. The ferroelectric-type nonvolatile semiconductor according to claim 18 , wherein the lower electrode layer is made of at least one noble metal selected from the group consisting of Ir, Ru, Rh, Pd, and Pt, or a compound thereof. Memory manufacturing method.

Images