KR100688054B1 - Method for fabricating concave capacitor in ferroelectric semiconductor device - Google Patents

Abstract

The present invention provides a method of fabricating a highly stable cone capacitor in the formation of a concealed capacitor structure of a ferroelectric element by preventing an overetching angle by adding an etching stop layer when etching an interlayer insulating layer in which a capacitor is formed, To this end, a ferroelectric capacitor manufacturing method of the present invention includes: depositing a first interlayer insulating layer on a substrate and forming a contact plug; Forming a diffusion barrier layer on the contact plug; Depositing a second interlayer insulating layer covering the diffusion barrier layer; Chemical mechanical polishing of the second interlayer insulating layer until the diffusion barrier layer is exposed; Depositing Al2O3 as an etch stop layer on the second interlayer insulating layer; Depositing a third interlayer insulating layer on the etch stop layer and forming a hole; Forming an adhesive layer in the hole; And patterning the lower electrode, the ferroelectric, and the upper electrode over the adhesive layer.

Semiconductor, ferroelectric, capacitor, etch stop layer

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric capacitor,             

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a capacitor of a cone structure according to the prior art; Fig.

2A to 2J are cross-sectional views of a capacitor process of a cone structure according to a preferred embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

30: substrate 31: element isolation film

32: active region 33: contact plug

34: first interlayer insulating layer 35: contact film

39: second interlayer insulating layer 40, 42: Al2O3

41: third interlayer insulating layer 43: lower electrode

44: ferroelectric 45: upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing field, and more particularly, to a ferroelectric capacitor forming method having a concave structure.

Ferroelectric random access memory (FeRAM) is a kind of nonvolatile memory device. It has the advantage of storing the stored information even when the power is off, and the operating speed is comparable to the conventional DRAM (Dynamic Random Access Memory) Be in the spotlight. SrBi2Ta2O9 (SBT) and Pb (ZrxTi1-x) O3 (PZT) thin films are mainly used as the dielectric material of the FeRAM device. In order to obtain excellent ferroelectric characteristics of the ferroelectric film, It is essential.

A non-volatile ferroelectric memory device is defined as "0" and "1" according to the direction of the ferroelectric substance, by utilizing the property of the ferroelectric substance that the residual polarization exists and the directionality thereof can be reversed even when the electric field is removed .

FeRAM cells have almost the same structure as word lines, bit lines, ferroelectric capacitors and transistors like conventional DRAMs. However, the dielectric film of the information storage capacitor is made of a ferroelectric material and the ferroelectric material is Pb (Zr, Ti) O3 PZT) and SrBi2Ta2O9 (SBT) are used. As the electrode, noble metal such as Pt, Ru, and Ir and noble metal oxide such as RuO2 and IrO2 are used.

In the DRAM, the upper electrode serves as a cell plate and the lower electrode serves as a storage node. In FeRAM, an upper electrode serves as a storage node and a lower electrode serves as a cell plate. do. Therefore, in order to connect the transistor with the storage node, there is an interconnection using a metal film in the cell. Further, in the FeRAM, the cell plate may be driven according to the driving method, so that the cell plate is divided and the cell plate is selectively driven only for a part of the cell plate.

  As the degree of integration of semiconductor memory elements increases, the area of a memory cell that stores 1 bit, which is the basic unit of memory information, is getting smaller. However, it is not possible to reduce the area of the capacitor in proportion to the reduction of the cell. This is because the sensing margin, the sensing speed, the durability against the soft error due to the? Because a charging capacity of more than a certain amount per unit cell is required.

Therefore, it has been studied to construct a capacitor of a three-dimensional structure among the methods of increasing the effective area of the capacitor in order to maintain the capacity of the memory capacitor within a limited cell area. The capacitor of a three-dimensional structure includes a stack structure, a concave structure, a sylinder structure, and a multi-layered pin structure.

The FeRAM needs to pattern the upper electrode in units of one capacitor for reasons of its operating method. Therefore, a concave structure which facilitates the patterning of the upper electrode is mainly used.

1 is a view showing a part of a process section of a conventional ferroelectric capacitor having a cone structure.

1, a first interlayer insulating layer 13 is formed on a substrate 10 on which an element isolation film 11, a gate pattern, and an active region 12 are formed, A contact hole is formed through the first interlayer insulating layer 13 and connected to the active region 12 of the substrate 10. A plug 15 is formed of polysilicon or tungsten in the contact hole, a TiSi2 16 is formed as a contact film for Ohmic's contact above the plug, a second interlayer insulating layer 14 is deposited Deposition TiN / Ir / IrOx (17, 18, 19) in the patterned area.

On the polysilicon, a TiN / Ti-Silicide process is typically performed for the purpose of reducing the barrier metal and contact resistance. However, because the TiN used at this time is weak in the high-temperature thermal process, Ir / IrOx, which is superior in the diffusion prevention characteristic of the external oxygen, is mainly used on the upper side of the plug.

Then, the third interlayer insulating film 20 is deposited, and the lower electrode, the ferroelectric, and the upper electrode are formed in the patterned holes to complete the capacitor.

In order to increase the surface area of the concealed capacitor having such a three-dimensional structure, SiOx (third interlayer insulating layer 20) is deposited by a desired thickness (about 10000 ANGSTROM) and then etched. However, when such a thick SiOx is etched, it becomes difficult to control the degree of overexcitation, and for this reason, an Over etch phenomenon (A portion in FIG. 1) occurs at the time of etching the cone hole at the top of the plug . Such a phenomenon eventually degrades the oxidation resistance characteristic of the plug, which causes many problems such as limitation of the heat treatment temperature in the subsequent capacitor manufacturing process, making it difficult to manufacture a three-dimensional capacitor.

An object of the present invention is to provide an etching stop layer during etching of an interlayer insulating layer in which a cone capacitor of a ferroelectric element is formed to prevent an over-etching and to provide a method of manufacturing a highly stable cone capacitor in a subsequent heat treatment.

According to an aspect of the present invention, there is provided a method of fabricating a ferroelectric capacitor including depositing a first interlayer insulating layer on a substrate and forming a contact plug; Forming a diffusion barrier layer on the contact plug; Depositing a second interlayer insulating layer covering the diffusion barrier layer; Chemical mechanical polishing of the second interlayer insulating layer until the diffusion barrier layer is exposed; Depositing Al2O3 as an etch stop layer on the second interlayer insulating layer; Depositing a third interlayer insulating layer on the etch stop layer and forming a hole; Forming an adhesive layer in the hole; And patterning the lower electrode, the ferroelectric, and the upper electrode over the adhesive layer.

The present invention is formed by first depositing SiOx and a layer having an excellent selectivity such as Al2O3 under the SiOx film to be deposited to form a cone structure. Since the selectivity ratio of Al2O3 to SiOx is about 50: 1, the Al2O3 layer acts as a stopping layer even when the etching time is sufficiently long at the time of etching the SiOx layer. Therefore, Is not generated.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

2A to 2J show cross-sectional views of a capacitor process of a cone structure according to a preferred embodiment of the present invention.

2A, a first interlayer insulating layer 34 is formed on a substrate 30 on which a device isolation layer 31, a gate pattern, and an active region 32 are formed, and then the first interlayer insulating layer 34 to form a contact hole to be connected to the active region 32 of the substrate 30. The polysilicon is then deposited over the surface to fill the contact holes. Then, the contact plug 33 is formed using a chemical mechanical polishing and an etch-back process or the like.

Here, tungsten, TaN or TiN may be used instead of polysilicon, or other conductive materials may be applied. When tungsten is applied, a TiSi2 and TiN process is performed underneath the tungsten plug. When TiN is applied, a TiSi2 process is performed under the TiN.

Referring to FIG. 2B, after the contact plug 33 is formed, Ti is deposited on the entire surface of the substrate. Heat treatment is performed in an N2 atmosphere using heat treatment using a furnace or rapid thermal treatment (RTP) so that TiSi2 (35) is formed only in the portion where the polysilicon is exposed. Then, the remaining portion of Ti is removed by wet cleaning or the like. Here, instead of TiSi2, TiSi, CoSi, CoSi2 and the like can be applied.

Referring to FIG. 2C, TiN / Ir / IrOx is sequentially deposited on the entire surface of the substrate from the bottom by chemical vapor deposition, physical vapor deposition (IMP), or atomic layer deposition After that, the TiN / Ir / IrOx (36, 37, 38) on the upper side of the plug is removed using a general photo and etch process, and the remainder is removed. Here, TiN serves as a diffusion preventing film, and Ir / IrOx serves as an oxidation preventing film.

At this time, plasma treatment can be performed in an N 2 or O 2 atmosphere for the purpose of improving the characteristics of the diffusion preventing film and the oxidation preventing film. Here, in order to improve the characteristics of the diffusion barrier layer, the heat treatment may be performed in a N 2 or O 2 atmosphere at 300 to 700 ° C. for 1 second to 5 hours by using a furnace or a rapid thermal annealing or by using other inert gas .

At this time, it is important to perform a sufficient slope etching so that the IrOx / Ir (38,37) fence does not occur. Here, the thickness of the TiN 36 is about 10 to 1000 angstroms, and the thickness of the Ir 37 is about 100 to 3000 angstroms.

In addition, the thickness of the IrOx 38 is about 10 to 1000 ANGSTROM. The same effect can be obtained by replacing TiNN, TaSiN, RuTiO, or RuTiN, which is superior in oxidation resistance, instead of TiN. Alternatively, RuOx / Ru may be deposited instead of IrOx / Ir, or Ru, RuTiN, RuTiO, RuTaN, RuTiO may be used.

Here, instead of the direct deposition process for forming Ir / IrOx, IrOx is formed on the Ir surface in an oxygen atmosphere in the range of 300 to 700 占 폚 for 1 second to 5 hours using a royal treatment or rapid thermal treatment equipment Or by performing a plasma heat treatment.                     

Referring to FIG. 2D, a SiOx layer having a suitable thickness is deposited on the entire surface of the substrate on which the IrOx / Ir / TiN layers 38, 37, and 36 are formed. At this time, it is necessary to consider the thickness for the Ir (37) to exhibit the oxidation preventing property. That is, it is essential that the thickness of SiOx be made larger than the total thickness of IrOx / Ir / TiN (38, 37, 36). That is, the thickness of SiOx is set to about 1000 to 5000 ANGSTROM. Instead of SiOx, SiOx, Si3N4, or the like can be used. As the deposition method, various methods such as chemical vapor deposition, spin-on, physical vapor deposition, and atomic layer deposition can be used.

Referring to FIG. 2E, the surface of the IrOx 38 is exposed using chemical mechanical polishing of SiOx. Even if the chemical mechanical polishing is excessively performed in this step, there is no problem because the IrOx (38) is not chemically mechanically polished. That is, it is very easy to set up a process.

Referring to FIG. 2F, Al2O3 to serve as an etch stop layer 40 is deposited to a proper thickness using a chemical vapor deposition, physical vapor deposition, or atomic layer deposition method to form a concave structure of the capacitor A SiOx layer is vapor-deposited to a proper thickness using the third interlayer insulating layer 41. Here, the thickness of Al 2 O 3 is about 50 to 1000 Å, and the thickness of SiO x is about 5000 to 20000 Å.

Alternatively, instead of Al 2 O 3, SiO 2 and other oxides having excellent etching selectivity may be used instead of Al 2 O 3, and various kinds of Si oxides may be used for SiO x. For the purpose of improving the etch selectivity of Al2O3 deposited by the etch stop layer, the annealing may be performed at a temperature ranging from 300 to 700 ° C. for 1 second to 5 hours by a heat treatment using a furnace or rapid thermal annealing.

Referring to FIG. 2G, SiOx is etched using the third interlayer insulating layer 41, and Al2O3 is deposited as an adhesive layer 42 of the lower electrode of the capacitor by chemical vapor deposition, physical vapor deposition, or atomic layer deposition Deposition is performed using a deposition method.

The over-etching angle is suppressed at the time of etching the third interlayer insulating layer 41 because of Al2O3 deposited by the etching stop layer 40. [ Al2O3 used as the adhesive layer 42 is an adhesive layer necessary because a metal layer such as Pt, Ir, or Ru is used as a capacitor lower electrode. Without this layer, the adhesion characteristics of the underlying SiOx used as the lower electrode and the third interlayer insulating layer 42 are poor, and difficulties arise in the device fabrication process such as lower electrode lifting.

Referring to FIG. 2h, Al2O3 deposited on the adhesive layer is etched back to remove the Al2O3 layer above the plug. If Al2O3 above the plug is removed, electrical flow through the plug is possible, and Al2O3 remains on the sidewall of the third interlayer insulating layer and acts as an adhesive layer of the lower electrode.

Referring to FIG. 2I, a lower electrode is formed only in the interior of the cone by applying an etch-back or a chemical mechanical polishing process after the lower electrode 43 is deposited. The lower electrode is usually made of Pt, Ir, IrOx, Ru, RuOx or the like, or a chemical vapor deposition, physical vapor deposition or atomic layer deposition method is used in combination. Is about 100 to 2000 ANGSTROM.

After the deposition of the lower electrode 43, a heat treatment furnace is used or a rapid thermal annealing or plasma process is used. When the heat treatment is performed in a furnace or in a rapid thermal annealing process, the annealing is performed in an atmosphere of O 2, ozone, N 2, or Ar at a temperature of 200 to 800 ° C. for 10 minutes to 5 hours, Min.

When plasma is used, heat treatment is performed in an atmosphere of O 2, ozone plasma, N 2, N 2 O, or NH 3.

Referring to FIG. 2J, the ferroelectric 44 and the upper electrode 45 are deposited and patterned by applying a general photolithography and etching process. BLT, SBT, SBTN, or PZT may be used for the ferroelectric 44, and one of Pt, Ir, Ru, IrOx, or RuOx may be applied to the upper electrode 45, or two layers The above-described hybrid electrode structure is also possible. The thickness of the ferroelectric layer 44 is about 100 to 2000 angstroms, and the thickness of the upper electrode 45 is about 100 to 4000 angstroms.

Here, the heat treatment temperature of the ferroelectric is about 10 to 5 hours in an atmosphere of O 2, N 2, Ar, ozone (O 3), He, Ne or Kr at about 400 to 800 ° C. The heat treatment equipment uses a diffusion furnace or rapid thermal treatment (RTP).

The manufacture of the above-mentioned concealed capacitors is also applicable to MIM (Metal / Insulator / Metal) capacitor capacitors such as DRAM. In addition to poly-silicon, a TiN plug, a tungsten plug, and the like can be applied to the plug.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be apparent to those of ordinary skill in the art.

In the method of manufacturing a ferroelectric capacitor according to the present invention, a stop layer is added at the time of etching an interlayer insulating layer forming a cone structure to prevent over-etching, thereby making it possible to manufacture a highly stable cone capacitor in a subsequent thermal process.

Claims (6)

Depositing a first interlayer insulating layer on the substrate and forming a contact plug; Forming a diffusion barrier layer on the contact plug; Depositing a second interlayer insulating layer covering the diffusion barrier layer; Chemical mechanical polishing of the second interlayer insulating layer until the diffusion barrier layer is exposed; Depositing Al2O3 as an etch stop layer on the second interlayer insulating layer; Depositing a third interlayer insulating layer on the etch stop layer and forming a hole; Forming an adhesive layer in the hole; And Patterning the lower electrode, the ferroelectric, and the upper electrode over the adhesive layer Wherein the ferroelectric capacitor is a ferroelectric capacitor. The method according to claim 1, Wherein the thickness of the Al2O3 layer is in the range of 50 to 1000 angstroms. The method according to claim 1, Wherein the Al2O3 is one selected from the group consisting of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. 2. A method of manufacturing a ferroelectric capacitor, The method according to claim 1, Wherein a heat treatment using a furnace or a rapid thermal annealing is performed for the purpose of improving the etch selectivity after deposition of the Al2O3. 5. The method of claim 4, Wherein the temperature of the heat treatment is in the range of 300 to 700 占 폚. 5. The method of claim 4, Wherein the time of the heat treatment is in the range of 1 second to 5 hours.

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