JP3142457B2 - Method of manufacturing ferroelectric thin film capacitor - Google Patents
Method of manufacturing ferroelectric thin film capacitorInfo
- Publication number
- JP3142457B2 JP3142457B2 JP07099139A JP9913995A JP3142457B2 JP 3142457 B2 JP3142457 B2 JP 3142457B2 JP 07099139 A JP07099139 A JP 07099139A JP 9913995 A JP9913995 A JP 9913995A JP 3142457 B2 JP3142457 B2 JP 3142457B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- platinum thin
- film
- platinum
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 107
- 239000003990 capacitor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 140
- 229910052697 platinum Inorganic materials 0.000 claims description 70
- 239000010408 film Substances 0.000 claims description 40
- 238000010438 heat treatment Methods 0.000 claims description 19
- 238000002425 crystallisation Methods 0.000 claims description 15
- 230000008025 crystallization Effects 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 238000000034 method Methods 0.000 description 10
- 238000004544 sputter deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000002180 anti-stress Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、強誘電体薄膜をキャ
パシタ絶縁膜として用いた強誘電体薄膜キャパシタの製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ferroelectric thin film capacitor using a ferroelectric thin film as a capacitor insulating film.
【０００２】[0002]
【従来の技術】近年の半導体デバイスにおいて、キャパ
シタ絶縁膜として、従来のシリコン酸化膜やシリコン窒
化膜に代わり、酸化物強誘電体薄膜を用いたデバイスの
応用が注目されている。強誘電体の特徴である高誘電率
や、ヒステリシス特性による残留分極を利用して、大容
量コンデンサや不揮発性機能を有するメモリ等が実現で
きるからである。2. Description of the Related Art In recent semiconductor devices, application of a device using an oxide ferroelectric thin film instead of a conventional silicon oxide film or silicon nitride film as a capacitor insulating film has attracted attention. This is because a large-capacity capacitor, a memory having a non-volatile function, and the like can be realized by utilizing the high dielectric constant and the residual polarization due to the hysteresis characteristic, which are the characteristics of the ferroelectric substance.
【０００３】この酸化物強誘電体薄膜を用いたキャパシ
タは、下電極を形成した後、その上に酸化物強誘電体薄
膜を形成し、さらにその上に上電極を形成することによ
り構成される。酸化物強誘電体薄膜の成膜法としては、
スパッタ法、ゾルゲル法、ＣＶＤ法などが用いられてい
るが、いずれの方法においても堆積された直後の薄膜は
強誘電性を有する結晶にはなっておらず、結晶化するた
めの熱処理が必要である。このため、この結晶化工程
は、通常酸素雰囲気中で６００℃以上の温度で熱処理す
ることにより行われる。A capacitor using this oxide ferroelectric thin film is formed by forming a lower electrode, forming an oxide ferroelectric thin film thereon, and further forming an upper electrode thereon. . As a method of forming an oxide ferroelectric thin film,
A sputtering method, a sol-gel method, a CVD method, etc. are used, but in any method, the thin film immediately after being deposited does not become a crystal having ferroelectricity, and a heat treatment for crystallization is required. is there. Therefore, this crystallization step is usually performed by heat treatment at a temperature of 600 ° C. or more in an oxygen atmosphere.
【０００４】しかし、半導体デバイスのキャパシタ電極
材料として、従来広く利用されているアルミニウム薄膜
や多結晶シリコン薄膜などをキャパシタ電極として用い
ると、前記結晶化工程あるいはキャパシタ形成後のアニ
ール工程時にこれらが酸化され、結果として電極と酸化
物強誘電体薄膜との間に誘電特性の異なる別の絶縁膜が
形成されることになり、所望のキャパシタ特性が得られ
なくなる。However, if an aluminum thin film or a polycrystalline silicon thin film which has been widely used as a capacitor electrode material of a semiconductor device is used as a capacitor electrode, these are oxidized during the crystallization step or the annealing step after forming the capacitor. As a result, another insulating film having different dielectric characteristics is formed between the electrode and the oxide ferroelectric thin film, and desired capacitor characteristics cannot be obtained.
【０００５】このため、酸化物強誘電体薄膜をキャパシ
タ絶縁膜として用いる強誘電体薄膜キャパシタにおいて
は、耐酸化性の強い白金薄膜が広く用いられている。従
来の技術による酸化物強誘電体薄膜キャパシタの製造方
法を図２（ａ）〜（ｃ）に示す工程順の断面図により説
明する。まず図２（ａ）に示すようにシリコン基板１上
にシリコン酸化膜２をＣＶＤ法により１５０ｎｍ堆積し
た後、下電極として白金薄膜３をスパッタ法により３０
０ｎｍ堆積する。次に図２（ｂ）に示すように酸化物強
誘電体薄膜５を、例えばスピン塗布により３００ｎｍ形
成し結晶化した後、図２（ｃ）に示すように上電極とし
て白金薄膜６をスパッタ法により２００ｎｍ堆積する。For this reason, in a ferroelectric thin film capacitor using an oxide ferroelectric thin film as a capacitor insulating film, a platinum thin film having high oxidation resistance is widely used. A method of manufacturing a conventional oxide ferroelectric thin film capacitor will be described with reference to cross-sectional views in the order of steps shown in FIGS. First, as shown in FIG. 2A, a silicon oxide film 2 is deposited on a silicon substrate 1 by a thickness of 150 nm by a CVD method, and then a platinum thin film 3 is formed as a lower electrode by a sputtering method.
Deposit 0 nm. Next, as shown in FIG. 2B, an oxide ferroelectric thin film 5 is formed to a thickness of 300 nm by, for example, spin coating and crystallized, and then, as shown in FIG. To deposit 200 nm.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、従来の
技術による強誘電体薄膜キャパシタの製造方法では、結
晶化工程後、下電極の白金薄膜中に多数の大きな空隙
（以下これをボイドと呼ぶ）が発生し、歩留まりの低下
や信頼性の低下の原因となっている。このボイドは、酸
化物強誘電体薄膜が結晶化する工程において下電極の白
金薄膜が強いストレスを受けることが原因で発生する。However, in the method of manufacturing a ferroelectric thin film capacitor according to the prior art, after the crystallization step, a large number of large voids (hereinafter referred to as voids) are formed in the platinum thin film of the lower electrode. This causes a decrease in yield and a decrease in reliability. The voids are generated due to strong stress applied to the platinum thin film of the lower electrode in the step of crystallizing the oxide ferroelectric thin film.
【０００７】これに対して、酸化物強誘電体薄膜を白金
薄膜上で成膜する前に、通常のスパッタ法で形成した白
金薄膜を高温での熱処理により緻密化しておけば、抗ス
トレス性が強くなりボイドは抑制できる。しかし一方
で、高温での白金薄膜の熱処理は表面に多数のヒロック
を成長させ、キャパシタの絶縁不良等の原因となる。[0007] On the other hand, if the platinum thin film formed by the ordinary sputtering method is densified by a heat treatment at a high temperature before the oxide ferroelectric thin film is formed on the platinum thin film, the anti-stress property is reduced. It becomes stronger and voids can be suppressed. On the other hand, however, heat treatment of the platinum thin film at a high temperature causes a large number of hillocks to grow on the surface and causes insulation failure of the capacitor.
【０００８】したがって、この発明の目的は、従来の問
題点を解決し、白金薄膜の表面にヒロックを形成するこ
となく白金薄膜を緻密化し、強誘電体結晶化工程時に発
生する白金薄膜中のボイドを抑制することができる強誘
電体薄膜キャパシタの製造方法を提供することである。Accordingly, an object of the present invention is to solve the conventional problems and to make a platinum thin film dense without forming hillocks on the surface of the platinum thin film, and to form voids in the platinum thin film generated during a ferroelectric crystallization step. It is an object of the present invention to provide a method for manufacturing a ferroelectric thin-film capacitor capable of suppressing the occurrence of the phenomenon.
【０００９】[0009]
【課題を解決するための手段】請求項１の強誘電体薄膜
キャパシタの製造方法は、半導体基板上にキャパシタの
第１の電極となる白金薄膜を堆積する第１の電極形成工
程と、白金薄膜上の全面に白金薄膜に対して圧縮応力を
もつ膜を堆積する圧縮応力膜形成工程と、白金薄膜およ
び白金薄膜に対して圧縮応力をもつ膜を熱処理する熱処
理工程と、白金薄膜上の白金薄膜に対して圧縮応力をも
つ膜を全面除去し白金薄膜を露出する除去工程と、白金
薄膜上に強誘電体薄膜を堆積し結晶化温度以上で熱処理
を行う強誘電体結晶化工程と、強誘電体薄膜上にキャパ
シタの第２の電極となる白金薄膜を堆積する第２の電極
形成工程とを含むものである。According to a first aspect of the present invention, there is provided a method of manufacturing a ferroelectric thin film capacitor, comprising the steps of: depositing a platinum thin film as a first electrode of a capacitor on a semiconductor substrate; A compressive stress film forming step of depositing a film having a compressive stress on the platinum thin film over the entire surface, a heat treatment step of heat treating the platinum thin film and a film having a compressive stress on the platinum thin film, and a platinum thin film on the platinum thin film A ferroelectric crystallization process in which a ferroelectric thin film is deposited on a platinum thin film and heat-treated at a temperature higher than a crystallization temperature; A second electrode forming step of depositing a platinum thin film serving as a second electrode of the capacitor on the body thin film.
【００１０】[0010]
【作用】請求項１の強誘電体薄膜キャパシタの製造方法
によれば、白金薄膜上に強誘電体薄膜を堆積する前に、
白金薄膜に対して圧縮応力をもつ膜で白金薄膜を覆った
後熱処理し、その後にその膜を除去するようにしたた
め、熱処理により白金薄膜を緻密化することができるの
で強誘電体薄膜の結晶化時のストレスにより発生する白
金薄膜中のボイドの発生を防ぐことができる。しかも、
白金薄膜の熱処理の際に白金薄膜が圧縮応力をもつ膜で
被覆されているため白金薄膜の表面にヒロックを発生す
ることがない。このため、ボイドのない白金電極を有す
る高歩留まりかつ高信頼性の強誘電体キャパシタを供給
することができる。According to the method for manufacturing a ferroelectric thin film capacitor of the first aspect, before depositing the ferroelectric thin film on the platinum thin film,
Heat treatment after covering the platinum thin film with a film having compressive stress on the platinum thin film, and then removing the film, so that the heat treatment can densify the platinum thin film, so crystallization of the ferroelectric thin film It is possible to prevent the occurrence of voids in the platinum thin film caused by stress at the time. Moreover,
Since the platinum thin film is covered with a film having a compressive stress during the heat treatment of the platinum thin film, no hillock is generated on the surface of the platinum thin film. Therefore, a high-yield and highly reliable ferroelectric capacitor having a platinum electrode without voids can be provided.
【００１１】[0011]
【実施例】以下、この発明の一実施例について、図１を
参照しながら説明する。すなわち、図１（ａ）〜（ｅ）
は、半導体装置において、この発明による強誘電体薄膜
キャパシタの製造方法の一実施例における工程順の断面
図を示すものである。図１（ａ）は第１の電極形成工程
後を示し、ＣＭＯＳを含むシリコン基板１上に層間膜と
してシリコン酸化膜２をＣＶＤ法により１５０ｎｍ堆積
し、続いてシリコン酸化膜２上に白金薄膜３をスパッタ
法により３００ｎｍ堆積して、第１の電極を形成する。
図１（ｂ）は圧縮応力膜形成工程後を示し、白金薄膜３
上に白金薄膜３に対して圧縮応力をもつ膜であるシリコ
ン酸化膜４をＬＰ−ＣＶＤ法により２００ｎｍ堆積す
る。つぎに熱処理工程で、白金薄膜２および白金薄膜２
に対して圧縮応力をもつシリコン酸化膜４を、８００℃
の窒素雰囲気中で６０分熱処理する。この熱処理工程に
おいて白金薄膜は、上部にシリコン酸化膜４が形成され
ているためヒロックを発生することはなく、かつ高温の
熱処理による焼きしめ効果で緻密化することができる。
図１（ｃ）は除去工程後を示し、フッ酸溶液によりシリ
コン酸化膜４を除去し、白金薄膜３を露出させる。図１
（ｄ）は白金薄膜３上に強誘電体薄膜を堆積し結晶化温
度以上での熱処理を行う強誘電体結晶化工程後を示し、
強誘電体形成に必要な結晶成分を含む溶液をスピンコー
トにより白金薄膜３上に堆積した後、８００℃の酸素雰
囲気中で結晶化させて、酸化物強誘電体薄膜５を形成す
る。この場合、白金薄膜３の熱処理工程により白金薄膜
３が緻密化されており、この結晶化工程時に白金薄膜３
中にボイドができることはない。図１（ｅ）は第２の電
極形成工程後を示し、酸化物強誘電体薄膜５上に白金薄
膜６をスパッタ法により２００ｎｍ堆積して第２の電極
を形成する。An embodiment of the present invention will be described below with reference to FIG. That is, FIGS. 1 (a) to 1 (e)
1 is a sectional view of a semiconductor device according to an embodiment of a method of manufacturing a ferroelectric thin film capacitor according to the present invention in the order of steps. FIG. 1A shows a state after a first electrode forming step, in which a silicon oxide film 2 is deposited as an interlayer film on a silicon substrate 1 including CMOS by a thickness of 150 nm by a CVD method, and then a platinum thin film 3 is formed on the silicon oxide film 2. Is deposited to a thickness of 300 nm by a sputtering method to form a first electrode.
FIG. 1B shows a state after the compression stress film forming step,
A 200 nm silicon oxide film 4 having a compressive stress on the platinum thin film 3 is deposited thereon by LP-CVD. Next, in a heat treatment step, the platinum thin film 2 and the platinum thin film 2
A silicon oxide film 4 having a compressive stress to
In a nitrogen atmosphere for 60 minutes. In this heat treatment step, the platinum thin film does not generate hillocks because the silicon oxide film 4 is formed thereon, and can be densified by the baking effect of the high-temperature heat treatment.
FIG. 1C shows a state after the removing step, in which the silicon oxide film 4 is removed with a hydrofluoric acid solution to expose the platinum thin film 3. FIG.
(D) shows a state after a ferroelectric crystallization step of depositing a ferroelectric thin film on the platinum thin film 3 and performing a heat treatment at a crystallization temperature or higher,
A solution containing a crystal component necessary for ferroelectric formation is deposited on the platinum thin film 3 by spin coating, and then crystallized in an oxygen atmosphere at 800 ° C. to form an oxide ferroelectric thin film 5. In this case, the platinum thin film 3 is densified by the heat treatment step of the platinum thin film 3, and during the crystallization step, the platinum thin film 3 is densified.
There is no void inside. FIG. 1E shows a state after the second electrode forming step, in which a platinum thin film 6 is deposited on the oxide ferroelectric thin film 5 by a sputtering method to a thickness of 200 nm to form a second electrode.
【００１２】これ以降、実施例では通常の半導体プロセ
スに従い、エッチング、層間膜形成、コンタクトホール
形成、ＡＬ配線形成等の工程を行う。この実施例によれ
ば、白金薄膜３上に強誘電体薄膜５を堆積する前に、白
金薄膜３に対して圧縮応力をもつシリコン酸化膜４で白
金薄膜３を覆った後熱処理し、その後にそのシリコン酸
化膜４を除去するようにしたため、シリコン酸化膜４の
熱膨張係数が白金薄膜３のそれよりも小さいことから、
熱処理により白金薄膜３を緻密化することができるので
強誘電体薄膜５の結晶化時のストレスにより発生する白
金薄膜中のボイドの発生を防ぐことができる。しかも、
白金薄膜３の熱処理の際にシリコン酸化膜４で被覆され
ているため白金薄膜３の表面にヒロックを発生すること
がない。Thereafter, in the embodiment, steps such as etching, formation of an interlayer film, formation of a contact hole, and formation of an AL wiring are performed in accordance with a normal semiconductor process. According to this embodiment, before depositing the ferroelectric thin film 5 on the platinum thin film 3, the platinum thin film 3 is covered with the silicon oxide film 4 having a compressive stress, and then heat-treated. Since the silicon oxide film 4 is removed, since the thermal expansion coefficient of the silicon oxide film 4 is smaller than that of the platinum thin film 3,
Since the platinum thin film 3 can be densified by the heat treatment, it is possible to prevent the generation of voids in the platinum thin film caused by stress during crystallization of the ferroelectric thin film 5. Moreover,
Since the platinum thin film 3 is covered with the silicon oxide film 4 during the heat treatment, no hillock is generated on the surface of the platinum thin film 3.
【００１３】なお、白金薄膜３上のシリコン酸化膜４
は、白金薄膜３に対して圧縮応力をもつ膜であればシリ
コン酸化膜４でなくてもよく、たとえばその他の例とし
て、シリコンナイトライド膜およびチタン酸化膜などが
ある。The silicon oxide film 4 on the platinum thin film 3
The silicon oxide film 4 need not be the silicon oxide film 4 as long as it has a compressive stress with respect to the platinum thin film 3. For example, there are a silicon nitride film and a titanium oxide film.
【００１４】[0014]
【発明の効果】請求項１の強誘電体薄膜キャパシタの製
造方法によれば、白金薄膜上に強誘電体薄膜を堆積する
前に、白金薄膜に対して圧縮応力をもつ膜で白金薄膜を
覆った後熱処理し、その後にその膜を除去するようにし
たため、熱処理により白金薄膜を緻密化することができ
るので強誘電体薄膜の結晶化時のストレスにより発生す
る白金薄膜中のボイドの発生を防ぐことができる。しか
も、白金薄膜の熱処理の際に白金薄膜が圧縮応力をもつ
膜で被覆されているため白金薄膜の表面にヒロックを発
生することがない。このため、ボイドのない白金電極を
有する高歩留まりかつ高信頼性の強誘電体キャパシタを
供給することができるという効果がある。According to the method for manufacturing a ferroelectric thin film capacitor of the present invention, the platinum thin film is covered with a film having a compressive stress on the platinum thin film before the ferroelectric thin film is deposited on the platinum thin film. After the heat treatment, the film is removed thereafter, so that the heat treatment can densify the platinum thin film, thereby preventing the generation of voids in the platinum thin film caused by stress during crystallization of the ferroelectric thin film. be able to. Moreover, since the platinum thin film is covered with a film having a compressive stress during the heat treatment of the platinum thin film, no hillock is generated on the surface of the platinum thin film. Therefore, there is an effect that a high-yield and highly reliable ferroelectric capacitor having a platinum electrode without voids can be supplied.
【図１】この発明の一実施例の半導体装置における強誘
電体薄膜キャパシタの製造方法の工程説明図である。FIG. 1 is a process explanatory view of a method of manufacturing a ferroelectric thin film capacitor in a semiconductor device according to one embodiment of the present invention.
【図２】従来例の強誘電体薄膜キャパシタの製造方法の
工程説明図である。FIG. 2 is a process explanatory view of a method of manufacturing a conventional ferroelectric thin film capacitor.
１ シリコン基板 ２ シリコン酸化膜 ３ 白金薄膜 ４ 白金薄膜に対して圧縮応力をもつ膜であるシリコ
ン酸化膜 ５ 強誘電体薄膜 ６ 白金薄膜REFERENCE SIGNS LIST 1 silicon substrate 2 silicon oxide film 3 platinum thin film 4 silicon oxide film having compressive stress on platinum thin film 5 ferroelectric thin film 6 platinum thin film
フロントページの続き (56)参考文献 特開 平８−222711（ＪＰ，Ａ) 特開 平８−213560（ＪＰ，Ａ) 特開 平７−74324（ＪＰ，Ａ) 特開 平７−22578（ＪＰ，Ａ) 特開 平５−13708（ＪＰ，Ａ) 特開 平５−13726（ＪＰ，Ａ) 特表 平９−501019（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 27/105 H01L 21/285 H01L 21/822 H01L 27/04 Continuation of the front page (56) References JP-A-8-222711 (JP, A) JP-A-8-213560 (JP, A) JP-A-7-74324 (JP, A) JP-A-7-22578 (JP) JP-A-5-13708 (JP, A) JP-A-5-13726 (JP, A) Table 9-9-501019 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB Name) H01L 27/105 H01L 21/285 H01L 21/822 H01L 27/04
Claims (1)
となる白金薄膜を堆積する第１の電極形成工程と、前記
白金薄膜上の全面に前記白金薄膜に対して圧縮応力をも
つ膜を堆積する圧縮応力膜形成工程と、前記白金薄膜お
よび前記白金薄膜に対して圧縮応力をもつ膜を熱処理す
る熱処理工程と、前記白金薄膜上の前記白金薄膜に対し
て圧縮応力をもつ膜を全面除去し前記白金薄膜を露出す
る除去工程と、前記白金薄膜上に強誘電体薄膜を堆積し
結晶化温度以上で熱処理を行う強誘電体結晶化工程と、
前記強誘電体薄膜上にキャパシタの第２の電極となる白
金薄膜を堆積する第２の電極形成工程とを含む強誘電体
薄膜キャパシタの製造方法。1. A first electrode forming step of depositing a platinum thin film to be a first electrode of a capacitor on a semiconductor substrate, and depositing a film having a compressive stress on the platinum thin film over the entire surface of the platinum thin film. Forming a compressive stress film, heat-treating the platinum thin film and a film having a compressive stress on the platinum thin film, and removing the entire film having a compressive stress on the platinum thin film on the platinum thin film. A removing step of exposing the platinum thin film, a ferroelectric crystallization step of depositing a ferroelectric thin film on the platinum thin film and performing a heat treatment at a crystallization temperature or higher,
A second electrode forming step of depositing a platinum thin film serving as a second electrode of the capacitor on the ferroelectric thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07099139A JP3142457B2 (en) | 1995-04-25 | 1995-04-25 | Method of manufacturing ferroelectric thin film capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07099139A JP3142457B2 (en) | 1995-04-25 | 1995-04-25 | Method of manufacturing ferroelectric thin film capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08293580A JPH08293580A (en) | 1996-11-05 |
| JP3142457B2 true JP3142457B2 (en) | 2001-03-07 |
Family
ID=14239383
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07099139A Expired - Fee Related JP3142457B2 (en) | 1995-04-25 | 1995-04-25 | Method of manufacturing ferroelectric thin film capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3142457B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100232223B1 (en) * | 1996-10-24 | 1999-12-01 | 김영환 | Method of fabricating pt thin film for memory |
| KR100434031B1 (en) * | 1996-12-30 | 2004-09-04 | 주식회사 하이닉스반도체 | Method of manufacturing ferroelectric capacitor of semiconductor device to prevent hillock |
| KR20000044603A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for manufacturing platinum upper electrode of ferroelectric capacitor |
| JP4641702B2 (en) * | 2002-11-20 | 2011-03-02 | ソニー株式会社 | Ferroelectric nonvolatile semiconductor memory and manufacturing method thereof |
| WO2008124372A2 (en) | 2007-04-04 | 2008-10-16 | Qualcomm Mems Technologies, Inc. | Eliminate release etch attack by interface modification in sacrificial layers |
-
1995
- 1995-04-25 JP JP07099139A patent/JP3142457B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08293580A (en) | 1996-11-05 |
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